pci.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * pci.c -- esd VME8349 PCI board support.
  4. * Copyright (c) 2006 Wind River Systems, Inc.
  5. * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  6. * Copyright (c) 2009 esd gmbh.
  7. *
  8. * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
  9. *
  10. * Based on MPC8349 PCI support but w/o PIB related code.
  11. */
  12. #include <init.h>
  13. #include <asm/mmu.h>
  14. #include <asm/io.h>
  15. #include <common.h>
  16. #include <mpc83xx.h>
  17. #include <pci.h>
  18. #include <i2c.h>
  19. #include <asm/fsl_i2c.h>
  20. #include "vme8349pin.h"
  21. static struct pci_region pci1_regions[] = {
  22. {
  23. bus_start: CONFIG_SYS_PCI1_MEM_BASE,
  24. phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
  25. size: CONFIG_SYS_PCI1_MEM_SIZE,
  26. flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
  27. },
  28. {
  29. bus_start: CONFIG_SYS_PCI1_IO_BASE,
  30. phys_start: CONFIG_SYS_PCI1_IO_PHYS,
  31. size: CONFIG_SYS_PCI1_IO_SIZE,
  32. flags: PCI_REGION_IO
  33. },
  34. {
  35. bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
  36. phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
  37. size: CONFIG_SYS_PCI1_MMIO_SIZE,
  38. flags: PCI_REGION_MEM
  39. },
  40. };
  41. /*
  42. * pci_init_board()
  43. *
  44. * NOTICE: PCI2 is not supported. There is only one
  45. * physical PCI slot on the board.
  46. *
  47. */
  48. void
  49. pci_init_board(void)
  50. {
  51. volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
  52. volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
  53. volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
  54. struct pci_region *reg[] = { pci1_regions };
  55. u8 reg8;
  56. int monarch = 0;
  57. i2c_set_bus_num(1);
  58. /* Read the PCI_M66EN jumper setting */
  59. if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, 1) == 0) ||
  60. (i2c_read(0x38 , 0, 0, &reg8, 1) == 0)) {
  61. if (reg8 & 0x40) {
  62. clk->occr = 0xff000000; /* 66 MHz PCI */
  63. printf("PCI: 66MHz\n");
  64. } else {
  65. clk->occr = 0xffff0003; /* 33 MHz PCI */
  66. printf("PCI: 33MHz\n");
  67. }
  68. if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
  69. monarch = 1;
  70. } else {
  71. clk->occr = 0xffff0003; /* 33 MHz PCI */
  72. printf("PCI: 33MHz (I2C read failed)\n");
  73. }
  74. udelay(2000);
  75. /*
  76. * Assert/deassert VME reset
  77. */
  78. clrsetbits_be32(&immr->gpio[1].dat,
  79. GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
  80. GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
  81. setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
  82. GPIO2_TSI_POWERUP_RESET_N |
  83. GPIO2_VME_RESET_N |
  84. GPIO2_L_RESET_EN_N);
  85. clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
  86. udelay(200);
  87. setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
  88. udelay(200);
  89. setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
  90. udelay(600000);
  91. clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
  92. /* Configure PCI Local Access Windows */
  93. pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
  94. pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
  95. pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
  96. pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
  97. udelay(2000);
  98. if (monarch == 0) {
  99. mpc83xx_pci_init(1, reg);
  100. } else {
  101. /*
  102. * Release PCI RST Output signal
  103. */
  104. out_be32(&immr->pci_ctrl[0].gcr, 0);
  105. udelay(2000);
  106. out_be32(&immr->pci_ctrl[0].gcr, 1);
  107. }
  108. }