nand.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
  4. */
  5. #include <bouncebuf.h>
  6. #include <common.h>
  7. #include <malloc.h>
  8. #include <nand.h>
  9. #include <asm/io.h>
  10. #include "axs10x.h"
  11. DECLARE_GLOBAL_DATA_PTR;
  12. #define BUS_WIDTH 8 /* AXI data bus width in bytes */
  13. /* DMA buffer descriptor bits & masks */
  14. #define BD_STAT_OWN (1 << 31)
  15. #define BD_STAT_BD_FIRST (1 << 3)
  16. #define BD_STAT_BD_LAST (1 << 2)
  17. #define BD_SIZES_BUFFER1_MASK 0xfff
  18. #define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
  19. /* Controller command flags */
  20. #define B_WFR (1 << 19) /* 1b - Wait for ready */
  21. #define B_LC (1 << 18) /* 1b - Last cycle */
  22. #define B_IWC (1 << 13) /* 1b - Interrupt when complete */
  23. /* NAND cycle types */
  24. #define B_CT_ADDRESS (0x0 << 16) /* Address operation */
  25. #define B_CT_COMMAND (0x1 << 16) /* Command operation */
  26. #define B_CT_WRITE (0x2 << 16) /* Write operation */
  27. #define B_CT_READ (0x3 << 16) /* Write operation */
  28. enum nand_isr_t {
  29. NAND_ISR_DATAREQUIRED = 0,
  30. NAND_ISR_TXUNDERFLOW,
  31. NAND_ISR_TXOVERFLOW,
  32. NAND_ISR_DATAAVAILABLE,
  33. NAND_ISR_RXUNDERFLOW,
  34. NAND_ISR_RXOVERFLOW,
  35. NAND_ISR_TXDMACOMPLETE,
  36. NAND_ISR_RXDMACOMPLETE,
  37. NAND_ISR_DESCRIPTORUNAVAILABLE,
  38. NAND_ISR_CMDDONE,
  39. NAND_ISR_CMDAVAILABLE,
  40. NAND_ISR_CMDERROR,
  41. NAND_ISR_DATATRANSFEROVER,
  42. NAND_ISR_NONE
  43. };
  44. enum nand_regs_t {
  45. AC_FIFO = 0, /* address and command fifo */
  46. IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */
  47. INT_STATUS = 0x118, /* interrupt status register */
  48. INT_CLR_STATUS = 0x120, /* interrupt clear status register */
  49. };
  50. struct nand_bd {
  51. uint32_t status; /* DES0 */
  52. uint32_t sizes; /* DES1 */
  53. uint32_t buffer_ptr0; /* DES2 */
  54. uint32_t buffer_ptr1; /* DES3 */
  55. };
  56. #define NAND_REG_WRITE(r, v) \
  57. writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
  58. #define NAND_REG_READ(r) \
  59. readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
  60. static struct nand_bd *bd; /* DMA buffer descriptors */
  61. /**
  62. * axs101_nand_write_buf - write buffer to chip
  63. * @mtd: MTD device structure
  64. * @buf: data buffer
  65. * @len: number of bytes to write
  66. */
  67. static uint32_t nand_flag_is_set(uint32_t flag)
  68. {
  69. uint32_t reg = NAND_REG_READ(INT_STATUS);
  70. if (reg & (1 << NAND_ISR_CMDERROR))
  71. return 0;
  72. if (reg & (1 << flag)) {
  73. NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
  74. return 1;
  75. }
  76. return 0;
  77. }
  78. /**
  79. * axs101_nand_write_buf - write buffer to chip
  80. * @mtd: MTD device structure
  81. * @buf: data buffer
  82. * @len: number of bytes to write
  83. */
  84. static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
  85. int len)
  86. {
  87. struct bounce_buffer bbstate;
  88. bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
  89. /* Setup buffer descriptor */
  90. writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
  91. writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
  92. writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
  93. writel(0, &bd->buffer_ptr1);
  94. /* Flush modified buffer descriptor */
  95. flush_dcache_range((unsigned long)bd,
  96. (unsigned long)bd + sizeof(struct nand_bd));
  97. /* Issue "write" command */
  98. NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
  99. /* Wait for NAND command and DMA to complete */
  100. while (!nand_flag_is_set(NAND_ISR_CMDDONE))
  101. ;
  102. while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
  103. ;
  104. bounce_buffer_stop(&bbstate);
  105. }
  106. /**
  107. * axs101_nand_read_buf - read chip data into buffer
  108. * @mtd: MTD device structure
  109. * @buf: buffer to store data
  110. * @len: number of bytes to read
  111. */
  112. static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
  113. {
  114. struct bounce_buffer bbstate;
  115. bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
  116. /* Setup buffer descriptor */
  117. writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
  118. writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
  119. writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
  120. writel(0, &bd->buffer_ptr1);
  121. /* Flush modified buffer descriptor */
  122. flush_dcache_range((unsigned long)bd,
  123. (unsigned long)bd + sizeof(struct nand_bd));
  124. /* Issue "read" command */
  125. NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
  126. /* Wait for NAND command and DMA to complete */
  127. while (!nand_flag_is_set(NAND_ISR_CMDDONE))
  128. ;
  129. while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
  130. ;
  131. bounce_buffer_stop(&bbstate);
  132. }
  133. /**
  134. * axs101_nand_read_byte - read one byte from the chip
  135. * @mtd: MTD device structure
  136. */
  137. static u_char axs101_nand_read_byte(struct mtd_info *mtd)
  138. {
  139. u8 byte;
  140. axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
  141. return byte;
  142. }
  143. /**
  144. * axs101_nand_read_word - read one word from the chip
  145. * @mtd: MTD device structure
  146. */
  147. static u16 axs101_nand_read_word(struct mtd_info *mtd)
  148. {
  149. u16 word;
  150. axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
  151. return word;
  152. }
  153. /**
  154. * axs101_nand_hwcontrol - NAND control functions wrapper.
  155. * @mtd: MTD device structure
  156. * @cmd: Command
  157. */
  158. static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
  159. unsigned int ctrl)
  160. {
  161. if (cmd == NAND_CMD_NONE)
  162. return;
  163. cmd = cmd & 0xff;
  164. switch (ctrl & (NAND_ALE | NAND_CLE)) {
  165. /* Address */
  166. case NAND_ALE:
  167. cmd |= B_CT_ADDRESS;
  168. break;
  169. /* Command */
  170. case NAND_CLE:
  171. cmd |= B_CT_COMMAND | B_WFR;
  172. break;
  173. default:
  174. debug("%s: unknown ctrl %#x\n", __func__, ctrl);
  175. }
  176. NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
  177. while (!nand_flag_is_set(NAND_ISR_CMDDONE))
  178. ;
  179. }
  180. int board_nand_init(struct nand_chip *nand)
  181. {
  182. bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
  183. sizeof(struct nand_bd));
  184. /* Set buffer descriptor address in IDMAC */
  185. NAND_REG_WRITE(IDMAC_BDADDR, bd);
  186. nand->ecc.mode = NAND_ECC_SOFT;
  187. nand->cmd_ctrl = axs101_nand_hwcontrol;
  188. nand->read_byte = axs101_nand_read_byte;
  189. nand->read_word = axs101_nand_read_word;
  190. nand->write_buf = axs101_nand_write_buf;
  191. nand->read_buf = axs101_nand_read_buf;
  192. /* MBv3 has NAND IC with 16-bit data bus */
  193. if (gd->board_type == AXS_MB_V3)
  194. nand->options |= NAND_BUSWIDTH_16;
  195. return 0;
  196. }