sh_i2c.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011, 2013 Renesas Solutions Corp.
  4. * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  5. *
  6. * NOTE: This driver should be converted to driver model before June 2017.
  7. * Please see doc/driver-model/i2c-howto.rst for instructions.
  8. */
  9. #include <common.h>
  10. #include <i2c.h>
  11. #include <asm/io.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. /* Every register is 32bit aligned, but only 8bits in size */
  14. #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1;
  15. struct sh_i2c {
  16. ureg(icdr);
  17. ureg(iccr);
  18. ureg(icsr);
  19. ureg(icic);
  20. ureg(iccl);
  21. ureg(icch);
  22. };
  23. #undef ureg
  24. /* ICCR */
  25. #define SH_I2C_ICCR_ICE (1 << 7)
  26. #define SH_I2C_ICCR_RACK (1 << 6)
  27. #define SH_I2C_ICCR_RTS (1 << 4)
  28. #define SH_I2C_ICCR_BUSY (1 << 2)
  29. #define SH_I2C_ICCR_SCP (1 << 0)
  30. /* ICSR / ICIC */
  31. #define SH_IC_BUSY (1 << 4)
  32. #define SH_IC_TACK (1 << 2)
  33. #define SH_IC_WAIT (1 << 1)
  34. #define SH_IC_DTE (1 << 0)
  35. #ifdef CONFIG_SH_I2C_8BIT
  36. /* store 8th bit of iccl and icch in ICIC register */
  37. #define SH_I2C_ICIC_ICCLB8 (1 << 7)
  38. #define SH_I2C_ICIC_ICCHB8 (1 << 6)
  39. #endif
  40. static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = {
  41. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0,
  42. #ifdef CONFIG_SYS_I2C_SH_BASE1
  43. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1,
  44. #endif
  45. #ifdef CONFIG_SYS_I2C_SH_BASE2
  46. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2,
  47. #endif
  48. #ifdef CONFIG_SYS_I2C_SH_BASE3
  49. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3,
  50. #endif
  51. #ifdef CONFIG_SYS_I2C_SH_BASE4
  52. (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4,
  53. #endif
  54. };
  55. static u16 iccl, icch;
  56. #define IRQ_WAIT 1000
  57. static void sh_irq_dte(struct sh_i2c *dev)
  58. {
  59. int i;
  60. for (i = 0; i < IRQ_WAIT; i++) {
  61. if (SH_IC_DTE & readb(&dev->icsr))
  62. break;
  63. udelay(10);
  64. }
  65. }
  66. static int sh_irq_dte_with_tack(struct sh_i2c *dev)
  67. {
  68. int i;
  69. for (i = 0; i < IRQ_WAIT; i++) {
  70. if (SH_IC_DTE & readb(&dev->icsr))
  71. break;
  72. if (SH_IC_TACK & readb(&dev->icsr))
  73. return -1;
  74. udelay(10);
  75. }
  76. return 0;
  77. }
  78. static void sh_irq_busy(struct sh_i2c *dev)
  79. {
  80. int i;
  81. for (i = 0; i < IRQ_WAIT; i++) {
  82. if (!(SH_IC_BUSY & readb(&dev->icsr)))
  83. break;
  84. udelay(10);
  85. }
  86. }
  87. static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop)
  88. {
  89. u8 icic = SH_IC_TACK;
  90. debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n",
  91. __func__, chip, addr, iccl, icch);
  92. clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  93. setbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  94. writeb(iccl & 0xff, &dev->iccl);
  95. writeb(icch & 0xff, &dev->icch);
  96. #ifdef CONFIG_SH_I2C_8BIT
  97. if (iccl > 0xff)
  98. icic |= SH_I2C_ICIC_ICCLB8;
  99. if (icch > 0xff)
  100. icic |= SH_I2C_ICIC_ICCHB8;
  101. #endif
  102. writeb(icic, &dev->icic);
  103. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
  104. sh_irq_dte(dev);
  105. clrbits_8(&dev->icsr, SH_IC_TACK);
  106. writeb(chip << 1, &dev->icdr);
  107. if (sh_irq_dte_with_tack(dev) != 0)
  108. return -1;
  109. writeb(addr, &dev->icdr);
  110. if (stop)
  111. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr);
  112. if (sh_irq_dte_with_tack(dev) != 0)
  113. return -1;
  114. return 0;
  115. }
  116. static void sh_i2c_finish(struct sh_i2c *dev)
  117. {
  118. writeb(0, &dev->icsr);
  119. clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE);
  120. }
  121. static int
  122. sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val)
  123. {
  124. int ret = -1;
  125. if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
  126. goto exit0;
  127. udelay(10);
  128. writeb(val, &dev->icdr);
  129. if (sh_irq_dte_with_tack(dev) != 0)
  130. goto exit0;
  131. writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr);
  132. if (sh_irq_dte_with_tack(dev) != 0)
  133. goto exit0;
  134. sh_irq_busy(dev);
  135. ret = 0;
  136. exit0:
  137. sh_i2c_finish(dev);
  138. return ret;
  139. }
  140. static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr)
  141. {
  142. int ret = -1;
  143. #if defined(CONFIG_SH73A0)
  144. if (sh_i2c_set_addr(dev, chip, addr, 0) != 0)
  145. goto exit0;
  146. #else
  147. if (sh_i2c_set_addr(dev, chip, addr, 1) != 0)
  148. goto exit0;
  149. udelay(100);
  150. #endif
  151. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr);
  152. sh_irq_dte(dev);
  153. writeb(chip << 1 | 0x01, &dev->icdr);
  154. if (sh_irq_dte_with_tack(dev) != 0)
  155. goto exit0;
  156. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr);
  157. if (sh_irq_dte_with_tack(dev) != 0)
  158. goto exit0;
  159. ret = readb(&dev->icdr) & 0xff;
  160. writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr);
  161. readb(&dev->icdr); /* Dummy read */
  162. sh_irq_busy(dev);
  163. exit0:
  164. sh_i2c_finish(dev);
  165. return ret;
  166. }
  167. static void
  168. sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  169. {
  170. int num, denom, tmp;
  171. /* No i2c support prior to relocation */
  172. if (!(gd->flags & GD_FLG_RELOC))
  173. return;
  174. /*
  175. * Calculate the value for iccl. From the data sheet:
  176. * iccl = (p-clock / transfer-rate) * (L / (L + H))
  177. * where L and H are the SCL low and high ratio.
  178. */
  179. num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW;
  180. denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
  181. tmp = num * 10 / denom;
  182. if (tmp % 10 >= 5)
  183. iccl = (u16)((num/denom) + 1);
  184. else
  185. iccl = (u16)(num/denom);
  186. /* Calculate the value for icch. From the data sheet:
  187. icch = (p clock / transfer rate) * (H / (L + H)) */
  188. num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
  189. tmp = num * 10 / denom;
  190. if (tmp % 10 >= 5)
  191. icch = (u16)((num/denom) + 1);
  192. else
  193. icch = (u16)(num/denom);
  194. debug("clock: %d, speed %d, iccl: %x, icch: %x\n",
  195. CONFIG_SH_I2C_CLOCK, speed, iccl, icch);
  196. }
  197. static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  198. uint addr, int alen, u8 *data, int len)
  199. {
  200. int ret, i;
  201. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  202. for (i = 0; i < len; i++) {
  203. ret = sh_i2c_raw_read(dev, chip, addr + i);
  204. if (ret < 0)
  205. return -1;
  206. data[i] = ret & 0xff;
  207. debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
  208. }
  209. return 0;
  210. }
  211. static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr,
  212. int alen, u8 *data, int len)
  213. {
  214. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  215. int i;
  216. for (i = 0; i < len; i++) {
  217. debug("%s: data[%d]: %02x\n", __func__, i, data[i]);
  218. if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0)
  219. return -1;
  220. }
  221. return 0;
  222. }
  223. static int
  224. sh_i2c_probe(struct i2c_adapter *adap, u8 dev)
  225. {
  226. u8 dummy[1];
  227. return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy);
  228. }
  229. static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap,
  230. unsigned int speed)
  231. {
  232. struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr];
  233. sh_i2c_finish(dev);
  234. sh_i2c_init(adap, speed, 0);
  235. return 0;
  236. }
  237. /*
  238. * Register RCAR i2c adapters
  239. */
  240. U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  241. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0)
  242. #ifdef CONFIG_SYS_I2C_SH_BASE1
  243. U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  244. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1)
  245. #endif
  246. #ifdef CONFIG_SYS_I2C_SH_BASE2
  247. U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  248. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2)
  249. #endif
  250. #ifdef CONFIG_SYS_I2C_SH_BASE3
  251. U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  252. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3)
  253. #endif
  254. #ifdef CONFIG_SYS_I2C_SH_BASE4
  255. U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read,
  256. sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4)
  257. #endif