kona_i2c.c 18 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Broadcom Corporation.
  4. *
  5. * NOTE: This driver should be converted to driver model before June 2017.
  6. * Please see doc/driver-model/i2c-howto.rst for instructions.
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <linux/errno.h>
  11. #include <asm/arch/sysmap.h>
  12. #include <asm/kona-common/clk.h>
  13. #include <i2c.h>
  14. /* Hardware register offsets and field defintions */
  15. #define CS_OFFSET 0x00000020
  16. #define CS_ACK_SHIFT 3
  17. #define CS_ACK_MASK 0x00000008
  18. #define CS_ACK_CMD_GEN_START 0x00000000
  19. #define CS_ACK_CMD_GEN_RESTART 0x00000001
  20. #define CS_CMD_SHIFT 1
  21. #define CS_CMD_CMD_NO_ACTION 0x00000000
  22. #define CS_CMD_CMD_START_RESTART 0x00000001
  23. #define CS_CMD_CMD_STOP 0x00000002
  24. #define CS_EN_SHIFT 0
  25. #define CS_EN_CMD_ENABLE_BSC 0x00000001
  26. #define TIM_OFFSET 0x00000024
  27. #define TIM_PRESCALE_SHIFT 6
  28. #define TIM_P_SHIFT 3
  29. #define TIM_NO_DIV_SHIFT 2
  30. #define TIM_DIV_SHIFT 0
  31. #define DAT_OFFSET 0x00000028
  32. #define TOUT_OFFSET 0x0000002c
  33. #define TXFCR_OFFSET 0x0000003c
  34. #define TXFCR_FIFO_FLUSH_MASK 0x00000080
  35. #define TXFCR_FIFO_EN_MASK 0x00000040
  36. #define IER_OFFSET 0x00000044
  37. #define IER_READ_COMPLETE_INT_MASK 0x00000010
  38. #define IER_I2C_INT_EN_MASK 0x00000008
  39. #define IER_FIFO_INT_EN_MASK 0x00000002
  40. #define IER_NOACK_EN_MASK 0x00000001
  41. #define ISR_OFFSET 0x00000048
  42. #define ISR_RESERVED_MASK 0xffffff60
  43. #define ISR_CMDBUSY_MASK 0x00000080
  44. #define ISR_READ_COMPLETE_MASK 0x00000010
  45. #define ISR_SES_DONE_MASK 0x00000008
  46. #define ISR_ERR_MASK 0x00000004
  47. #define ISR_TXFIFOEMPTY_MASK 0x00000002
  48. #define ISR_NOACK_MASK 0x00000001
  49. #define CLKEN_OFFSET 0x0000004c
  50. #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
  51. #define CLKEN_M_SHIFT 4
  52. #define CLKEN_N_SHIFT 1
  53. #define CLKEN_CLKEN_MASK 0x00000001
  54. #define FIFO_STATUS_OFFSET 0x00000054
  55. #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
  56. #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
  57. #define HSTIM_OFFSET 0x00000058
  58. #define HSTIM_HS_MODE_MASK 0x00008000
  59. #define HSTIM_HS_HOLD_SHIFT 10
  60. #define HSTIM_HS_HIGH_PHASE_SHIFT 5
  61. #define HSTIM_HS_SETUP_SHIFT 0
  62. #define PADCTL_OFFSET 0x0000005c
  63. #define PADCTL_PAD_OUT_EN_MASK 0x00000004
  64. #define RXFCR_OFFSET 0x00000068
  65. #define RXFCR_NACK_EN_SHIFT 7
  66. #define RXFCR_READ_COUNT_SHIFT 0
  67. #define RXFIFORDOUT_OFFSET 0x0000006c
  68. /* Locally used constants */
  69. #define MAX_RX_FIFO_SIZE 64U /* bytes */
  70. #define MAX_TX_FIFO_SIZE 64U /* bytes */
  71. #define I2C_TIMEOUT 100000 /* usecs */
  72. #define WAIT_INT_CHK 100 /* usecs */
  73. #if I2C_TIMEOUT % WAIT_INT_CHK
  74. #error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
  75. #endif
  76. /* Operations that can be commanded to the controller */
  77. enum bcm_kona_cmd_t {
  78. BCM_CMD_NOACTION = 0,
  79. BCM_CMD_START,
  80. BCM_CMD_RESTART,
  81. BCM_CMD_STOP,
  82. };
  83. /* Internal divider settings for standard mode, fast mode and fast mode plus */
  84. struct bus_speed_cfg {
  85. uint8_t time_m; /* Number of cycles for setup time */
  86. uint8_t time_n; /* Number of cycles for hold time */
  87. uint8_t prescale; /* Prescale divider */
  88. uint8_t time_p; /* Timing coefficient */
  89. uint8_t no_div; /* Disable clock divider */
  90. uint8_t time_div; /* Post-prescale divider */
  91. };
  92. static const struct bus_speed_cfg std_cfg_table[] = {
  93. [IC_SPEED_MODE_STANDARD] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
  94. [IC_SPEED_MODE_FAST] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
  95. [IC_SPEED_MODE_FAST_PLUS] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
  96. };
  97. struct bcm_kona_i2c_dev {
  98. void *base;
  99. uint speed;
  100. const struct bus_speed_cfg *std_cfg;
  101. };
  102. /* Keep these two defines in sync */
  103. #define DEF_SPD I2C_SPEED_STANDARD_RATE
  104. #define DEF_SPD_ENUM IC_SPEED_MODE_STANDARD
  105. #define DEF_DEVICE(num) \
  106. {(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
  107. static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
  108. #ifdef CONFIG_SYS_I2C_BASE0
  109. DEF_DEVICE(0),
  110. #endif
  111. #ifdef CONFIG_SYS_I2C_BASE1
  112. DEF_DEVICE(1),
  113. #endif
  114. #ifdef CONFIG_SYS_I2C_BASE2
  115. DEF_DEVICE(2),
  116. #endif
  117. #ifdef CONFIG_SYS_I2C_BASE3
  118. DEF_DEVICE(3),
  119. #endif
  120. #ifdef CONFIG_SYS_I2C_BASE4
  121. DEF_DEVICE(4),
  122. #endif
  123. #ifdef CONFIG_SYS_I2C_BASE5
  124. DEF_DEVICE(5),
  125. #endif
  126. };
  127. #define I2C_M_TEN 0x0010 /* ten bit address */
  128. #define I2C_M_RD 0x0001 /* read data */
  129. #define I2C_M_NOSTART 0x4000 /* no restart between msgs */
  130. struct kona_i2c_msg {
  131. uint16_t addr;
  132. uint16_t flags;
  133. uint16_t len;
  134. uint8_t *buf;
  135. };
  136. static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
  137. enum bcm_kona_cmd_t cmd)
  138. {
  139. debug("%s, %d\n", __func__, cmd);
  140. switch (cmd) {
  141. case BCM_CMD_NOACTION:
  142. writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
  143. (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
  144. dev->base + CS_OFFSET);
  145. break;
  146. case BCM_CMD_START:
  147. writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
  148. (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
  149. (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
  150. dev->base + CS_OFFSET);
  151. break;
  152. case BCM_CMD_RESTART:
  153. writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
  154. (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
  155. (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
  156. dev->base + CS_OFFSET);
  157. break;
  158. case BCM_CMD_STOP:
  159. writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
  160. (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
  161. dev->base + CS_OFFSET);
  162. break;
  163. default:
  164. printf("Unknown command %d\n", cmd);
  165. }
  166. }
  167. static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
  168. {
  169. writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
  170. dev->base + CLKEN_OFFSET);
  171. }
  172. static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
  173. {
  174. writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
  175. dev->base + CLKEN_OFFSET);
  176. }
  177. /* Wait until at least one of the mask bit(s) are set */
  178. static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
  179. unsigned long time_left,
  180. uint32_t mask)
  181. {
  182. uint32_t status;
  183. while (time_left) {
  184. status = readl(dev->base + ISR_OFFSET);
  185. if ((status & ~ISR_RESERVED_MASK) == 0) {
  186. debug("Bogus I2C interrupt 0x%x\n", status);
  187. continue;
  188. }
  189. /* Must flush the TX FIFO when NAK detected */
  190. if (status & ISR_NOACK_MASK)
  191. writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
  192. dev->base + TXFCR_OFFSET);
  193. writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
  194. if (status & mask) {
  195. /* We are done since one of the mask bits are set */
  196. return time_left;
  197. }
  198. udelay(WAIT_INT_CHK);
  199. time_left -= WAIT_INT_CHK;
  200. }
  201. return 0;
  202. }
  203. /* Send command to I2C bus */
  204. static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
  205. enum bcm_kona_cmd_t cmd)
  206. {
  207. int rc = 0;
  208. unsigned long time_left = I2C_TIMEOUT;
  209. /* Send the command */
  210. bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
  211. /* Wait for transaction to finish or timeout */
  212. time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
  213. if (!time_left) {
  214. printf("controller timed out\n");
  215. rc = -ETIMEDOUT;
  216. }
  217. /* Clear command */
  218. bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
  219. return rc;
  220. }
  221. /* Read a single RX FIFO worth of data from the i2c bus */
  222. static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
  223. uint8_t *buf, unsigned int len,
  224. unsigned int last_byte_nak)
  225. {
  226. unsigned long time_left = I2C_TIMEOUT;
  227. /* Start the RX FIFO */
  228. writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
  229. (len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
  230. /* Wait for FIFO read to complete */
  231. time_left =
  232. wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
  233. if (!time_left) {
  234. printf("RX FIFO time out\n");
  235. return -EREMOTEIO;
  236. }
  237. /* Read data from FIFO */
  238. for (; len > 0; len--, buf++)
  239. *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
  240. return 0;
  241. }
  242. /* Read any amount of data using the RX FIFO from the i2c bus */
  243. static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
  244. struct kona_i2c_msg *msg)
  245. {
  246. unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
  247. unsigned int last_byte_nak = 0;
  248. unsigned int bytes_read = 0;
  249. int rc;
  250. uint8_t *tmp_buf = msg->buf;
  251. while (bytes_read < msg->len) {
  252. if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
  253. last_byte_nak = 1; /* NAK last byte of transfer */
  254. bytes_to_read = msg->len - bytes_read;
  255. }
  256. rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
  257. last_byte_nak);
  258. if (rc < 0)
  259. return -EREMOTEIO;
  260. bytes_read += bytes_to_read;
  261. tmp_buf += bytes_to_read;
  262. }
  263. return 0;
  264. }
  265. /* Write a single byte of data to the i2c bus */
  266. static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
  267. unsigned int nak_expected)
  268. {
  269. unsigned long time_left = I2C_TIMEOUT;
  270. unsigned int nak_received;
  271. /* Clear pending session done interrupt */
  272. writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
  273. /* Send one byte of data */
  274. writel(data, dev->base + DAT_OFFSET);
  275. time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
  276. if (!time_left) {
  277. debug("controller timed out\n");
  278. return -ETIMEDOUT;
  279. }
  280. nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
  281. if (nak_received ^ nak_expected) {
  282. debug("unexpected NAK/ACK\n");
  283. return -EREMOTEIO;
  284. }
  285. return 0;
  286. }
  287. /* Write a single TX FIFO worth of data to the i2c bus */
  288. static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
  289. uint8_t *buf, unsigned int len)
  290. {
  291. int k;
  292. unsigned long time_left = I2C_TIMEOUT;
  293. unsigned int fifo_status;
  294. /* Write data into FIFO */
  295. for (k = 0; k < len; k++)
  296. writel(buf[k], (dev->base + DAT_OFFSET));
  297. /* Wait for FIFO to empty */
  298. do {
  299. time_left =
  300. wait_for_int_timeout(dev, time_left,
  301. (IER_FIFO_INT_EN_MASK |
  302. IER_NOACK_EN_MASK));
  303. fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
  304. } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
  305. /* Check if there was a NAK */
  306. if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
  307. printf("unexpected NAK\n");
  308. return -EREMOTEIO;
  309. }
  310. /* Check if a timeout occurred */
  311. if (!time_left) {
  312. printf("completion timed out\n");
  313. return -EREMOTEIO;
  314. }
  315. return 0;
  316. }
  317. /* Write any amount of data using TX FIFO to the i2c bus */
  318. static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
  319. struct kona_i2c_msg *msg)
  320. {
  321. unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
  322. unsigned int bytes_written = 0;
  323. int rc;
  324. uint8_t *tmp_buf = msg->buf;
  325. while (bytes_written < msg->len) {
  326. if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
  327. bytes_to_write = msg->len - bytes_written;
  328. rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
  329. bytes_to_write);
  330. if (rc < 0)
  331. return -EREMOTEIO;
  332. bytes_written += bytes_to_write;
  333. tmp_buf += bytes_to_write;
  334. }
  335. return 0;
  336. }
  337. /* Send i2c address */
  338. static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
  339. struct kona_i2c_msg *msg)
  340. {
  341. unsigned char addr;
  342. if (msg->flags & I2C_M_TEN) {
  343. /* First byte is 11110XX0 where XX is upper 2 bits */
  344. addr = 0xf0 | ((msg->addr & 0x300) >> 7);
  345. if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
  346. return -EREMOTEIO;
  347. /* Second byte is the remaining 8 bits */
  348. addr = msg->addr & 0xff;
  349. if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
  350. return -EREMOTEIO;
  351. if (msg->flags & I2C_M_RD) {
  352. /* For read, send restart command */
  353. if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
  354. return -EREMOTEIO;
  355. /* Then re-send the first byte with the read bit set */
  356. addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
  357. if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
  358. return -EREMOTEIO;
  359. }
  360. } else {
  361. addr = msg->addr << 1;
  362. if (msg->flags & I2C_M_RD)
  363. addr |= 1;
  364. if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
  365. return -EREMOTEIO;
  366. }
  367. return 0;
  368. }
  369. static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
  370. {
  371. writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
  372. dev->base + CLKEN_OFFSET);
  373. }
  374. static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
  375. {
  376. writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
  377. dev->base + HSTIM_OFFSET);
  378. writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
  379. (dev->std_cfg->time_p << TIM_P_SHIFT) |
  380. (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
  381. (dev->std_cfg->time_div << TIM_DIV_SHIFT),
  382. dev->base + TIM_OFFSET);
  383. writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
  384. (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
  385. CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
  386. }
  387. /* Master transfer function */
  388. static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
  389. struct kona_i2c_msg msgs[], int num)
  390. {
  391. struct kona_i2c_msg *pmsg;
  392. int rc = 0;
  393. int i;
  394. /* Enable pad output */
  395. writel(0, dev->base + PADCTL_OFFSET);
  396. /* Enable internal clocks */
  397. bcm_kona_i2c_enable_clock(dev);
  398. /* Send start command */
  399. rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
  400. if (rc < 0) {
  401. printf("Start command failed rc = %d\n", rc);
  402. goto xfer_disable_pad;
  403. }
  404. /* Loop through all messages */
  405. for (i = 0; i < num; i++) {
  406. pmsg = &msgs[i];
  407. /* Send restart for subsequent messages */
  408. if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
  409. rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
  410. if (rc < 0) {
  411. printf("restart cmd failed rc = %d\n", rc);
  412. goto xfer_send_stop;
  413. }
  414. }
  415. /* Send slave address */
  416. if (!(pmsg->flags & I2C_M_NOSTART)) {
  417. rc = bcm_kona_i2c_do_addr(dev, pmsg);
  418. if (rc < 0) {
  419. debug("NAK from addr %2.2x msg#%d rc = %d\n",
  420. pmsg->addr, i, rc);
  421. goto xfer_send_stop;
  422. }
  423. }
  424. /* Perform data transfer */
  425. if (pmsg->flags & I2C_M_RD) {
  426. rc = bcm_kona_i2c_read_fifo(dev, pmsg);
  427. if (rc < 0) {
  428. printf("read failure\n");
  429. goto xfer_send_stop;
  430. }
  431. } else {
  432. rc = bcm_kona_i2c_write_fifo(dev, pmsg);
  433. if (rc < 0) {
  434. printf("write failure");
  435. goto xfer_send_stop;
  436. }
  437. }
  438. }
  439. rc = num;
  440. xfer_send_stop:
  441. /* Send a STOP command */
  442. bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
  443. xfer_disable_pad:
  444. /* Disable pad output */
  445. writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
  446. /* Stop internal clock */
  447. bcm_kona_i2c_disable_clock(dev);
  448. return rc;
  449. }
  450. static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
  451. uint speed)
  452. {
  453. switch (speed) {
  454. case I2C_SPEED_STANDARD_RATE:
  455. dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_STANDARD];
  456. break;
  457. case I2C_SPEED_FAST_RATE:
  458. dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST];
  459. break;
  460. case I2C_SPEED_FAST_PLUS_RATE:
  461. dev->std_cfg = &std_cfg_table[IC_SPEED_MODE_FAST_PLUS];
  462. break;
  463. default:
  464. printf("%d hz bus speed not supported\n", speed);
  465. return -EINVAL;
  466. }
  467. dev->speed = speed;
  468. return 0;
  469. }
  470. static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
  471. {
  472. /* Parse bus speed */
  473. bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
  474. /* Enable internal clocks */
  475. bcm_kona_i2c_enable_clock(dev);
  476. /* Configure internal dividers */
  477. bcm_kona_i2c_config_timing(dev);
  478. /* Disable timeout */
  479. writel(0, dev->base + TOUT_OFFSET);
  480. /* Enable autosense */
  481. bcm_kona_i2c_enable_autosense(dev);
  482. /* Enable TX FIFO */
  483. writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
  484. dev->base + TXFCR_OFFSET);
  485. /* Mask all interrupts */
  486. writel(0, dev->base + IER_OFFSET);
  487. /* Clear all pending interrupts */
  488. writel(ISR_CMDBUSY_MASK |
  489. ISR_READ_COMPLETE_MASK |
  490. ISR_SES_DONE_MASK |
  491. ISR_ERR_MASK |
  492. ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
  493. /* Enable the controller but leave it idle */
  494. bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
  495. /* Disable pad output */
  496. writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
  497. }
  498. /*
  499. * uboot layer
  500. */
  501. struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
  502. {
  503. return &g_i2c_devs[adap->hwadapnr];
  504. }
  505. static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  506. {
  507. struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
  508. if (clk_bsc_enable(dev->base))
  509. return;
  510. bcm_kona_i2c_init(dev);
  511. }
  512. static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
  513. int alen, uchar *buffer, int len)
  514. {
  515. /* msg[0] writes the addr, msg[1] reads the data */
  516. struct kona_i2c_msg msg[2];
  517. unsigned char msgbuf0[64];
  518. struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
  519. msg[0].addr = chip;
  520. msg[0].flags = 0;
  521. msg[0].len = 1;
  522. msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */
  523. msg[1].addr = chip;
  524. msg[1].flags = I2C_M_RD;
  525. /* msg[1].buf dest ptr increments each read */
  526. msgbuf0[0] = (unsigned char)addr;
  527. msg[1].buf = buffer;
  528. msg[1].len = len;
  529. if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
  530. /* Sending 2 i2c messages */
  531. kona_i2c_init(adap, adap->speed, adap->slaveaddr);
  532. debug("I2C read: I/O error\n");
  533. return -EIO;
  534. }
  535. return 0;
  536. }
  537. static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
  538. int alen, uchar *buffer, int len)
  539. {
  540. struct kona_i2c_msg msg[1];
  541. unsigned char msgbuf0[64];
  542. unsigned int i;
  543. struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
  544. msg[0].addr = chip;
  545. msg[0].flags = 0;
  546. msg[0].len = 2; /* addr byte plus data */
  547. msg[0].buf = msgbuf0;
  548. for (i = 0; i < len; i++) {
  549. msgbuf0[0] = addr++;
  550. msgbuf0[1] = buffer[i];
  551. if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
  552. kona_i2c_init(adap, adap->speed, adap->slaveaddr);
  553. debug("I2C write: I/O error\n");
  554. return -EIO;
  555. }
  556. }
  557. return 0;
  558. }
  559. static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
  560. {
  561. uchar tmp;
  562. /*
  563. * read addr 0x0 of the given chip.
  564. */
  565. return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
  566. }
  567. static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  568. {
  569. struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
  570. return bcm_kona_i2c_assign_bus_speed(dev, speed);
  571. }
  572. /*
  573. * Register kona i2c adapters. Keep the order below so
  574. * that the bus number matches the adapter number.
  575. */
  576. #define DEF_ADAPTER(num) \
  577. U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
  578. kona_i2c_read, kona_i2c_write, \
  579. kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
  580. #ifdef CONFIG_SYS_I2C_BASE0
  581. DEF_ADAPTER(0)
  582. #endif
  583. #ifdef CONFIG_SYS_I2C_BASE1
  584. DEF_ADAPTER(1)
  585. #endif
  586. #ifdef CONFIG_SYS_I2C_BASE2
  587. DEF_ADAPTER(2)
  588. #endif
  589. #ifdef CONFIG_SYS_I2C_BASE3
  590. DEF_ADAPTER(3)
  591. #endif
  592. #ifdef CONFIG_SYS_I2C_BASE4
  593. DEF_ADAPTER(4)
  594. #endif
  595. #ifdef CONFIG_SYS_I2C_BASE5
  596. DEF_ADAPTER(5)
  597. #endif