davinci_i2c.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * TI DaVinci (TMS320DM644x) I2C driver.
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
  8. * --------------------------------------------------------
  9. *
  10. * NOTE: This driver should be converted to driver model before June 2017.
  11. * Please see doc/driver-model/i2c-howto.rst for instructions.
  12. */
  13. #include <common.h>
  14. #include <i2c.h>
  15. #include <dm.h>
  16. #include <asm/arch/hardware.h>
  17. #include <asm/arch/i2c_defs.h>
  18. #include <asm/io.h>
  19. #include "davinci_i2c.h"
  20. #ifdef CONFIG_DM_I2C
  21. /* Information about i2c controller */
  22. struct i2c_bus {
  23. int id;
  24. uint speed;
  25. struct i2c_regs *regs;
  26. };
  27. #endif
  28. #define CHECK_NACK() \
  29. do {\
  30. if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
  31. REG(&(i2c_base->i2c_con)) = 0;\
  32. return 1;\
  33. } \
  34. } while (0)
  35. static int _wait_for_bus(struct i2c_regs *i2c_base)
  36. {
  37. int stat, timeout;
  38. REG(&(i2c_base->i2c_stat)) = 0xffff;
  39. for (timeout = 0; timeout < 10; timeout++) {
  40. stat = REG(&(i2c_base->i2c_stat));
  41. if (!((stat) & I2C_STAT_BB)) {
  42. REG(&(i2c_base->i2c_stat)) = 0xffff;
  43. return 0;
  44. }
  45. REG(&(i2c_base->i2c_stat)) = stat;
  46. udelay(50000);
  47. }
  48. REG(&(i2c_base->i2c_stat)) = 0xffff;
  49. return 1;
  50. }
  51. static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask)
  52. {
  53. int stat, timeout;
  54. for (timeout = 0; timeout < 10; timeout++) {
  55. udelay(1000);
  56. stat = REG(&(i2c_base->i2c_stat));
  57. if (stat & mask)
  58. return stat;
  59. }
  60. REG(&(i2c_base->i2c_stat)) = 0xffff;
  61. return stat | I2C_TIMEOUT;
  62. }
  63. static void _flush_rx(struct i2c_regs *i2c_base)
  64. {
  65. while (1) {
  66. if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
  67. break;
  68. REG(&(i2c_base->i2c_drr));
  69. REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
  70. udelay(1000);
  71. }
  72. }
  73. static uint _davinci_i2c_setspeed(struct i2c_regs *i2c_base,
  74. uint speed)
  75. {
  76. uint32_t div, psc;
  77. psc = 2;
  78. /* SCLL + SCLH */
  79. div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
  80. REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
  81. REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
  82. REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
  83. return 0;
  84. }
  85. static void _davinci_i2c_init(struct i2c_regs *i2c_base,
  86. uint speed, int slaveadd)
  87. {
  88. if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
  89. REG(&(i2c_base->i2c_con)) = 0;
  90. udelay(50000);
  91. }
  92. _davinci_i2c_setspeed(i2c_base, speed);
  93. REG(&(i2c_base->i2c_oa)) = slaveadd;
  94. REG(&(i2c_base->i2c_cnt)) = 0;
  95. /* Interrupts must be enabled or I2C module won't work */
  96. REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
  97. I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
  98. /* Now enable I2C controller (get it out of reset) */
  99. REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
  100. udelay(1000);
  101. }
  102. static int _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip,
  103. uint32_t addr, int alen, uint8_t *buf, int len)
  104. {
  105. uint32_t tmp;
  106. int i;
  107. if ((alen < 0) || (alen > 2)) {
  108. printf("%s(): bogus address length %x\n", __func__, alen);
  109. return 1;
  110. }
  111. if (_wait_for_bus(i2c_base))
  112. return 1;
  113. if (alen != 0) {
  114. /* Start address phase */
  115. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
  116. REG(&(i2c_base->i2c_cnt)) = alen;
  117. REG(&(i2c_base->i2c_sa)) = chip;
  118. REG(&(i2c_base->i2c_con)) = tmp;
  119. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
  120. CHECK_NACK();
  121. switch (alen) {
  122. case 2:
  123. /* Send address MSByte */
  124. if (tmp & I2C_STAT_XRDY) {
  125. REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
  126. } else {
  127. REG(&(i2c_base->i2c_con)) = 0;
  128. return 1;
  129. }
  130. tmp = _poll_i2c_irq(i2c_base,
  131. I2C_STAT_XRDY | I2C_STAT_NACK);
  132. CHECK_NACK();
  133. /* No break, fall through */
  134. case 1:
  135. /* Send address LSByte */
  136. if (tmp & I2C_STAT_XRDY) {
  137. REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
  138. } else {
  139. REG(&(i2c_base->i2c_con)) = 0;
  140. return 1;
  141. }
  142. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY |
  143. I2C_STAT_NACK | I2C_STAT_ARDY);
  144. CHECK_NACK();
  145. if (!(tmp & I2C_STAT_ARDY)) {
  146. REG(&(i2c_base->i2c_con)) = 0;
  147. return 1;
  148. }
  149. }
  150. }
  151. /* Address phase is over, now read 'len' bytes and stop */
  152. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
  153. REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
  154. REG(&(i2c_base->i2c_sa)) = chip;
  155. REG(&(i2c_base->i2c_con)) = tmp;
  156. for (i = 0; i < len; i++) {
  157. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_RRDY | I2C_STAT_NACK |
  158. I2C_STAT_ROVR);
  159. CHECK_NACK();
  160. if (tmp & I2C_STAT_RRDY) {
  161. buf[i] = REG(&(i2c_base->i2c_drr));
  162. } else {
  163. REG(&(i2c_base->i2c_con)) = 0;
  164. return 1;
  165. }
  166. }
  167. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
  168. CHECK_NACK();
  169. if (!(tmp & I2C_STAT_SCD)) {
  170. REG(&(i2c_base->i2c_con)) = 0;
  171. return 1;
  172. }
  173. _flush_rx(i2c_base);
  174. REG(&(i2c_base->i2c_stat)) = 0xffff;
  175. REG(&(i2c_base->i2c_cnt)) = 0;
  176. REG(&(i2c_base->i2c_con)) = 0;
  177. return 0;
  178. }
  179. static int _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip,
  180. uint32_t addr, int alen, uint8_t *buf, int len)
  181. {
  182. uint32_t tmp;
  183. int i;
  184. if ((alen < 0) || (alen > 2)) {
  185. printf("%s(): bogus address length %x\n", __func__, alen);
  186. return 1;
  187. }
  188. if (len < 0) {
  189. printf("%s(): bogus length %x\n", __func__, len);
  190. return 1;
  191. }
  192. if (_wait_for_bus(i2c_base))
  193. return 1;
  194. /* Start address phase */
  195. tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
  196. I2C_CON_TRX | I2C_CON_STP;
  197. REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
  198. len & 0xffff : (len & 0xffff) + alen;
  199. REG(&(i2c_base->i2c_sa)) = chip;
  200. REG(&(i2c_base->i2c_con)) = tmp;
  201. switch (alen) {
  202. case 2:
  203. /* Send address MSByte */
  204. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
  205. CHECK_NACK();
  206. if (tmp & I2C_STAT_XRDY) {
  207. REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
  208. } else {
  209. REG(&(i2c_base->i2c_con)) = 0;
  210. return 1;
  211. }
  212. /* No break, fall through */
  213. case 1:
  214. /* Send address LSByte */
  215. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
  216. CHECK_NACK();
  217. if (tmp & I2C_STAT_XRDY) {
  218. REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
  219. } else {
  220. REG(&(i2c_base->i2c_con)) = 0;
  221. return 1;
  222. }
  223. }
  224. for (i = 0; i < len; i++) {
  225. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_XRDY | I2C_STAT_NACK);
  226. CHECK_NACK();
  227. if (tmp & I2C_STAT_XRDY)
  228. REG(&(i2c_base->i2c_dxr)) = buf[i];
  229. else
  230. return 1;
  231. }
  232. tmp = _poll_i2c_irq(i2c_base, I2C_STAT_SCD | I2C_STAT_NACK);
  233. CHECK_NACK();
  234. if (!(tmp & I2C_STAT_SCD)) {
  235. REG(&(i2c_base->i2c_con)) = 0;
  236. return 1;
  237. }
  238. _flush_rx(i2c_base);
  239. REG(&(i2c_base->i2c_stat)) = 0xffff;
  240. REG(&(i2c_base->i2c_cnt)) = 0;
  241. REG(&(i2c_base->i2c_con)) = 0;
  242. return 0;
  243. }
  244. static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
  245. {
  246. int rc = 1;
  247. if (chip == REG(&(i2c_base->i2c_oa)))
  248. return rc;
  249. REG(&(i2c_base->i2c_con)) = 0;
  250. if (_wait_for_bus(i2c_base))
  251. return 1;
  252. /* try to read one byte from current (or only) address */
  253. REG(&(i2c_base->i2c_cnt)) = 1;
  254. REG(&(i2c_base->i2c_sa)) = chip;
  255. REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
  256. I2C_CON_STP);
  257. udelay(50000);
  258. if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
  259. rc = 0;
  260. _flush_rx(i2c_base);
  261. REG(&(i2c_base->i2c_stat)) = 0xffff;
  262. } else {
  263. REG(&(i2c_base->i2c_stat)) = 0xffff;
  264. REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
  265. udelay(20000);
  266. if (_wait_for_bus(i2c_base))
  267. return 1;
  268. }
  269. _flush_rx(i2c_base);
  270. REG(&(i2c_base->i2c_stat)) = 0xffff;
  271. REG(&(i2c_base->i2c_cnt)) = 0;
  272. return rc;
  273. }
  274. #ifndef CONFIG_DM_I2C
  275. static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
  276. {
  277. switch (adap->hwadapnr) {
  278. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  279. case 2:
  280. return (struct i2c_regs *)I2C2_BASE;
  281. #endif
  282. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  283. case 1:
  284. return (struct i2c_regs *)I2C1_BASE;
  285. #endif
  286. case 0:
  287. return (struct i2c_regs *)I2C_BASE;
  288. default:
  289. printf("wrong hwadapnr: %d\n", adap->hwadapnr);
  290. }
  291. return NULL;
  292. }
  293. static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
  294. {
  295. struct i2c_regs *i2c_base = davinci_get_base(adap);
  296. uint ret;
  297. adap->speed = speed;
  298. ret = _davinci_i2c_setspeed(i2c_base, speed);
  299. return ret;
  300. }
  301. static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
  302. int slaveadd)
  303. {
  304. struct i2c_regs *i2c_base = davinci_get_base(adap);
  305. adap->speed = speed;
  306. _davinci_i2c_init(i2c_base, speed, slaveadd);
  307. return;
  308. }
  309. static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  310. uint32_t addr, int alen, uint8_t *buf, int len)
  311. {
  312. struct i2c_regs *i2c_base = davinci_get_base(adap);
  313. return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
  314. }
  315. static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  316. uint32_t addr, int alen, uint8_t *buf, int len)
  317. {
  318. struct i2c_regs *i2c_base = davinci_get_base(adap);
  319. return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
  320. }
  321. static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
  322. {
  323. struct i2c_regs *i2c_base = davinci_get_base(adap);
  324. return _davinci_i2c_probe_chip(i2c_base, chip);
  325. }
  326. U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
  327. davinci_i2c_read, davinci_i2c_write,
  328. davinci_i2c_setspeed,
  329. CONFIG_SYS_DAVINCI_I2C_SPEED,
  330. CONFIG_SYS_DAVINCI_I2C_SLAVE,
  331. 0)
  332. #if CONFIG_SYS_I2C_BUS_MAX >= 2
  333. U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
  334. davinci_i2c_read, davinci_i2c_write,
  335. davinci_i2c_setspeed,
  336. CONFIG_SYS_DAVINCI_I2C_SPEED1,
  337. CONFIG_SYS_DAVINCI_I2C_SLAVE1,
  338. 1)
  339. #endif
  340. #if CONFIG_SYS_I2C_BUS_MAX >= 3
  341. U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
  342. davinci_i2c_read, davinci_i2c_write,
  343. davinci_i2c_setspeed,
  344. CONFIG_SYS_DAVINCI_I2C_SPEED2,
  345. CONFIG_SYS_DAVINCI_I2C_SLAVE2,
  346. 2)
  347. #endif
  348. #else /* CONFIG_DM_I2C */
  349. static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  350. int nmsgs)
  351. {
  352. struct i2c_bus *i2c_bus = dev_get_priv(bus);
  353. int ret;
  354. debug("i2c_xfer: %d messages\n", nmsgs);
  355. for (; nmsgs > 0; nmsgs--, msg++) {
  356. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  357. if (msg->flags & I2C_M_RD) {
  358. ret = _davinci_i2c_read(i2c_bus->regs, msg->addr,
  359. 0, 0, msg->buf, msg->len);
  360. } else {
  361. ret = _davinci_i2c_write(i2c_bus->regs, msg->addr,
  362. 0, 0, msg->buf, msg->len);
  363. }
  364. if (ret) {
  365. debug("i2c_write: error sending\n");
  366. return -EREMOTEIO;
  367. }
  368. }
  369. return ret;
  370. }
  371. static int davinci_i2c_set_speed(struct udevice *dev, uint speed)
  372. {
  373. struct i2c_bus *i2c_bus = dev_get_priv(dev);
  374. i2c_bus->speed = speed;
  375. return _davinci_i2c_setspeed(i2c_bus->regs, speed);
  376. }
  377. static int davinci_i2c_probe(struct udevice *dev)
  378. {
  379. struct i2c_bus *i2c_bus = dev_get_priv(dev);
  380. i2c_bus->id = dev->seq;
  381. i2c_bus->regs = (struct i2c_regs *)devfdt_get_addr(dev);
  382. i2c_bus->speed = 100000;
  383. _davinci_i2c_init(i2c_bus->regs, i2c_bus->speed, 0);
  384. return 0;
  385. }
  386. static int davinci_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  387. uint chip_flags)
  388. {
  389. struct i2c_bus *i2c_bus = dev_get_priv(bus);
  390. return _davinci_i2c_probe_chip(i2c_bus->regs, chip_addr);
  391. }
  392. static const struct dm_i2c_ops davinci_i2c_ops = {
  393. .xfer = davinci_i2c_xfer,
  394. .probe_chip = davinci_i2c_probe_chip,
  395. .set_bus_speed = davinci_i2c_set_speed,
  396. };
  397. static const struct udevice_id davinci_i2c_ids[] = {
  398. { .compatible = "ti,davinci-i2c"},
  399. { .compatible = "ti,keystone-i2c"},
  400. { }
  401. };
  402. U_BOOT_DRIVER(i2c_davinci) = {
  403. .name = "i2c_davinci",
  404. .id = UCLASS_I2C,
  405. .of_match = davinci_i2c_ids,
  406. .probe = davinci_i2c_probe,
  407. .priv_auto_alloc_size = sizeof(struct i2c_bus),
  408. .ops = &davinci_i2c_ops,
  409. };
  410. #endif /* CONFIG_DM_I2C */