xilinx.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  4. *
  5. * (C) Copyright 2002
  6. * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
  7. * Keith Outwater, keith_outwater@mvis.com
  8. */
  9. /*
  10. * Xilinx FPGA support
  11. */
  12. #include <common.h>
  13. #include <fpga.h>
  14. #include <virtex2.h>
  15. #include <spartan2.h>
  16. #include <spartan3.h>
  17. #include <zynqpl.h>
  18. /* Local Static Functions */
  19. static int xilinx_validate(xilinx_desc *desc, char *fn);
  20. /* ------------------------------------------------------------------------- */
  21. int fpga_is_partial_data(int devnum, size_t img_len)
  22. {
  23. const fpga_desc * const desc = fpga_get_desc(devnum);
  24. xilinx_desc *desc_xilinx = desc->devdesc;
  25. /* Check datasize against FPGA size */
  26. if (img_len >= desc_xilinx->size)
  27. return 0;
  28. /* datasize is smaller, must be partial data */
  29. return 1;
  30. }
  31. int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
  32. bitstream_type bstype)
  33. {
  34. unsigned int length;
  35. unsigned int swapsize;
  36. unsigned char *dataptr;
  37. unsigned int i;
  38. const fpga_desc *desc;
  39. xilinx_desc *xdesc;
  40. dataptr = (unsigned char *)fpgadata;
  41. /* Find out fpga_description */
  42. desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
  43. /* Assign xilinx device description */
  44. xdesc = desc->devdesc;
  45. /* skip the first bytes of the bitsteam, their meaning is unknown */
  46. length = (*dataptr << 8) + *(dataptr + 1);
  47. dataptr += 2;
  48. dataptr += length;
  49. /* get design name (identifier, length, string) */
  50. length = (*dataptr << 8) + *(dataptr + 1);
  51. dataptr += 2;
  52. if (*dataptr++ != 0x61) {
  53. debug("%s: Design name id not recognized in bitstream\n",
  54. __func__);
  55. return FPGA_FAIL;
  56. }
  57. length = (*dataptr << 8) + *(dataptr + 1);
  58. dataptr += 2;
  59. printf(" design filename = \"%s\"\n", dataptr);
  60. dataptr += length;
  61. /* get part number (identifier, length, string) */
  62. if (*dataptr++ != 0x62) {
  63. printf("%s: Part number id not recognized in bitstream\n",
  64. __func__);
  65. return FPGA_FAIL;
  66. }
  67. length = (*dataptr << 8) + *(dataptr + 1);
  68. dataptr += 2;
  69. if (xdesc->name) {
  70. i = (ulong)strstr((char *)dataptr, xdesc->name);
  71. if (!i) {
  72. printf("%s: Wrong bitstream ID for this device\n",
  73. __func__);
  74. printf("%s: Bitstream ID %s, current device ID %d/%s\n",
  75. __func__, dataptr, devnum, xdesc->name);
  76. return FPGA_FAIL;
  77. }
  78. } else {
  79. printf("%s: Please fill correct device ID to xilinx_desc\n",
  80. __func__);
  81. }
  82. printf(" part number = \"%s\"\n", dataptr);
  83. dataptr += length;
  84. /* get date (identifier, length, string) */
  85. if (*dataptr++ != 0x63) {
  86. printf("%s: Date identifier not recognized in bitstream\n",
  87. __func__);
  88. return FPGA_FAIL;
  89. }
  90. length = (*dataptr << 8) + *(dataptr+1);
  91. dataptr += 2;
  92. printf(" date = \"%s\"\n", dataptr);
  93. dataptr += length;
  94. /* get time (identifier, length, string) */
  95. if (*dataptr++ != 0x64) {
  96. printf("%s: Time identifier not recognized in bitstream\n",
  97. __func__);
  98. return FPGA_FAIL;
  99. }
  100. length = (*dataptr << 8) + *(dataptr+1);
  101. dataptr += 2;
  102. printf(" time = \"%s\"\n", dataptr);
  103. dataptr += length;
  104. /* get fpga data length (identifier, length) */
  105. if (*dataptr++ != 0x65) {
  106. printf("%s: Data length id not recognized in bitstream\n",
  107. __func__);
  108. return FPGA_FAIL;
  109. }
  110. swapsize = ((unsigned int) *dataptr << 24) +
  111. ((unsigned int) *(dataptr + 1) << 16) +
  112. ((unsigned int) *(dataptr + 2) << 8) +
  113. ((unsigned int) *(dataptr + 3));
  114. dataptr += 4;
  115. printf(" bytes in bitstream = %d\n", swapsize);
  116. return fpga_load(devnum, dataptr, swapsize, bstype);
  117. }
  118. int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
  119. bitstream_type bstype)
  120. {
  121. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  122. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  123. return FPGA_FAIL;
  124. }
  125. if (!desc->operations || !desc->operations->load) {
  126. printf("%s: Missing load operation\n", __func__);
  127. return FPGA_FAIL;
  128. }
  129. return desc->operations->load(desc, buf, bsize, bstype);
  130. }
  131. #if defined(CONFIG_CMD_FPGA_LOADFS)
  132. int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
  133. fpga_fs_info *fpga_fsinfo)
  134. {
  135. if (!xilinx_validate(desc, (char *)__func__)) {
  136. printf("%s: Invalid device descriptor\n", __func__);
  137. return FPGA_FAIL;
  138. }
  139. if (!desc->operations || !desc->operations->loadfs) {
  140. printf("%s: Missing loadfs operation\n", __func__);
  141. return FPGA_FAIL;
  142. }
  143. return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
  144. }
  145. #endif
  146. #if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
  147. int xilinx_loads(xilinx_desc *desc, const void *buf, size_t bsize,
  148. struct fpga_secure_info *fpga_sec_info)
  149. {
  150. if (!xilinx_validate(desc, (char *)__func__)) {
  151. printf("%s: Invalid device descriptor\n", __func__);
  152. return FPGA_FAIL;
  153. }
  154. if (!desc->operations || !desc->operations->loads) {
  155. printf("%s: Missing loads operation\n", __func__);
  156. return FPGA_FAIL;
  157. }
  158. return desc->operations->loads(desc, buf, bsize, fpga_sec_info);
  159. }
  160. #endif
  161. int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
  162. {
  163. if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
  164. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  165. return FPGA_FAIL;
  166. }
  167. if (!desc->operations || !desc->operations->dump) {
  168. printf("%s: Missing dump operation\n", __func__);
  169. return FPGA_FAIL;
  170. }
  171. return desc->operations->dump(desc, buf, bsize);
  172. }
  173. int xilinx_info(xilinx_desc *desc)
  174. {
  175. int ret_val = FPGA_FAIL;
  176. if (xilinx_validate (desc, (char *)__FUNCTION__)) {
  177. printf ("Family: \t");
  178. switch (desc->family) {
  179. case xilinx_spartan2:
  180. printf ("Spartan-II\n");
  181. break;
  182. case xilinx_spartan3:
  183. printf ("Spartan-III\n");
  184. break;
  185. case xilinx_virtex2:
  186. printf ("Virtex-II\n");
  187. break;
  188. case xilinx_zynq:
  189. printf("Zynq PL\n");
  190. break;
  191. case xilinx_zynqmp:
  192. printf("ZynqMP PL\n");
  193. break;
  194. case xilinx_versal:
  195. printf("Versal PL\n");
  196. break;
  197. /* Add new family types here */
  198. default:
  199. printf ("Unknown family type, %d\n", desc->family);
  200. }
  201. printf ("Interface type:\t");
  202. switch (desc->iface) {
  203. case slave_serial:
  204. printf ("Slave Serial\n");
  205. break;
  206. case master_serial: /* Not used */
  207. printf ("Master Serial\n");
  208. break;
  209. case slave_parallel:
  210. printf ("Slave Parallel\n");
  211. break;
  212. case jtag_mode: /* Not used */
  213. printf ("JTAG Mode\n");
  214. break;
  215. case slave_selectmap:
  216. printf ("Slave SelectMap Mode\n");
  217. break;
  218. case master_selectmap:
  219. printf ("Master SelectMap Mode\n");
  220. break;
  221. case devcfg:
  222. printf("Device configuration interface (Zynq)\n");
  223. break;
  224. case csu_dma:
  225. printf("csu_dma configuration interface (ZynqMP)\n");
  226. break;
  227. case cfi:
  228. printf("CFI configuration interface (Versal)\n");
  229. break;
  230. /* Add new interface types here */
  231. default:
  232. printf ("Unsupported interface type, %d\n", desc->iface);
  233. }
  234. printf("Device Size: \t%zd bytes\n"
  235. "Cookie: \t0x%x (%d)\n",
  236. desc->size, desc->cookie, desc->cookie);
  237. if (desc->name)
  238. printf("Device name: \t%s\n", desc->name);
  239. if (desc->iface_fns)
  240. printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
  241. else
  242. printf ("No Device Function Table.\n");
  243. if (desc->operations && desc->operations->info)
  244. desc->operations->info(desc);
  245. ret_val = FPGA_SUCCESS;
  246. } else {
  247. printf ("%s: Invalid device descriptor\n", __FUNCTION__);
  248. }
  249. return ret_val;
  250. }
  251. /* ------------------------------------------------------------------------- */
  252. static int xilinx_validate(xilinx_desc *desc, char *fn)
  253. {
  254. int ret_val = false;
  255. if (desc) {
  256. if ((desc->family > min_xilinx_type) &&
  257. (desc->family < max_xilinx_type)) {
  258. if ((desc->iface > min_xilinx_iface_type) &&
  259. (desc->iface < max_xilinx_iface_type)) {
  260. if (desc->size) {
  261. ret_val = true;
  262. } else
  263. printf ("%s: NULL part size\n", fn);
  264. } else
  265. printf ("%s: Invalid Interface type, %d\n",
  266. fn, desc->iface);
  267. } else
  268. printf ("%s: Invalid family type, %d\n", fn, desc->family);
  269. } else
  270. printf ("%s: NULL descriptor!\n", fn);
  271. return ret_val;
  272. }