ahci.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. * Author: Jason Jin<Jason.jin@freescale.com>
  5. * Zhang Wei<wei.zhang@freescale.com>
  6. *
  7. * with the reference on libata and ahci drvier in kernel
  8. *
  9. * This driver provides a SCSI interface to SATA.
  10. */
  11. #include <common.h>
  12. #include <command.h>
  13. #include <dm.h>
  14. #include <pci.h>
  15. #include <asm/processor.h>
  16. #include <linux/errno.h>
  17. #include <asm/io.h>
  18. #include <malloc.h>
  19. #include <memalign.h>
  20. #include <pci.h>
  21. #include <scsi.h>
  22. #include <libata.h>
  23. #include <linux/ctype.h>
  24. #include <ahci.h>
  25. #include <dm/device-internal.h>
  26. #include <dm/lists.h>
  27. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
  28. #ifndef CONFIG_DM_SCSI
  29. struct ahci_uc_priv *probe_ent = NULL;
  30. #endif
  31. #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  32. /*
  33. * Some controllers limit number of blocks they can read/write at once.
  34. * Contemporary SSD devices work much faster if the read/write size is aligned
  35. * to a power of 2. Let's set default to 128 and allowing to be overwritten if
  36. * needed.
  37. */
  38. #ifndef MAX_SATA_BLOCKS_READ_WRITE
  39. #define MAX_SATA_BLOCKS_READ_WRITE 0x80
  40. #endif
  41. /* Maximum timeouts for each event */
  42. #define WAIT_MS_SPINUP 20000
  43. #define WAIT_MS_DATAIO 10000
  44. #define WAIT_MS_FLUSH 5000
  45. #define WAIT_MS_LINKUP 200
  46. __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
  47. {
  48. return base + 0x100 + (port * 0x80);
  49. }
  50. #define msleep(a) udelay(a * 1000)
  51. static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
  52. {
  53. const unsigned long start = begin;
  54. const unsigned long end = start + len;
  55. debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
  56. flush_dcache_range(start, end);
  57. }
  58. /*
  59. * SATA controller DMAs to physical RAM. Ensure data from the
  60. * controller is invalidated from dcache; next access comes from
  61. * physical RAM.
  62. */
  63. static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
  64. {
  65. const unsigned long start = begin;
  66. const unsigned long end = start + len;
  67. debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
  68. invalidate_dcache_range(start, end);
  69. }
  70. /*
  71. * Ensure data for SATA controller is flushed out of dcache and
  72. * written to physical memory.
  73. */
  74. static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
  75. {
  76. ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
  77. AHCI_PORT_PRIV_DMA_SZ);
  78. }
  79. static int waiting_for_cmd_completed(void __iomem *offset,
  80. int timeout_msec,
  81. u32 sign)
  82. {
  83. int i;
  84. u32 status;
  85. for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  86. msleep(1);
  87. return (i < timeout_msec) ? 0 : -1;
  88. }
  89. int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
  90. {
  91. u32 tmp;
  92. int j = 0;
  93. void __iomem *port_mmio = uc_priv->port[port].port_mmio;
  94. /*
  95. * Bring up SATA link.
  96. * SATA link bringup time is usually less than 1 ms; only very
  97. * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
  98. */
  99. while (j < WAIT_MS_LINKUP) {
  100. tmp = readl(port_mmio + PORT_SCR_STAT);
  101. tmp &= PORT_SCR_STAT_DET_MASK;
  102. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  103. return 0;
  104. udelay(1000);
  105. j++;
  106. }
  107. return 1;
  108. }
  109. #ifdef CONFIG_SUNXI_AHCI
  110. /* The sunxi AHCI controller requires this undocumented setup */
  111. static void sunxi_dma_init(void __iomem *port_mmio)
  112. {
  113. clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
  114. }
  115. #endif
  116. int ahci_reset(void __iomem *base)
  117. {
  118. int i = 1000;
  119. u32 __iomem *host_ctl_reg = base + HOST_CTL;
  120. u32 tmp = readl(host_ctl_reg); /* global controller reset */
  121. if ((tmp & HOST_RESET) == 0)
  122. writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
  123. /*
  124. * reset must complete within 1 second, or
  125. * the hardware should be considered fried.
  126. */
  127. do {
  128. udelay(1000);
  129. tmp = readl(host_ctl_reg);
  130. i--;
  131. } while ((i > 0) && (tmp & HOST_RESET));
  132. if (i == 0) {
  133. printf("controller reset failed (0x%x)\n", tmp);
  134. return -1;
  135. }
  136. return 0;
  137. }
  138. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  139. {
  140. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  141. # ifdef CONFIG_DM_PCI
  142. struct udevice *dev = uc_priv->dev;
  143. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  144. # else
  145. pci_dev_t pdev = uc_priv->dev;
  146. unsigned short vendor;
  147. # endif
  148. u16 tmp16;
  149. #endif
  150. void __iomem *mmio = uc_priv->mmio_base;
  151. u32 tmp, cap_save, cmd;
  152. int i, j, ret;
  153. void __iomem *port_mmio;
  154. u32 port_map;
  155. debug("ahci_host_init: start\n");
  156. cap_save = readl(mmio + HOST_CAP);
  157. cap_save &= ((1 << 28) | (1 << 17));
  158. cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
  159. ret = ahci_reset(uc_priv->mmio_base);
  160. if (ret)
  161. return ret;
  162. writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
  163. writel(cap_save, mmio + HOST_CAP);
  164. writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
  165. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  166. # ifdef CONFIG_DM_PCI
  167. if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
  168. u16 tmp16;
  169. dm_pci_read_config16(dev, 0x92, &tmp16);
  170. dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
  171. }
  172. # else
  173. pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  174. if (vendor == PCI_VENDOR_ID_INTEL) {
  175. u16 tmp16;
  176. pci_read_config_word(pdev, 0x92, &tmp16);
  177. tmp16 |= 0xf;
  178. pci_write_config_word(pdev, 0x92, tmp16);
  179. }
  180. # endif
  181. #endif
  182. uc_priv->cap = readl(mmio + HOST_CAP);
  183. uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
  184. port_map = uc_priv->port_map;
  185. uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
  186. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  187. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  188. #if !defined(CONFIG_DM_SCSI)
  189. if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
  190. uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
  191. #endif
  192. for (i = 0; i < uc_priv->n_ports; i++) {
  193. if (!(port_map & (1 << i)))
  194. continue;
  195. uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
  196. port_mmio = (u8 *)uc_priv->port[i].port_mmio;
  197. /* make sure port is not active */
  198. tmp = readl(port_mmio + PORT_CMD);
  199. if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  200. PORT_CMD_FIS_RX | PORT_CMD_START)) {
  201. debug("Port %d is active. Deactivating.\n", i);
  202. tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  203. PORT_CMD_FIS_RX | PORT_CMD_START);
  204. writel_with_flush(tmp, port_mmio + PORT_CMD);
  205. /* spec says 500 msecs for each bit, so
  206. * this is slightly incorrect.
  207. */
  208. msleep(500);
  209. }
  210. #ifdef CONFIG_SUNXI_AHCI
  211. sunxi_dma_init(port_mmio);
  212. #endif
  213. /* Add the spinup command to whatever mode bits may
  214. * already be on in the command register.
  215. */
  216. cmd = readl(port_mmio + PORT_CMD);
  217. cmd |= PORT_CMD_SPIN_UP;
  218. writel_with_flush(cmd, port_mmio + PORT_CMD);
  219. /* Bring up SATA link. */
  220. ret = ahci_link_up(uc_priv, i);
  221. if (ret) {
  222. printf("SATA link %d timeout.\n", i);
  223. continue;
  224. } else {
  225. debug("SATA link ok.\n");
  226. }
  227. /* Clear error status */
  228. tmp = readl(port_mmio + PORT_SCR_ERR);
  229. if (tmp)
  230. writel(tmp, port_mmio + PORT_SCR_ERR);
  231. debug("Spinning up device on SATA port %d... ", i);
  232. j = 0;
  233. while (j < WAIT_MS_SPINUP) {
  234. tmp = readl(port_mmio + PORT_TFDATA);
  235. if (!(tmp & (ATA_BUSY | ATA_DRQ)))
  236. break;
  237. udelay(1000);
  238. tmp = readl(port_mmio + PORT_SCR_STAT);
  239. tmp &= PORT_SCR_STAT_DET_MASK;
  240. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  241. break;
  242. j++;
  243. }
  244. tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
  245. if (tmp == PORT_SCR_STAT_DET_COMINIT) {
  246. debug("SATA link %d down (COMINIT received), retrying...\n", i);
  247. i--;
  248. continue;
  249. }
  250. printf("Target spinup took %d ms.\n", j);
  251. if (j == WAIT_MS_SPINUP)
  252. debug("timeout.\n");
  253. else
  254. debug("ok.\n");
  255. tmp = readl(port_mmio + PORT_SCR_ERR);
  256. debug("PORT_SCR_ERR 0x%x\n", tmp);
  257. writel(tmp, port_mmio + PORT_SCR_ERR);
  258. /* ack any pending irq events for this port */
  259. tmp = readl(port_mmio + PORT_IRQ_STAT);
  260. debug("PORT_IRQ_STAT 0x%x\n", tmp);
  261. if (tmp)
  262. writel(tmp, port_mmio + PORT_IRQ_STAT);
  263. writel(1 << i, mmio + HOST_IRQ_STAT);
  264. /* register linkup ports */
  265. tmp = readl(port_mmio + PORT_SCR_STAT);
  266. debug("SATA port %d status: 0x%x\n", i, tmp);
  267. if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
  268. uc_priv->link_port_map |= (0x01 << i);
  269. }
  270. tmp = readl(mmio + HOST_CTL);
  271. debug("HOST_CTL 0x%x\n", tmp);
  272. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  273. tmp = readl(mmio + HOST_CTL);
  274. debug("HOST_CTL 0x%x\n", tmp);
  275. #if !defined(CONFIG_DM_SCSI)
  276. #ifndef CONFIG_SCSI_AHCI_PLAT
  277. # ifdef CONFIG_DM_PCI
  278. dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
  279. tmp |= PCI_COMMAND_MASTER;
  280. dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
  281. # else
  282. pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
  283. tmp |= PCI_COMMAND_MASTER;
  284. pci_write_config_word(pdev, PCI_COMMAND, tmp16);
  285. # endif
  286. #endif
  287. #endif
  288. return 0;
  289. }
  290. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  291. {
  292. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  293. # if defined(CONFIG_DM_PCI)
  294. struct udevice *dev = uc_priv->dev;
  295. # else
  296. pci_dev_t pdev = uc_priv->dev;
  297. # endif
  298. u16 cc;
  299. #endif
  300. void __iomem *mmio = uc_priv->mmio_base;
  301. u32 vers, cap, cap2, impl, speed;
  302. const char *speed_s;
  303. const char *scc_s;
  304. vers = readl(mmio + HOST_VERSION);
  305. cap = uc_priv->cap;
  306. cap2 = readl(mmio + HOST_CAP2);
  307. impl = uc_priv->port_map;
  308. speed = (cap >> 20) & 0xf;
  309. if (speed == 1)
  310. speed_s = "1.5";
  311. else if (speed == 2)
  312. speed_s = "3";
  313. else if (speed == 3)
  314. speed_s = "6";
  315. else
  316. speed_s = "?";
  317. #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
  318. scc_s = "SATA";
  319. #else
  320. # ifdef CONFIG_DM_PCI
  321. dm_pci_read_config16(dev, 0x0a, &cc);
  322. # else
  323. pci_read_config_word(pdev, 0x0a, &cc);
  324. # endif
  325. if (cc == 0x0101)
  326. scc_s = "IDE";
  327. else if (cc == 0x0106)
  328. scc_s = "SATA";
  329. else if (cc == 0x0104)
  330. scc_s = "RAID";
  331. else
  332. scc_s = "unknown";
  333. #endif
  334. printf("AHCI %02x%02x.%02x%02x "
  335. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  336. (vers >> 24) & 0xff,
  337. (vers >> 16) & 0xff,
  338. (vers >> 8) & 0xff,
  339. vers & 0xff,
  340. ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
  341. printf("flags: "
  342. "%s%s%s%s%s%s%s"
  343. "%s%s%s%s%s%s%s"
  344. "%s%s%s%s%s%s\n",
  345. cap & (1 << 31) ? "64bit " : "",
  346. cap & (1 << 30) ? "ncq " : "",
  347. cap & (1 << 28) ? "ilck " : "",
  348. cap & (1 << 27) ? "stag " : "",
  349. cap & (1 << 26) ? "pm " : "",
  350. cap & (1 << 25) ? "led " : "",
  351. cap & (1 << 24) ? "clo " : "",
  352. cap & (1 << 19) ? "nz " : "",
  353. cap & (1 << 18) ? "only " : "",
  354. cap & (1 << 17) ? "pmp " : "",
  355. cap & (1 << 16) ? "fbss " : "",
  356. cap & (1 << 15) ? "pio " : "",
  357. cap & (1 << 14) ? "slum " : "",
  358. cap & (1 << 13) ? "part " : "",
  359. cap & (1 << 7) ? "ccc " : "",
  360. cap & (1 << 6) ? "ems " : "",
  361. cap & (1 << 5) ? "sxs " : "",
  362. cap2 & (1 << 2) ? "apst " : "",
  363. cap2 & (1 << 1) ? "nvmp " : "",
  364. cap2 & (1 << 0) ? "boh " : "");
  365. }
  366. #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
  367. # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  368. static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
  369. # else
  370. static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
  371. # endif
  372. {
  373. #if !defined(CONFIG_DM_SCSI)
  374. u16 vendor;
  375. #endif
  376. int rc;
  377. uc_priv->dev = dev;
  378. uc_priv->host_flags = ATA_FLAG_SATA
  379. | ATA_FLAG_NO_LEGACY
  380. | ATA_FLAG_MMIO
  381. | ATA_FLAG_PIO_DMA
  382. | ATA_FLAG_NO_ATAPI;
  383. uc_priv->pio_mask = 0x1f;
  384. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  385. #if !defined(CONFIG_DM_SCSI)
  386. #ifdef CONFIG_DM_PCI
  387. uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  388. PCI_REGION_MEM);
  389. /* Take from kernel:
  390. * JMicron-specific fixup:
  391. * make sure we're in AHCI mode
  392. */
  393. dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
  394. if (vendor == 0x197b)
  395. dm_pci_write_config8(dev, 0x41, 0xa1);
  396. #else
  397. uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  398. PCI_REGION_MEM);
  399. /* Take from kernel:
  400. * JMicron-specific fixup:
  401. * make sure we're in AHCI mode
  402. */
  403. pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
  404. if (vendor == 0x197b)
  405. pci_write_config_byte(dev, 0x41, 0xa1);
  406. #endif
  407. #else
  408. struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
  409. uc_priv->mmio_base = (void *)plat->base;
  410. #endif
  411. debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
  412. /* initialize adapter */
  413. rc = ahci_host_init(uc_priv);
  414. if (rc)
  415. goto err_out;
  416. ahci_print_info(uc_priv);
  417. return 0;
  418. err_out:
  419. return rc;
  420. }
  421. #endif
  422. #define MAX_DATA_BYTE_COUNT (4*1024*1024)
  423. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  424. unsigned char *buf, int buf_len)
  425. {
  426. struct ahci_ioports *pp = &(uc_priv->port[port]);
  427. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  428. u32 sg_count;
  429. int i;
  430. sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
  431. if (sg_count > AHCI_MAX_SG) {
  432. printf("Error:Too much sg!\n");
  433. return -1;
  434. }
  435. for (i = 0; i < sg_count; i++) {
  436. ahci_sg->addr =
  437. cpu_to_le32((unsigned long) buf + i * MAX_DATA_BYTE_COUNT);
  438. ahci_sg->addr_hi = 0;
  439. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  440. (buf_len < MAX_DATA_BYTE_COUNT
  441. ? (buf_len - 1)
  442. : (MAX_DATA_BYTE_COUNT - 1)));
  443. ahci_sg++;
  444. buf_len -= MAX_DATA_BYTE_COUNT;
  445. }
  446. return sg_count;
  447. }
  448. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
  449. {
  450. pp->cmd_slot->opts = cpu_to_le32(opts);
  451. pp->cmd_slot->status = 0;
  452. pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
  453. #ifdef CONFIG_PHYS_64BIT
  454. pp->cmd_slot->tbl_addr_hi =
  455. cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
  456. #endif
  457. }
  458. static int wait_spinup(void __iomem *port_mmio)
  459. {
  460. ulong start;
  461. u32 tf_data;
  462. start = get_timer(0);
  463. do {
  464. tf_data = readl(port_mmio + PORT_TFDATA);
  465. if (!(tf_data & ATA_BUSY))
  466. return 0;
  467. } while (get_timer(start) < WAIT_MS_SPINUP);
  468. return -ETIMEDOUT;
  469. }
  470. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  471. {
  472. struct ahci_ioports *pp = &(uc_priv->port[port]);
  473. void __iomem *port_mmio = pp->port_mmio;
  474. u32 port_status;
  475. void __iomem *mem;
  476. debug("Enter start port: %d\n", port);
  477. port_status = readl(port_mmio + PORT_SCR_STAT);
  478. debug("Port %d status: %x\n", port, port_status);
  479. if ((port_status & 0xf) != 0x03) {
  480. printf("No Link on this port!\n");
  481. return -1;
  482. }
  483. mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
  484. if (!mem) {
  485. free(pp);
  486. printf("%s: No mem for table!\n", __func__);
  487. return -ENOMEM;
  488. }
  489. memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  490. /*
  491. * First item in chunk of DMA memory: 32-slot command table,
  492. * 32 bytes each in size
  493. */
  494. pp->cmd_slot =
  495. (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
  496. debug("cmd_slot = %p\n", pp->cmd_slot);
  497. mem += (AHCI_CMD_SLOT_SZ + 224);
  498. /*
  499. * Second item: Received-FIS area
  500. */
  501. pp->rx_fis = virt_to_phys((void *)mem);
  502. mem += AHCI_RX_FIS_SZ;
  503. /*
  504. * Third item: data area for storing a single command
  505. * and its scatter-gather table
  506. */
  507. pp->cmd_tbl = virt_to_phys((void *)mem);
  508. debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
  509. mem += AHCI_CMD_TBL_HDR;
  510. pp->cmd_tbl_sg =
  511. (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
  512. writel_with_flush((unsigned long)pp->cmd_slot,
  513. port_mmio + PORT_LST_ADDR);
  514. writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
  515. #ifdef CONFIG_SUNXI_AHCI
  516. sunxi_dma_init(port_mmio);
  517. #endif
  518. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  519. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  520. PORT_CMD_START, port_mmio + PORT_CMD);
  521. debug("Exit start port %d\n", port);
  522. /*
  523. * Make sure interface is not busy based on error and status
  524. * information from task file data register before proceeding
  525. */
  526. return wait_spinup(port_mmio);
  527. }
  528. static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
  529. int fis_len, u8 *buf, int buf_len, u8 is_write)
  530. {
  531. struct ahci_ioports *pp = &(uc_priv->port[port]);
  532. void __iomem *port_mmio = pp->port_mmio;
  533. u32 opts;
  534. u32 port_status;
  535. int sg_count;
  536. debug("Enter %s: for port %d\n", __func__, port);
  537. if (port > uc_priv->n_ports) {
  538. printf("Invalid port number %d\n", port);
  539. return -1;
  540. }
  541. port_status = readl(port_mmio + PORT_SCR_STAT);
  542. if ((port_status & 0xf) != 0x03) {
  543. debug("No Link on port %d!\n", port);
  544. return -1;
  545. }
  546. memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
  547. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  548. opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
  549. ahci_fill_cmd_slot(pp, opts);
  550. ahci_dcache_flush_sata_cmd(pp);
  551. ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
  552. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  553. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  554. WAIT_MS_DATAIO, 0x1)) {
  555. printf("timeout exit!\n");
  556. return -1;
  557. }
  558. ahci_dcache_invalidate_range((unsigned long)buf,
  559. (unsigned long)buf_len);
  560. debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
  561. return 0;
  562. }
  563. static char *ata_id_strcpy(u16 *target, u16 *src, int len)
  564. {
  565. int i;
  566. for (i = 0; i < len / 2; i++)
  567. target[i] = swab16(src[i]);
  568. return (char *)target;
  569. }
  570. /*
  571. * SCSI INQUIRY command operation.
  572. */
  573. static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
  574. struct scsi_cmd *pccb)
  575. {
  576. static const u8 hdr[] = {
  577. 0,
  578. 0,
  579. 0x5, /* claim SPC-3 version compatibility */
  580. 2,
  581. 95 - 4,
  582. };
  583. u8 fis[20];
  584. u16 *idbuf;
  585. ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
  586. u8 port;
  587. /* Clean ccb data buffer */
  588. memset(pccb->pdata, 0, pccb->datalen);
  589. memcpy(pccb->pdata, hdr, sizeof(hdr));
  590. if (pccb->datalen <= 35)
  591. return 0;
  592. memset(fis, 0, sizeof(fis));
  593. /* Construct the FIS */
  594. fis[0] = 0x27; /* Host to device FIS. */
  595. fis[1] = 1 << 7; /* Command FIS. */
  596. fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
  597. /* Read id from sata */
  598. port = pccb->target;
  599. if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
  600. (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
  601. debug("scsi_ahci: SCSI inquiry command failure.\n");
  602. return -EIO;
  603. }
  604. if (!uc_priv->ataid[port]) {
  605. uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
  606. if (!uc_priv->ataid[port]) {
  607. printf("%s: No memory for ataid[port]\n", __func__);
  608. return -ENOMEM;
  609. }
  610. }
  611. idbuf = uc_priv->ataid[port];
  612. memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
  613. ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
  614. memcpy(&pccb->pdata[8], "ATA ", 8);
  615. ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
  616. ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
  617. #ifdef DEBUG
  618. ata_dump_id(idbuf);
  619. #endif
  620. return 0;
  621. }
  622. /*
  623. * SCSI READ10/WRITE10 command operation.
  624. */
  625. static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
  626. struct scsi_cmd *pccb, u8 is_write)
  627. {
  628. lbaint_t lba = 0;
  629. u16 blocks = 0;
  630. u8 fis[20];
  631. u8 *user_buffer = pccb->pdata;
  632. u32 user_buffer_size = pccb->datalen;
  633. /* Retrieve the base LBA number from the ccb structure. */
  634. if (pccb->cmd[0] == SCSI_READ16) {
  635. memcpy(&lba, pccb->cmd + 2, 8);
  636. lba = be64_to_cpu(lba);
  637. } else {
  638. u32 temp;
  639. memcpy(&temp, pccb->cmd + 2, 4);
  640. lba = be32_to_cpu(temp);
  641. }
  642. /*
  643. * Retrieve the base LBA number and the block count from
  644. * the ccb structure.
  645. *
  646. * For 10-byte and 16-byte SCSI R/W commands, transfer
  647. * length 0 means transfer 0 block of data.
  648. * However, for ATA R/W commands, sector count 0 means
  649. * 256 or 65536 sectors, not 0 sectors as in SCSI.
  650. *
  651. * WARNING: one or two older ATA drives treat 0 as 0...
  652. */
  653. if (pccb->cmd[0] == SCSI_READ16)
  654. blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
  655. else
  656. blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
  657. debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
  658. is_write ? "write" : "read", blocks, lba);
  659. /* Preset the FIS */
  660. memset(fis, 0, sizeof(fis));
  661. fis[0] = 0x27; /* Host to device FIS. */
  662. fis[1] = 1 << 7; /* Command FIS. */
  663. /* Command byte (read/write). */
  664. fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  665. while (blocks) {
  666. u16 now_blocks; /* number of blocks per iteration */
  667. u32 transfer_size; /* number of bytes per iteration */
  668. now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
  669. transfer_size = ATA_SECT_SIZE * now_blocks;
  670. if (transfer_size > user_buffer_size) {
  671. printf("scsi_ahci: Error: buffer too small.\n");
  672. return -EIO;
  673. }
  674. /*
  675. * LBA48 SATA command but only use 32bit address range within
  676. * that (unless we've enabled 64bit LBA support). The next
  677. * smaller command range (28bit) is too small.
  678. */
  679. fis[4] = (lba >> 0) & 0xff;
  680. fis[5] = (lba >> 8) & 0xff;
  681. fis[6] = (lba >> 16) & 0xff;
  682. fis[7] = 1 << 6; /* device reg: set LBA mode */
  683. fis[8] = ((lba >> 24) & 0xff);
  684. #ifdef CONFIG_SYS_64BIT_LBA
  685. if (pccb->cmd[0] == SCSI_READ16) {
  686. fis[9] = ((lba >> 32) & 0xff);
  687. fis[10] = ((lba >> 40) & 0xff);
  688. }
  689. #endif
  690. fis[3] = 0xe0; /* features */
  691. /* Block (sector) count */
  692. fis[12] = (now_blocks >> 0) & 0xff;
  693. fis[13] = (now_blocks >> 8) & 0xff;
  694. /* Read/Write from ahci */
  695. if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
  696. sizeof(fis), user_buffer, transfer_size,
  697. is_write)) {
  698. debug("scsi_ahci: SCSI %s10 command failure.\n",
  699. is_write ? "WRITE" : "READ");
  700. return -EIO;
  701. }
  702. /* If this transaction is a write, do a following flush.
  703. * Writes in u-boot are so rare, and the logic to know when is
  704. * the last write and do a flush only there is sufficiently
  705. * difficult. Just do a flush after every write. This incurs,
  706. * usually, one extra flush when the rare writes do happen.
  707. */
  708. if (is_write) {
  709. if (-EIO == ata_io_flush(uc_priv, pccb->target))
  710. return -EIO;
  711. }
  712. user_buffer += transfer_size;
  713. user_buffer_size -= transfer_size;
  714. blocks -= now_blocks;
  715. lba += now_blocks;
  716. }
  717. return 0;
  718. }
  719. /*
  720. * SCSI READ CAPACITY10 command operation.
  721. */
  722. static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
  723. struct scsi_cmd *pccb)
  724. {
  725. u32 cap;
  726. u64 cap64;
  727. u32 block_size;
  728. if (!uc_priv->ataid[pccb->target]) {
  729. printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
  730. "\tNo ATA info!\n"
  731. "\tPlease run SCSI command INQUIRY first!\n");
  732. return -EPERM;
  733. }
  734. cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  735. if (cap64 > 0x100000000ULL)
  736. cap64 = 0xffffffff;
  737. cap = cpu_to_be32(cap64);
  738. memcpy(pccb->pdata, &cap, sizeof(cap));
  739. block_size = cpu_to_be32((u32)512);
  740. memcpy(&pccb->pdata[4], &block_size, 4);
  741. return 0;
  742. }
  743. /*
  744. * SCSI READ CAPACITY16 command operation.
  745. */
  746. static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
  747. struct scsi_cmd *pccb)
  748. {
  749. u64 cap;
  750. u64 block_size;
  751. if (!uc_priv->ataid[pccb->target]) {
  752. printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
  753. "\tNo ATA info!\n"
  754. "\tPlease run SCSI command INQUIRY first!\n");
  755. return -EPERM;
  756. }
  757. cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  758. cap = cpu_to_be64(cap);
  759. memcpy(pccb->pdata, &cap, sizeof(cap));
  760. block_size = cpu_to_be64((u64)512);
  761. memcpy(&pccb->pdata[8], &block_size, 8);
  762. return 0;
  763. }
  764. /*
  765. * SCSI TEST UNIT READY command operation.
  766. */
  767. static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
  768. struct scsi_cmd *pccb)
  769. {
  770. return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
  771. }
  772. static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  773. {
  774. struct ahci_uc_priv *uc_priv;
  775. #ifdef CONFIG_DM_SCSI
  776. uc_priv = dev_get_uclass_priv(dev->parent);
  777. #else
  778. uc_priv = probe_ent;
  779. #endif
  780. int ret;
  781. switch (pccb->cmd[0]) {
  782. case SCSI_READ16:
  783. case SCSI_READ10:
  784. ret = ata_scsiop_read_write(uc_priv, pccb, 0);
  785. break;
  786. case SCSI_WRITE10:
  787. ret = ata_scsiop_read_write(uc_priv, pccb, 1);
  788. break;
  789. case SCSI_RD_CAPAC10:
  790. ret = ata_scsiop_read_capacity10(uc_priv, pccb);
  791. break;
  792. case SCSI_RD_CAPAC16:
  793. ret = ata_scsiop_read_capacity16(uc_priv, pccb);
  794. break;
  795. case SCSI_TST_U_RDY:
  796. ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
  797. break;
  798. case SCSI_INQUIRY:
  799. ret = ata_scsiop_inquiry(uc_priv, pccb);
  800. break;
  801. default:
  802. printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  803. return -ENOTSUPP;
  804. }
  805. if (ret) {
  806. debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  807. return ret;
  808. }
  809. return 0;
  810. }
  811. static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
  812. {
  813. u32 linkmap;
  814. int i;
  815. linkmap = uc_priv->link_port_map;
  816. for (i = 0; i < uc_priv->n_ports; i++) {
  817. if (((linkmap >> i) & 0x01)) {
  818. if (ahci_port_start(uc_priv, (u8) i)) {
  819. printf("Can not start port %d\n", i);
  820. continue;
  821. }
  822. }
  823. }
  824. return 0;
  825. }
  826. #ifndef CONFIG_DM_SCSI
  827. void scsi_low_level_init(int busdevfunc)
  828. {
  829. struct ahci_uc_priv *uc_priv;
  830. #ifndef CONFIG_SCSI_AHCI_PLAT
  831. probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
  832. if (!probe_ent) {
  833. printf("%s: No memory for uc_priv\n", __func__);
  834. return;
  835. }
  836. uc_priv = probe_ent;
  837. # if defined(CONFIG_DM_PCI)
  838. struct udevice *dev;
  839. int ret;
  840. ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
  841. if (ret)
  842. return;
  843. ahci_init_one(uc_priv, dev);
  844. # else
  845. ahci_init_one(uc_priv, busdevfunc);
  846. # endif
  847. #else
  848. uc_priv = probe_ent;
  849. #endif
  850. ahci_start_ports(uc_priv);
  851. }
  852. #endif
  853. #ifndef CONFIG_SCSI_AHCI_PLAT
  854. # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  855. int ahci_init_one_dm(struct udevice *dev)
  856. {
  857. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  858. return ahci_init_one(uc_priv, dev);
  859. }
  860. #endif
  861. #endif
  862. int ahci_start_ports_dm(struct udevice *dev)
  863. {
  864. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  865. return ahci_start_ports(uc_priv);
  866. }
  867. #ifdef CONFIG_SCSI_AHCI_PLAT
  868. static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
  869. {
  870. int rc;
  871. uc_priv->host_flags = ATA_FLAG_SATA
  872. | ATA_FLAG_NO_LEGACY
  873. | ATA_FLAG_MMIO
  874. | ATA_FLAG_PIO_DMA
  875. | ATA_FLAG_NO_ATAPI;
  876. uc_priv->pio_mask = 0x1f;
  877. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  878. uc_priv->mmio_base = base;
  879. /* initialize adapter */
  880. rc = ahci_host_init(uc_priv);
  881. if (rc)
  882. goto err_out;
  883. ahci_print_info(uc_priv);
  884. rc = ahci_start_ports(uc_priv);
  885. err_out:
  886. return rc;
  887. }
  888. #ifndef CONFIG_DM_SCSI
  889. int ahci_init(void __iomem *base)
  890. {
  891. struct ahci_uc_priv *uc_priv;
  892. probe_ent = malloc(sizeof(struct ahci_uc_priv));
  893. if (!probe_ent) {
  894. printf("%s: No memory for uc_priv\n", __func__);
  895. return -ENOMEM;
  896. }
  897. uc_priv = probe_ent;
  898. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  899. return ahci_init_common(uc_priv, base);
  900. }
  901. #endif
  902. int ahci_init_dm(struct udevice *dev, void __iomem *base)
  903. {
  904. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  905. return ahci_init_common(uc_priv, base);
  906. }
  907. void __weak scsi_init(void)
  908. {
  909. }
  910. #endif /* CONFIG_SCSI_AHCI_PLAT */
  911. /*
  912. * In the general case of generic rotating media it makes sense to have a
  913. * flush capability. It probably even makes sense in the case of SSDs because
  914. * one cannot always know for sure what kind of internal cache/flush mechanism
  915. * is embodied therein. At first it was planned to invoke this after the last
  916. * write to disk and before rebooting. In practice, knowing, a priori, which
  917. * is the last write is difficult. Because writing to the disk in u-boot is
  918. * very rare, this flush command will be invoked after every block write.
  919. */
  920. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
  921. {
  922. u8 fis[20];
  923. struct ahci_ioports *pp = &(uc_priv->port[port]);
  924. void __iomem *port_mmio = pp->port_mmio;
  925. u32 cmd_fis_len = 5; /* five dwords */
  926. /* Preset the FIS */
  927. memset(fis, 0, 20);
  928. fis[0] = 0x27; /* Host to device FIS. */
  929. fis[1] = 1 << 7; /* Command FIS. */
  930. fis[2] = ATA_CMD_FLUSH_EXT;
  931. memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
  932. ahci_fill_cmd_slot(pp, cmd_fis_len);
  933. ahci_dcache_flush_sata_cmd(pp);
  934. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  935. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  936. WAIT_MS_FLUSH, 0x1)) {
  937. debug("scsi_ahci: flush command timeout on port %d.\n", port);
  938. return -EIO;
  939. }
  940. return 0;
  941. }
  942. static int ahci_scsi_bus_reset(struct udevice *dev)
  943. {
  944. /* Not implemented */
  945. return 0;
  946. }
  947. #ifdef CONFIG_DM_SCSI
  948. int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
  949. {
  950. struct udevice *dev;
  951. int ret;
  952. ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
  953. if (ret)
  954. return ret;
  955. *devp = dev;
  956. return 0;
  957. }
  958. int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
  959. {
  960. struct ahci_uc_priv *uc_priv;
  961. struct scsi_platdata *uc_plat;
  962. struct udevice *dev;
  963. int ret;
  964. device_find_first_child(ahci_dev, &dev);
  965. if (!dev)
  966. return -ENODEV;
  967. uc_plat = dev_get_uclass_platdata(dev);
  968. uc_plat->base = base;
  969. uc_plat->max_lun = 1;
  970. uc_plat->max_id = 2;
  971. uc_priv = dev_get_uclass_priv(ahci_dev);
  972. ret = ahci_init_one(uc_priv, dev);
  973. if (ret)
  974. return ret;
  975. ret = ahci_start_ports(uc_priv);
  976. if (ret)
  977. return ret;
  978. return 0;
  979. }
  980. #ifdef CONFIG_DM_PCI
  981. int ahci_probe_scsi_pci(struct udevice *ahci_dev)
  982. {
  983. ulong base;
  984. base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
  985. PCI_REGION_MEM);
  986. return ahci_probe_scsi(ahci_dev, base);
  987. }
  988. #endif
  989. struct scsi_ops scsi_ops = {
  990. .exec = ahci_scsi_exec,
  991. .bus_reset = ahci_scsi_bus_reset,
  992. };
  993. U_BOOT_DRIVER(ahci_scsi) = {
  994. .name = "ahci_scsi",
  995. .id = UCLASS_SCSI,
  996. .ops = &scsi_ops,
  997. };
  998. #else
  999. int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  1000. {
  1001. return ahci_scsi_exec(dev, pccb);
  1002. }
  1003. __weak int scsi_bus_reset(struct udevice *dev)
  1004. {
  1005. return ahci_scsi_bus_reset(dev);
  1006. return 0;
  1007. }
  1008. #endif