CPCI405.h 13 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405GP 1 /* This is a PPC405 CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
  35. #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
  36. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  37. #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
  38. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  39. #define CONFIG_BAUDRATE 9600
  40. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  41. #undef CONFIG_BOOTARGS
  42. #undef CONFIG_BOOTCOMMAND
  43. #define CONFIG_PREBOOT /* enable preboot variable */
  44. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  45. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  46. #define CONFIG_PPC4xx_EMAC
  47. #define CONFIG_MII 1 /* MII PHY management */
  48. #define CONFIG_PHY_ADDR 0 /* PHY address */
  49. #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
  50. #define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
  51. #define CONFIG_NET_MULTI 1
  52. #undef CONFIG_HAS_ETH1
  53. /*
  54. * BOOTP options
  55. */
  56. #define CONFIG_BOOTP_SUBNETMASK
  57. #define CONFIG_BOOTP_GATEWAY
  58. #define CONFIG_BOOTP_HOSTNAME
  59. #define CONFIG_BOOTP_BOOTPATH
  60. #define CONFIG_BOOTP_DNS
  61. #define CONFIG_BOOTP_DNS2
  62. #define CONFIG_BOOTP_SEND_HOSTNAME
  63. /*
  64. * Command line configuration.
  65. */
  66. #include <config_cmd_default.h>
  67. #define CONFIG_CMD_DHCP
  68. #define CONFIG_CMD_PCI
  69. #define CONFIG_CMD_IRQ
  70. #define CONFIG_CMD_IDE
  71. #define CONFIG_CMD_FAT
  72. #define CONFIG_CMD_ELF
  73. #define CONFIG_CMD_MII
  74. #define CONFIG_CMD_EEPROM
  75. #define CONFIG_MAC_PARTITION
  76. #define CONFIG_DOS_PARTITION
  77. #define CONFIG_SUPPORT_VFAT
  78. #undef CONFIG_WATCHDOG /* watchdog disabled */
  79. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  80. /*
  81. * Miscellaneous configurable options
  82. */
  83. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  84. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  85. #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  86. #ifdef CONFIG_SYS_HUSH_PARSER
  87. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  88. #endif
  89. #if defined(CONFIG_CMD_KGDB)
  90. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  91. #else
  92. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  93. #endif
  94. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  95. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  96. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  97. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  98. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  99. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  100. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  101. #define CONFIG_CONS_INDEX 1 /* Use UART0 */
  102. #define CONFIG_SYS_NS16550
  103. #define CONFIG_SYS_NS16550_SERIAL
  104. #define CONFIG_SYS_NS16550_REG_SIZE 1
  105. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  106. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
  107. #define CONFIG_SYS_BASE_BAUD 691200
  108. /* The following table includes the supported baudrates */
  109. #define CONFIG_SYS_BAUDRATE_TABLE \
  110. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  111. 57600, 115200, 230400, 460800, 921600 }
  112. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  113. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  114. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  115. #define CONFIG_LOOPW 1 /* enable loopw command */
  116. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  117. /*-----------------------------------------------------------------------
  118. * PCI stuff
  119. *-----------------------------------------------------------------------
  120. */
  121. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  122. #define PCI_HOST_FORCE 1 /* configure as pci host */
  123. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  124. #define CONFIG_PCI /* include pci support */
  125. #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
  126. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  127. /* resource configuration */
  128. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  129. #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
  130. #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
  131. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
  132. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
  133. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
  134. #define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
  135. #define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
  136. #define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
  137. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  138. #define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
  139. #define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
  140. #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  141. #define CONFIG_PCI_4xx_PTM_OVERWRITE 1 /* overwrite PTMx settings by env */
  142. /*-----------------------------------------------------------------------
  143. * IDE/ATA stuff
  144. *-----------------------------------------------------------------------
  145. */
  146. #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
  147. #undef CONFIG_IDE_LED /* no led for ide supported */
  148. #undef CONFIG_IDE_RESET /* no reset for ide supported */
  149. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
  150. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
  151. #define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
  152. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  153. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
  154. #define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
  155. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
  156. /*-----------------------------------------------------------------------
  157. * Start addresses for the final memory configuration
  158. * (Set up by the startup code)
  159. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  160. */
  161. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  162. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE
  163. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  164. #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
  165. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  166. /*
  167. * For booting Linux, the board info and command line data
  168. * have to be in the first 8 MB of memory, since this is
  169. * the maximum mapped by the Linux kernel during initialization.
  170. */
  171. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  172. /*-----------------------------------------------------------------------
  173. * FLASH organization
  174. */
  175. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  176. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  177. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  178. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  179. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  180. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  181. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  182. /*
  183. * The following defines are added for buggy IOP480 byte interface.
  184. * All other boards should use the standard values (CPCI405 etc.)
  185. */
  186. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  187. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  188. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  189. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  190. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
  191. #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
  192. #define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
  193. #if 1 /* Use NVRAM for environment variables */
  194. /*-----------------------------------------------------------------------
  195. * NVRAM organization
  196. */
  197. #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
  198. #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
  199. #define CONFIG_ENV_ADDR \
  200. (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
  201. #else /* Use EEPROM for environment variables */
  202. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  203. #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
  204. #define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
  205. /* total size of a CAT24WC08 is 1024 bytes */
  206. #endif
  207. /*-----------------------------------------------------------------------
  208. * I2C EEPROM (CAT24WC08) for environment
  209. */
  210. #define CONFIG_HARD_I2C /* I2c with hardware support */
  211. #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
  212. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  213. #define CONFIG_SYS_I2C_SLAVE 0x7F
  214. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  215. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  216. /* mask of address bits that overflow into the "EEPROM chip address" */
  217. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  218. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  219. /* 16 byte page write mode using*/
  220. /* last 4 bits of the address */
  221. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  222. /*
  223. * Init Memory Controller:
  224. *
  225. * BR0/1 and OR0/1 (FLASH)
  226. */
  227. #define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
  228. #define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
  229. /*-----------------------------------------------------------------------
  230. * External Bus Controller (EBC) Setup
  231. */
  232. /* Memory Bank 0 (Flash Bank 0) initialization */
  233. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  234. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  235. /* Memory Bank 1 (Flash Bank 1) initialization */
  236. #define CONFIG_SYS_EBC_PB1AP 0x92015480
  237. #define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
  238. /* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */
  239. #define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  240. #define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  241. /* Memory Bank 3 (CompactFlash IDE) initialization */
  242. #define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
  243. #define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
  244. /* Memory Bank 4 (NVRAM) initialization */
  245. #define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */
  246. #define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
  247. /* Memory Bank 5 (Quart) initialization */
  248. #define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
  249. #define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */
  250. /*-----------------------------------------------------------------------
  251. * FPGA stuff
  252. */
  253. /* FPGA program pin configuration */
  254. #define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
  255. #define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
  256. #define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
  257. #define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
  258. #define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
  259. /*-----------------------------------------------------------------------
  260. * Definitions for initial stack pointer and data area (in data cache)
  261. */
  262. #if 1 /* test-only */
  263. #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
  264. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
  265. #else
  266. #define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
  267. #endif
  268. #define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
  269. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  270. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  271. #endif /* __CONFIG_H */