CPC45.h 17 KB

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  1. /*
  2. * (C) Copyright 2001-2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. *
  25. * Configuration settings for the CPC45 board.
  26. *
  27. */
  28. /* ------------------------------------------------------------------------- */
  29. /*
  30. * board/config.h - configuration options, board specific
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /*
  35. * High Level Configuration Options
  36. * (easy to change)
  37. */
  38. #define CONFIG_MPC824X 1
  39. #define CONFIG_MPC8245 1
  40. #define CONFIG_CPC45 1
  41. #define CONFIG_SYS_TEXT_BASE 0xFFF00000
  42. #define CONFIG_CONS_INDEX 1
  43. #define CONFIG_BAUDRATE 9600
  44. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  45. #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  46. #define CONFIG_BOOTDELAY 5
  47. /*
  48. * BOOTP options
  49. */
  50. #define CONFIG_BOOTP_SUBNETMASK
  51. #define CONFIG_BOOTP_GATEWAY
  52. #define CONFIG_BOOTP_HOSTNAME
  53. #define CONFIG_BOOTP_BOOTPATH
  54. #define CONFIG_BOOTP_BOOTFILESIZE
  55. /*
  56. * Command line configuration.
  57. */
  58. #include <config_cmd_default.h>
  59. #define CONFIG_CMD_BEDBUG
  60. #define CONFIG_CMD_DATE
  61. #define CONFIG_CMD_DHCP
  62. #define CONFIG_CMD_EEPROM
  63. #define CONFIG_CMD_EXT2
  64. #define CONFIG_CMD_FAT
  65. #define CONFIG_CMD_FLASH
  66. #define CONFIG_CMD_I2C
  67. #define CONFIG_CMD_IDE
  68. #define CONFIG_CMD_NFS
  69. #define CONFIG_CMD_PCI
  70. #define CONFIG_CMD_PING
  71. #define CONFIG_CMD_SDRAM
  72. #define CONFIG_CMD_SNTP
  73. /*
  74. * Miscellaneous configurable options
  75. */
  76. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  77. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  78. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  79. #if 1
  80. #define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
  81. #endif
  82. #ifdef CONFIG_SYS_HUSH_PARSER
  83. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  84. #endif
  85. /* Print Buffer Size
  86. */
  87. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  88. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  89. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  90. #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
  91. /*-----------------------------------------------------------------------
  92. * Start addresses for the final memory configuration
  93. * (Set up by the startup code)
  94. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  95. */
  96. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  97. #if defined(CONFIG_BOOT_ROM)
  98. #define CONFIG_SYS_FLASH_BASE 0xFF000000
  99. #else
  100. #define CONFIG_SYS_FLASH_BASE 0xFF800000
  101. #endif
  102. #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
  103. #define CONFIG_SYS_EUMB_ADDR 0xFCE00000
  104. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  105. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  106. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  107. #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
  108. #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
  109. /* Maximum amount of RAM.
  110. */
  111. #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
  112. #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
  113. #undef CONFIG_SYS_RAMBOOT
  114. #else
  115. #define CONFIG_SYS_RAMBOOT
  116. #endif
  117. /*-----------------------------------------------------------------------
  118. * Definitions for initial stack pointer and data area
  119. */
  120. /* Size in bytes reserved for initial data
  121. */
  122. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  123. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  124. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  125. /*
  126. * NS16550 Configuration
  127. */
  128. #define CONFIG_SYS_NS16550
  129. #define CONFIG_SYS_NS16550_SERIAL
  130. #define CONFIG_SYS_NS16550_REG_SIZE 1
  131. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  132. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
  133. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
  134. #define DUART_DCR (CONFIG_SYS_EUMB_ADDR + 0x4511)
  135. /*
  136. * I2C configuration
  137. */
  138. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  139. #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
  140. #define CONFIG_SYS_I2C_SLAVE 0x7F
  141. /*
  142. * RTC configuration
  143. */
  144. #define CONFIG_RTC_PCF8563
  145. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  146. /*
  147. * EEPROM configuration
  148. */
  149. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
  150. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  151. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  152. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  153. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  154. /*
  155. * Low Level Configuration Settings
  156. * (address mappings, register initial values, etc.)
  157. * You should know what you are doing if you make changes here.
  158. * For the detail description refer to the MPC8240 user's manual.
  159. */
  160. #define CONFIG_SYS_CLK_FREQ 33000000
  161. #define CONFIG_SYS_HZ 1000
  162. /* Bit-field values for MCCR1.
  163. */
  164. #define CONFIG_SYS_ROMNAL 0
  165. #define CONFIG_SYS_ROMFAL 8
  166. #define CONFIG_SYS_BANK0_ROW 0 /* SDRAM bank 7-0 row address */
  167. #define CONFIG_SYS_BANK1_ROW 0
  168. #define CONFIG_SYS_BANK2_ROW 0
  169. #define CONFIG_SYS_BANK3_ROW 0
  170. #define CONFIG_SYS_BANK4_ROW 0
  171. #define CONFIG_SYS_BANK5_ROW 0
  172. #define CONFIG_SYS_BANK6_ROW 0
  173. #define CONFIG_SYS_BANK7_ROW 0
  174. /* Bit-field values for MCCR2.
  175. */
  176. #define CONFIG_SYS_REFINT 0x2ec
  177. /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
  178. */
  179. #define CONFIG_SYS_BSTOPRE 160
  180. /* Bit-field values for MCCR3.
  181. */
  182. #define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
  183. #define CONFIG_SYS_RDLAT 0 /* Data latancy from read command */
  184. /* Bit-field values for MCCR4.
  185. */
  186. #define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval */
  187. #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
  188. #define CONFIG_SYS_SDMODE_CAS_LAT 2 /* SDMODE CAS latancy */
  189. #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
  190. #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
  191. #define CONFIG_SYS_ACTORW 2
  192. #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
  193. #define CONFIG_SYS_EXTROM 0
  194. #define CONFIG_SYS_REGDIMM 0
  195. /* Memory bank settings.
  196. * Only bits 20-29 are actually used from these vales to set the
  197. * start/end addresses. The upper two bits will always be 0, and the lower
  198. * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
  199. * address. Refer to the MPC8240 book.
  200. */
  201. #define CONFIG_SYS_BANK0_START 0x00000000
  202. #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
  203. #define CONFIG_SYS_BANK0_ENABLE 1
  204. #define CONFIG_SYS_BANK1_START 0x3ff00000
  205. #define CONFIG_SYS_BANK1_END 0x3fffffff
  206. #define CONFIG_SYS_BANK1_ENABLE 0
  207. #define CONFIG_SYS_BANK2_START 0x3ff00000
  208. #define CONFIG_SYS_BANK2_END 0x3fffffff
  209. #define CONFIG_SYS_BANK2_ENABLE 0
  210. #define CONFIG_SYS_BANK3_START 0x3ff00000
  211. #define CONFIG_SYS_BANK3_END 0x3fffffff
  212. #define CONFIG_SYS_BANK3_ENABLE 0
  213. #define CONFIG_SYS_BANK4_START 0x3ff00000
  214. #define CONFIG_SYS_BANK4_END 0x3fffffff
  215. #define CONFIG_SYS_BANK4_ENABLE 0
  216. #define CONFIG_SYS_BANK5_START 0x3ff00000
  217. #define CONFIG_SYS_BANK5_END 0x3fffffff
  218. #define CONFIG_SYS_BANK5_ENABLE 0
  219. #define CONFIG_SYS_BANK6_START 0x3ff00000
  220. #define CONFIG_SYS_BANK6_END 0x3fffffff
  221. #define CONFIG_SYS_BANK6_ENABLE 0
  222. #define CONFIG_SYS_BANK7_START 0x3ff00000
  223. #define CONFIG_SYS_BANK7_END 0x3fffffff
  224. #define CONFIG_SYS_BANK7_ENABLE 0
  225. #define CONFIG_SYS_ODCR 0xff
  226. #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
  227. /* currently accessed page in memory */
  228. /* see 8240 book for details */
  229. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  230. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  231. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
  232. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  233. #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  234. #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  235. #define CONFIG_SYS_IBAT3L (0xFC000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  236. #define CONFIG_SYS_IBAT3U (0xFC000000 | BATU_BL_64M | BATU_VS | BATU_VP)
  237. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  238. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  239. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  240. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  241. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  242. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  243. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  244. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  245. /*
  246. * For booting Linux, the board info and command line data
  247. * have to be in the first 8 MB of memory, since this is
  248. * the maximum mapped by the Linux kernel during initialization.
  249. */
  250. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  251. /*-----------------------------------------------------------------------
  252. * FLASH organization
  253. */
  254. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
  255. #define CONFIG_SYS_MAX_FLASH_SECT 39 /* Max number of sectors in one bank */
  256. #define INTEL_ID_28F160F3T 0x88F388F3 /* 16M = 1M x 16 top boot sector */
  257. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  258. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  259. /* Warining: environment is not EMBEDDED in the ppcboot code.
  260. * It's stored in flash separately.
  261. */
  262. #define CONFIG_ENV_IS_IN_FLASH 1
  263. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x7F8000)
  264. #define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment */
  265. #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
  266. #define CONFIG_ENV_SECT_SIZE 0x8000 /* Size of the Environment Sector */
  267. /*-----------------------------------------------------------------------
  268. * Cache Configuration
  269. */
  270. #define CONFIG_SYS_CACHELINE_SIZE 32
  271. #if defined(CONFIG_CMD_KGDB)
  272. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  273. #endif
  274. /*----------------------------------------------------------------------*/
  275. /* CPC45 Memory Map */
  276. /*----------------------------------------------------------------------*/
  277. #define SRAM_BASE 0x80000000 /* SRAM base address */
  278. #define SRAM_END 0x801FFFFF
  279. #define ST16552_A_BASE 0x80200000 /* ST16552 channel A */
  280. #define ST16552_B_BASE 0x80400000 /* ST16552 channel A */
  281. #define BCSR_BASE 0x80600000 /* board control / status registers */
  282. #define DISPLAY_BASE 0x80600040 /* DISPLAY base */
  283. #define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */
  284. #define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */
  285. #define CONFIG_SYS_SRAM_BASE SRAM_BASE
  286. #define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1)
  287. /*---------------------------------------------------------------------*/
  288. /* CPC45 Control/Status Registers */
  289. /*---------------------------------------------------------------------*/
  290. #define IRQ_ENA_1 *((volatile uchar*)(BCSR_BASE + 0x00))
  291. #define IRQ_STAT_1 *((volatile uchar*)(BCSR_BASE + 0x01))
  292. #define IRQ_ENA_2 *((volatile uchar*)(BCSR_BASE + 0x02))
  293. #define IRQ_STAT_2 *((volatile uchar*)(BCSR_BASE + 0x03))
  294. #define BOARD_CTRL *((volatile uchar*)(BCSR_BASE + 0x04))
  295. #define BOARD_STAT *((volatile uchar*)(BCSR_BASE + 0x05))
  296. #define WDG_START *((volatile uchar*)(BCSR_BASE + 0x06))
  297. #define WDG_PRESTOP *((volatile uchar*)(BCSR_BASE + 0x06))
  298. #define WDG_STOP *((volatile uchar*)(BCSR_BASE + 0x06))
  299. #define BOARD_REV *((volatile uchar*)(BCSR_BASE + 0x07))
  300. /* IRQ_ENA_1 bit definitions */
  301. #define I_ENA_1_IERA 0x80 /* INTA enable */
  302. #define I_ENA_1_IERB 0x40 /* INTB enable */
  303. #define I_ENA_1_IERC 0x20 /* INTC enable */
  304. #define I_ENA_1_IERD 0x10 /* INTD enable */
  305. /* IRQ_STAT_1 bit definitions */
  306. #define I_STAT_1_INTA 0x80 /* INTA status */
  307. #define I_STAT_1_INTB 0x40 /* INTB status */
  308. #define I_STAT_1_INTC 0x20 /* INTC status */
  309. #define I_STAT_1_INTD 0x10 /* INTD status */
  310. /* IRQ_ENA_2 bit definitions */
  311. #define I_ENA_2_IEAB 0x80 /* ABORT IRQ enable */
  312. #define I_ENA_2_IEK1 0x40 /* KEY1 IRQ enable */
  313. #define I_ENA_2_IEK2 0x20 /* KEY2 IRQ enable */
  314. #define I_ENA_2_IERT 0x10 /* RTC IRQ enable */
  315. #define I_ENA_2_IESM 0x08 /* LM81 IRQ enable */
  316. #define I_ENA_2_IEDG 0x04 /* DEGENERATING IRQ enable */
  317. #define I_ENA_2_IES2 0x02 /* ST16552/B IRQ enable */
  318. #define I_ENA_2_IES1 0x01 /* ST16552/A IRQ enable */
  319. /* IRQ_STAT_2 bit definitions */
  320. #define I_STAT_2_ABO 0x80 /* ABORT IRQ status */
  321. #define I_STAT_2_KY1 0x40 /* KEY1 IRQ status */
  322. #define I_STAT_2_KY2 0x20 /* KEY2 IRQ status */
  323. #define I_STAT_2_RTC 0x10 /* RTC IRQ status */
  324. #define I_STAT_2_SMN 0x08 /* LM81 IRQ status */
  325. #define I_STAT_2_DEG 0x04 /* DEGENERATING IRQ status */
  326. #define I_STAT_2_SIO2 0x02 /* ST16552/B IRQ status */
  327. #define I_STAT_2_SIO1 0x01 /* ST16552/A IRQ status */
  328. /* BOARD_CTRL bit definitions */
  329. #define USER_LEDS 2 /* 2 user LEDs */
  330. #if (USER_LEDS == 4)
  331. #define B_CTRL_WRSE 0x80
  332. #define B_CTRL_KRSE 0x40
  333. #define B_CTRL_FWRE 0x20 /* Flash write enable */
  334. #define B_CTRL_FWPT 0x10 /* Flash write protect */
  335. #define B_CTRL_LED3 0x08 /* LED 3 control */
  336. #define B_CTRL_LED2 0x04 /* LED 2 control */
  337. #define B_CTRL_LED1 0x02 /* LED 1 control */
  338. #define B_CTRL_LED0 0x01 /* LED 0 control */
  339. #else
  340. #define B_CTRL_WRSE 0x80
  341. #define B_CTRL_KRSE 0x40
  342. #define B_CTRL_FWRE_1 0x20 /* Flash write enable */
  343. #define B_CTRL_FWPT_1 0x10 /* Flash write protect */
  344. #define B_CTRL_LED1 0x08 /* LED 1 control */
  345. #define B_CTRL_LED0 0x04 /* LED 0 control */
  346. #define B_CTRL_FWRE_0 0x02 /* Flash write enable */
  347. #define B_CTRL_FWPT_0 0x01 /* Flash write protect */
  348. #endif
  349. /* BOARD_STAT bit definitions */
  350. #define B_STAT_WDGE 0x80
  351. #define B_STAT_WDGS 0x40
  352. #define B_STAT_WRST 0x20
  353. #define B_STAT_KRST 0x10
  354. #define B_STAT_CSW3 0x08 /* sitch bit 3 status */
  355. #define B_STAT_CSW2 0x04 /* sitch bit 2 status */
  356. #define B_STAT_CSW1 0x02 /* sitch bit 1 status */
  357. #define B_STAT_CSW0 0x01 /* sitch bit 0 status */
  358. /*---------------------------------------------------------------------*/
  359. /* Display addresses */
  360. /*---------------------------------------------------------------------*/
  361. #define DISP_UDC_RAM (DISPLAY_BASE + 0x08) /* UDC RAM */
  362. #define DISP_CHR_RAM (DISPLAY_BASE + 0x18) /* character Ram */
  363. #define DISP_FLASH (DISPLAY_BASE + 0x20) /* Flash Ram */
  364. #define DISP_UDC_ADR *((volatile uchar*)(DISPLAY_BASE + 0x00)) /* UDC Address Reg. */
  365. #define DISP_CWORD *((volatile uchar*)(DISPLAY_BASE + 0x10)) /* Control Word Reg. */
  366. #define DISP_DIG0 *((volatile uchar*)(DISP_CHR_RAM + 0x00)) /* Digit 0 address */
  367. #define DISP_DIG1 *((volatile uchar*)(DISP_CHR_RAM + 0x01)) /* Digit 0 address */
  368. #define DISP_DIG2 *((volatile uchar*)(DISP_CHR_RAM + 0x02)) /* Digit 0 address */
  369. #define DISP_DIG3 *((volatile uchar*)(DISP_CHR_RAM + 0x03)) /* Digit 0 address */
  370. #define DISP_DIG4 *((volatile uchar*)(DISP_CHR_RAM + 0x04)) /* Digit 0 address */
  371. #define DISP_DIG5 *((volatile uchar*)(DISP_CHR_RAM + 0x05)) /* Digit 0 address */
  372. #define DISP_DIG6 *((volatile uchar*)(DISP_CHR_RAM + 0x06)) /* Digit 0 address */
  373. #define DISP_DIG7 *((volatile uchar*)(DISP_CHR_RAM + 0x07)) /* Digit 0 address */
  374. /*-----------------------------------------------------------------------
  375. * PCI stuff
  376. *-----------------------------------------------------------------------
  377. */
  378. #define CONFIG_PCI /* include pci support */
  379. #define CONFIG_SYS_EARLY_PCI_INIT
  380. #undef CONFIG_PCI_PNP
  381. #undef CONFIG_PCI_SCAN_SHOW
  382. #define CONFIG_NET_MULTI /* Multi ethernet cards support */
  383. #define CONFIG_EEPRO100
  384. #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  385. #define PCI_ENET0_IOADDR 0x82000000
  386. #define PCI_ENET0_MEMADDR 0x82000000
  387. #define PCI_PLX9030_IOADDR 0x82100000
  388. #define PCI_PLX9030_MEMADDR 0x82100000
  389. /*-----------------------------------------------------------------------
  390. * PCMCIA stuff
  391. *-----------------------------------------------------------------------
  392. */
  393. #define CONFIG_I82365
  394. #define CONFIG_SYS_PCMCIA_MEM_ADDR PCMCIA_MEM_BASE
  395. #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x1000
  396. #define CONFIG_PCMCIA_SLOT_A
  397. /*-----------------------------------------------------------------------
  398. * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  399. *-----------------------------------------------------------------------
  400. */
  401. #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  402. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  403. #undef CONFIG_IDE_RESET /* reset for IDE not supported */
  404. #define CONFIG_IDE_LED /* LED for IDE is supported */
  405. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  406. #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  407. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  408. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
  409. #define CONFIG_SYS_ATA_DATA_OFFSET CONFIG_SYS_PCMCIA_MEM_SIZE
  410. /* Offset for normal register accesses */
  411. #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  412. /* Offset for alternate registers */
  413. #define CONFIG_SYS_ATA_ALT_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x400)
  414. #define CONFIG_DOS_PARTITION
  415. #endif /* __CONFIG_H */