CANBT.h 8.2 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405CR 1 /* This is a PPC405CR CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_CANBT 1 /* ...on a CANBT board */
  35. #define CONFIG_SYS_TEXT_BASE 0xFFFC0000
  36. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  37. #define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
  38. #define CONFIG_BAUDRATE 115200
  39. #define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
  40. #undef CONFIG_BOOTARGS
  41. #define CONFIG_BOOTCOMMAND \
  42. "setenv bootargs root=/dev/ram rw console=ttyS0,115200; " \
  43. "bootm ffe00000 ffe80000"
  44. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  45. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  46. #undef CONFIG_PCI_PNP /* no pci plug-and-play */
  47. #define CONFIG_PHY_ADDR 0 /* PHY address */
  48. /*
  49. * BOOTP options
  50. */
  51. #define CONFIG_BOOTP_BOOTFILESIZE
  52. #define CONFIG_BOOTP_BOOTPATH
  53. #define CONFIG_BOOTP_GATEWAY
  54. #define CONFIG_BOOTP_HOSTNAME
  55. /*
  56. * Command line configuration.
  57. */
  58. #include <config_cmd_default.h>
  59. #define CONFIG_CMD_IRQ
  60. #define CONFIG_CMD_EEPROM
  61. #undef CONFIG_CMD_NET
  62. #undef CONFIG_WATCHDOG /* watchdog disabled */
  63. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  64. /*
  65. * Miscellaneous configurable options
  66. */
  67. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  68. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  69. #if defined(CONFIG_CMD_KGDB)
  70. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  71. #else
  72. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  73. #endif
  74. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  75. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  76. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  77. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  78. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  79. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  80. #define CONFIG_CONS_INDEX 1 /* Use UART0 */
  81. #define CONFIG_SYS_NS16550
  82. #define CONFIG_SYS_NS16550_SERIAL
  83. #define CONFIG_SYS_NS16550_REG_SIZE 1
  84. #define CONFIG_SYS_NS16550_CLK get_serial_clock()
  85. #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
  86. /* The following table includes the supported baudrates */
  87. #define CONFIG_SYS_BAUDRATE_TABLE \
  88. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  89. 57600, 115200, 230400, 460800, 921600 }
  90. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  91. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  92. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  93. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  94. /*-----------------------------------------------------------------------
  95. * Start addresses for the final memory configuration
  96. * (Set up by the startup code)
  97. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  98. */
  99. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  100. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
  101. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  102. #define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
  103. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  104. /*
  105. * For booting Linux, the board info and command line data
  106. * have to be in the first 8 MB of memory, since this is
  107. * the maximum mapped by the Linux kernel during initialization.
  108. */
  109. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  110. /*-----------------------------------------------------------------------
  111. * FLASH organization
  112. */
  113. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  114. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  115. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  116. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  117. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  118. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  119. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  120. /*
  121. * The following defines are added for buggy IOP480 byte interface.
  122. * All other boards should use the standard values (CPCI405 etc.)
  123. */
  124. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  125. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  126. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  127. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  128. #if 0 /* Use FLASH for environment variables */
  129. #define CONFIG_ENV_IS_IN_FLASH 1
  130. #define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
  131. #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
  132. #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
  133. #else /* Use EEPROM for environment variables */
  134. #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
  135. #define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
  136. #define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */
  137. /* total size of a CAT24WC08 is 1024 bytes */
  138. #endif
  139. /*-----------------------------------------------------------------------
  140. * I2C EEPROM (CAT24WC08) for environment
  141. */
  142. #define CONFIG_HARD_I2C /* I2C with hardware support */
  143. #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
  144. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  145. #define CONFIG_SYS_I2C_SLAVE 0x7F
  146. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  147. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
  148. /* mask of address bits that overflow into the "EEPROM chip address" */
  149. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  150. /*
  151. * Init Memory Controller:
  152. *
  153. * BR0/1 and OR0/1 (FLASH)
  154. */
  155. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  156. #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
  157. /*-----------------------------------------------------------------------
  158. * External Bus Controller (EBC) Setup
  159. */
  160. /* Memory Bank 0 (Flash Bank 0) initialization */
  161. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  162. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  163. /* Memory Bank 1 (CAN/USB) initialization */
  164. #define CONFIG_SYS_EBC_PB1AP 0x010053C0 /* enable Ready, BEM=1 */
  165. #define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  166. /* Memory Bank 2 (Misc-IO/LEDs) initialization */
  167. #define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */
  168. #define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
  169. /* Memory Bank 3 (CAN Features) initialization */
  170. #define CONFIG_SYS_EBC_PB3AP 0x80000040 /* no Ready, BEM=1 */
  171. #define CONFIG_SYS_EBC_PB3CR 0xF021C000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=32bit */
  172. /*-----------------------------------------------------------------------
  173. * Definitions for initial stack pointer and data area (in RAM)
  174. */
  175. #define CONFIG_SYS_INIT_RAM_ADDR 0x00ef0000 /* inside of SDRAM */
  176. #define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
  177. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  178. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  179. #endif /* __CONFIG_H */