BC3450.h 17 KB

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  1. /*
  2. * -- Version 1.1 --
  3. *
  4. * (C) Copyright 2003-2005
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2004-2005
  8. * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
  9. *
  10. * (C) Copyright 2005
  11. * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
  12. *
  13. * History:
  14. * 1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
  15. *
  16. * See file CREDITS for list of people who contributed to this
  17. * project.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License as
  21. * published by the Free Software Foundation; either version 2 of
  22. * the License, or (at your option) any later version.
  23. *
  24. * This program is distributed in the hope that it will be useful,
  25. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  27. * GNU General Public License for more details.
  28. *
  29. * You should have received a copy of the GNU General Public License
  30. * along with this program; if not, write to the Free Software
  31. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32. * MA 02111-1307 USA
  33. */
  34. #ifndef __CONFIG_H
  35. #define __CONFIG_H
  36. /*
  37. * High Level Configuration Options
  38. */
  39. #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
  40. #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
  41. #define CONFIG_TQM5200 1 /* ... on a TQM5200 module */
  42. #define CONFIG_BC3450 1 /* ... on a BC3450 mainboard */
  43. #define CONFIG_BC3450_PS2 1 /* + a PS/2 converter onboard */
  44. #define CONFIG_BC3450_IDE 1 /* + IDE drives (Compact Flash) */
  45. #define CONFIG_BC3450_USB 1 /* + USB support */
  46. # define CONFIG_FAT 1 /* + FAT support */
  47. # define CONFIG_EXT2 1 /* + EXT2 support */
  48. #undef CONFIG_BC3450_BUZZER /* + Buzzer onboard */
  49. #undef CONFIG_BC3450_CAN /* + CAN transceiver */
  50. #undef CONFIG_BC3450_DS1340 /* + a RTC DS1340 onboard */
  51. #undef CONFIG_BC3450_DS3231 /* + a RTC DS3231 onboard tbd */
  52. #undef CONFIG_BC3450_AC97 /* + AC97 on PSC2, tbd */
  53. #define CONFIG_BC3450_FP 1 /* + enable FP O/P */
  54. #undef CONFIG_BC3450_CRT /* + enable CRT O/P (Debug only!) */
  55. /*
  56. * Valid values for CONFIG_SYS_TEXT_BASE are:
  57. * 0xFC000000 boot low (standard configuration with room for
  58. * max 64 MByte Flash ROM)
  59. * 0x00100000 boot from RAM (for testing only)
  60. */
  61. #ifndef CONFIG_SYS_TEXT_BASE
  62. #define CONFIG_SYS_TEXT_BASE 0xFC000000
  63. #endif
  64. #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
  65. #define CONFIG_HIGH_BATS 1 /* High BATs supported */
  66. /*
  67. * Serial console configuration
  68. */
  69. #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
  70. #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
  71. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  72. /*
  73. * AT-PS/2 Multiplexer
  74. */
  75. #ifdef CONFIG_BC3450_PS2
  76. # define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
  77. # define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
  78. # define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
  79. # define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */
  80. # define CONFIG_BOARD_EARLY_INIT_R
  81. #endif /* CONFIG_BC3450_PS2 */
  82. /*
  83. * PCI Mapping:
  84. * 0x40000000 - 0x4fffffff - PCI Memory
  85. * 0x50000000 - 0x50ffffff - PCI IO Space
  86. */
  87. # define CONFIG_PCI 1
  88. # define CONFIG_PCI_PNP 1
  89. /* #define CONFIG_PCI_SCAN_SHOW 1 */
  90. #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  91. #define CONFIG_PCI_MEM_BUS 0x40000000
  92. #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  93. #define CONFIG_PCI_MEM_SIZE 0x10000000
  94. #define CONFIG_PCI_IO_BUS 0x50000000
  95. #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  96. #define CONFIG_PCI_IO_SIZE 0x01000000
  97. #define CONFIG_NET_MULTI 1
  98. /*#define CONFIG_EEPRO100 XXX - FIXME: conflicts when CONFIG_MII is enabled */
  99. #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  100. #define CONFIG_NS8382X 1
  101. /*
  102. * Video console
  103. */
  104. # define CONFIG_VIDEO
  105. # define CONFIG_VIDEO_SM501
  106. # define CONFIG_VIDEO_SM501_32BPP
  107. # define CONFIG_CFB_CONSOLE
  108. # define CONFIG_VIDEO_LOGO
  109. # define CONFIG_VGA_AS_SINGLE_DEVICE
  110. # define CONFIG_CONSOLE_EXTRA_INFO /* display Board/Device-Infos */
  111. # define CONFIG_VIDEO_SW_CURSOR
  112. # define CONFIG_SPLASH_SCREEN
  113. # define CONFIG_SYS_CONSOLE_IS_IN_ENV
  114. /*
  115. * Partitions
  116. */
  117. #define CONFIG_MAC_PARTITION
  118. #define CONFIG_DOS_PARTITION
  119. #define CONFIG_ISO_PARTITION
  120. /*
  121. * USB
  122. */
  123. #ifdef CONFIG_BC3450_USB
  124. # define CONFIG_USB_OHCI
  125. # define CONFIG_USB_STORAGE
  126. #endif /* CONFIG_BC3450_USB */
  127. /*
  128. * POST support
  129. */
  130. #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
  131. CONFIG_SYS_POST_CPU | \
  132. CONFIG_SYS_POST_I2C)
  133. #ifdef CONFIG_POST
  134. /* preserve space for the post_word at end of on-chip SRAM */
  135. # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
  136. #endif /* CONFIG_POST */
  137. /*
  138. * BOOTP options
  139. */
  140. #define CONFIG_BOOTP_BOOTFILESIZE
  141. #define CONFIG_BOOTP_BOOTPATH
  142. #define CONFIG_BOOTP_GATEWAY
  143. #define CONFIG_BOOTP_HOSTNAME
  144. /*
  145. * Command line configuration.
  146. */
  147. #include <config_cmd_default.h>
  148. #define CONFIG_CMD_ASKENV
  149. #define CONFIG_CMD_DATE
  150. #define CONFIG_CMD_DHCP
  151. #define CONFIG_CMD_ECHO
  152. #define CONFIG_CMD_EEPROM
  153. #define CONFIG_CMD_I2C
  154. #define CONFIG_CMD_JFFS2
  155. #define CONFIG_CMD_MII
  156. #define CONFIG_CMD_NFS
  157. #define CONFIG_CMD_PING
  158. #define CONFIG_CMD_REGINFO
  159. #define CONFIG_CMD_SNTP
  160. #define CONFIG_CMD_BSP
  161. #ifdef CONFIG_VIDEO
  162. #define CONFIG_CMD_BMP
  163. #endif
  164. #ifdef CONFIG_BC3450_IDE
  165. #define CONFIG_CMD_IDE
  166. #endif
  167. #if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
  168. #ifdef CONFIG_FAT
  169. #define CONFIG_CMD_FAT
  170. #endif
  171. #ifdef CONFIG_EXT2
  172. #define CONFIG_CMD_EXT2
  173. #endif
  174. #endif
  175. #ifdef CONFIG_BC3450_USB
  176. #define CONFIG_CMD_USB
  177. #endif
  178. #ifdef CONFIG_PCI
  179. #define CONFIG_CMD_PCI
  180. #endif
  181. #ifdef CONFIG_POST
  182. #define CONFIG_CMD_DIAG
  183. #endif
  184. #define CONFIG_TIMESTAMP /* display image timestamps */
  185. #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) /* Boot low */
  186. # define CONFIG_SYS_LOWBOOT 1
  187. #endif
  188. /*
  189. * Autobooting
  190. */
  191. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  192. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  193. #define CONFIG_PREBOOT "echo;" \
  194. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  195. "echo;"
  196. #undef CONFIG_BOOTARGS
  197. #define CONFIG_EXTRA_ENV_SETTINGS \
  198. "netdev=eth0\0" \
  199. "ipaddr=192.168.1.10\0" \
  200. "serverip=192.168.1.3\0" \
  201. "netmask=255.255.255.0\0" \
  202. "hostname=bc3450\0" \
  203. "rootpath=/opt/eldk/ppc_6xx\0" \
  204. "kernel_addr=fc0a0000\0" \
  205. "ramdisk_addr=fc1c0000\0" \
  206. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  207. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  208. "nfsroot=$(serverip):$(rootpath)\0" \
  209. "ideargs=setenv bootargs root=/dev/hda2 ro\0" \
  210. "addip=setenv bootargs $(bootargs) " \
  211. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
  212. ":$(hostname):$(netdev):off panic=1\0" \
  213. "addcons=setenv bootargs $(bootargs) " \
  214. "console=ttyS0,$(baudrate) console=tty0\0" \
  215. "flash_self=run ramargs addip addcons;" \
  216. "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  217. "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0" \
  218. "net_nfs=tftp 200000 $(bootfile); " \
  219. "run nfsargs addip addcons; bootm\0" \
  220. "ide_nfs=run nfsargs addip addcons; " \
  221. "disk 200000 0:1; bootm\0" \
  222. "ide_ide=run ideargs addip addcons; " \
  223. "disk 200000 0:1; bootm\0" \
  224. "usb_self=run usbload; run ramargs addip addcons; " \
  225. "bootm 200000 400000\0" \
  226. "usbload=usb reset; usb scan; usbboot 200000 0:1; " \
  227. "usbboot 400000 0:2\0" \
  228. "bootfile=uImage\0" \
  229. "load=tftp 200000 $(u-boot)\0" \
  230. "u-boot=u-boot.bin\0" \
  231. "update=protect off FC000000 FC05FFFF;" \
  232. "erase FC000000 FC05FFFF;" \
  233. "cp.b 200000 FC000000 $(filesize);" \
  234. "protect on FC000000 FC05FFFF\0" \
  235. ""
  236. #define CONFIG_BOOTCOMMAND "run flash_self"
  237. /*
  238. * IPB Bus clocking configuration.
  239. */
  240. #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
  241. /*
  242. * PCI Bus clocking configuration
  243. *
  244. * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
  245. * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
  246. * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
  247. */
  248. #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
  249. # define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */
  250. #endif
  251. /*
  252. * I2C configuration
  253. */
  254. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  255. #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
  256. /*
  257. * I2C clock frequency
  258. *
  259. * Please notice, that the resulting clock frequency could differ from the
  260. * configured value. This is because the I2C clock is derived from system
  261. * clock over a frequency divider with only a few divider values. U-boot
  262. * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
  263. * approximation allways lies below the configured value, never above.
  264. */
  265. #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
  266. #define CONFIG_SYS_I2C_SLAVE 0x7F
  267. /*
  268. * EEPROM configuration for I²C EEPROM M24C32
  269. * M24C64 should work also. For other EEPROMs config should be verified.
  270. *
  271. * The TQM5200 module may hold an EEPROM at address 0x50.
  272. */
  273. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x (TQM) */
  274. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  275. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
  276. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
  277. /*
  278. * RTC configuration
  279. */
  280. #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
  281. # define CONFIG_RTC_M41T11 1
  282. # define CONFIG_SYS_I2C_RTC_ADDR 0x68
  283. #else
  284. # define CONFIG_RTC_MPC5200 1 /* use MPC5200 internal RTC */
  285. # define CONFIG_BOARD_EARLY_INIT_R
  286. #endif
  287. /*
  288. * Flash configuration
  289. */
  290. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE /* 0xFC000000 */
  291. /* use CFI flash driver if no module variant is spezified */
  292. #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
  293. #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
  294. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START }
  295. #define CONFIG_SYS_FLASH_EMPTY_INFO
  296. #define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */
  297. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
  298. #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
  299. #if !defined(CONFIG_SYS_LOWBOOT)
  300. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
  301. #else /* CONFIG_SYS_LOWBOOT */
  302. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
  303. #endif /* CONFIG_SYS_LOWBOOT */
  304. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
  305. (= chip selects) */
  306. #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
  307. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  308. /* Dynamic MTD partition support */
  309. #define CONFIG_CMD_MTDPARTS
  310. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  311. #define CONFIG_FLASH_CFI_MTD
  312. #define MTDIDS_DEFAULT "nor0=TQM5200-0"
  313. #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
  314. "1408k(kernel)," \
  315. "2m(initrd)," \
  316. "4m(small-fs)," \
  317. "16m(big-fs)," \
  318. "8m(misc)"
  319. /*
  320. * Environment settings
  321. */
  322. #define CONFIG_ENV_IS_IN_FLASH 1
  323. #define CONFIG_ENV_SIZE 0x10000
  324. #define CONFIG_ENV_SECT_SIZE 0x20000
  325. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
  326. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  327. /*
  328. * Memory map
  329. */
  330. #define CONFIG_SYS_MBAR 0xF0000000
  331. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  332. #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  333. /* Use ON-Chip SRAM until RAM will be available */
  334. #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
  335. #ifdef CONFIG_POST
  336. /* preserve space for the post_word at end of on-chip SRAM */
  337. # define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
  338. #else
  339. # define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
  340. #endif /*CONFIG_POST*/
  341. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  342. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  343. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  344. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  345. # define CONFIG_SYS_RAMBOOT 1
  346. #endif
  347. #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
  348. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  349. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  350. /*
  351. * Ethernet configuration
  352. *
  353. * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
  354. */
  355. #define CONFIG_MPC5xxx_FEC 1
  356. #define CONFIG_MPC5xxx_FEC_MII100
  357. #undef CONFIG_MPC5xxx_MII10
  358. #define CONFIG_PHY_ADDR 0x00
  359. /*
  360. * GPIO configuration on BC3450
  361. *
  362. * PSC1: UART1 (Service-UART) [0x xxxxxxx4]
  363. * PSC2: UART2 [0x xxxxxx4x]
  364. * or: AC/97 if CONFIG_BC3450_AC97 [0x xxxxxx2x]
  365. * PSC3: USB2 [0x xxxxx1xx]
  366. * USB: UART4(ext.)/UART5(int.) [0x xxxx2xxx]
  367. * (this has to match
  368. * CONFIG_USB_CONFIG which is
  369. * used by usb_ohci.c to set
  370. * the USB ports)
  371. * Eth: 10/100Mbit Ethernet [0x xxx0xxxx]
  372. * (this is reset to '5'
  373. * in FEC driver: fec.c)
  374. * PSC6: UART6 (int. to PS/2 contr.) [0x xx5xxxxx]
  375. * ATA/CS: ??? [0x x1xxxxxx]
  376. * FIXME! UM Fig 2-10 suggests [0x x0xxxxxx]
  377. * CS1: Use Pin gpio_wkup_6 as second
  378. * SDRAM chip select (mem_cs1)
  379. * Timer: CAN2 / SPI
  380. * I2C: CAN1 / I²C2 [0x bxxxxxxx]
  381. */
  382. #ifdef CONFIG_BC3450_AC97
  383. # define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502124
  384. #else /* PSC2=UART2 */
  385. # define CONFIG_SYS_GPS_PORT_CONFIG 0xb1502144
  386. #endif
  387. /*
  388. * Miscellaneous configurable options
  389. */
  390. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  391. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  392. #if defined(CONFIG_CMD_KGDB)
  393. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  394. #else
  395. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  396. #endif
  397. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  398. #define CONFIG_SYS_MAXARGS 16 /* max no of command args */
  399. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg. Buffer Size */
  400. #define CONFIG_SYS_ALT_MEMTEST /* Enable an alternative, */
  401. /* more extensive mem test */
  402. #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
  403. #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  404. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  405. #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */
  406. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
  407. #if defined(CONFIG_CMD_KGDB)
  408. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  409. #endif
  410. /*
  411. * Enable loopw command.
  412. */
  413. #define CONFIG_LOOPW
  414. /*
  415. * Various low-level settings
  416. */
  417. #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
  418. #define CONFIG_SYS_HID0_FINAL HID0_ICE
  419. #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
  420. #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
  421. #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
  422. # define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
  423. #else
  424. # define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
  425. #endif
  426. #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
  427. #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
  428. /* automatic configuration of chip selects */
  429. #ifdef CONFIG_TQM5200
  430. # define CONFIG_LAST_STAGE_INIT
  431. #endif /* CONFIG_TQM5200 */
  432. /*
  433. * SRAM - Do not map below 2 GB in address space, because this area is used
  434. * for SDRAM autosizing.
  435. */
  436. #ifdef CONFIG_TQM5200
  437. # define CONFIG_SYS_CS2_START 0xE5000000
  438. # define CONFIG_SYS_CS2_SIZE 0x100000 /* 1 MByte */
  439. # define CONFIG_SYS_CS2_CFG 0x0004D930
  440. #endif /* CONFIG_TQM5200 */
  441. /*
  442. * Grafic controller - Do not map below 2 GB in address space, because this
  443. * area is used for SDRAM autosizing.
  444. */
  445. #ifdef CONFIG_TQM5200
  446. # define SM501_FB_BASE 0xE0000000
  447. # define CONFIG_SYS_CS1_START (SM501_FB_BASE)
  448. # define CONFIG_SYS_CS1_SIZE 0x4000000 /* 64 MByte */
  449. # define CONFIG_SYS_CS1_CFG 0x8F48FF70
  450. # define SM501_MMIO_BASE CONFIG_SYS_CS1_START + 0x03E00000
  451. #endif /* CONFIG_TQM5200 */
  452. #define CONFIG_SYS_CS_BURST 0x00000000
  453. #define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for */
  454. /* flash and SM501 */
  455. #define CONFIG_SYS_RESET_ADDRESS 0xff000000
  456. /*
  457. * USB stuff
  458. */
  459. #define CONFIG_USB_CLOCK 0x0001BBBB
  460. #define CONFIG_USB_CONFIG 0x00002000 /* we're using Port 2 */
  461. /*
  462. * IDE/ATA stuff Supports IDE harddisk
  463. */
  464. #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
  465. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  466. #undef CONFIG_IDE_LED /* LED for ide not supported */
  467. #define CONFIG_IDE_RESET /* reset for ide supported */
  468. #define CONFIG_IDE_PREINIT
  469. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
  470. #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
  471. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  472. #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
  473. /* Offset for data I/O */
  474. #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
  475. /* Offset for normal register accesses */
  476. #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
  477. /* Offset for alternate registers */
  478. #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
  479. /* Interval between registers */
  480. #define CONFIG_SYS_ATA_STRIDE 4
  481. #endif /* __CONFIG_H */