BAB7xx.h 16 KB

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  1. /*
  2. * (C) Copyright 2002 ELTEC Elektronik AG
  3. * Frank Gottschling <fgottschling@eltec.de>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. #define GTREGREAD(x) 0xffffffff /* needed for debug */
  29. /*
  30. * High Level Configuration Options
  31. * (easy to change)
  32. */
  33. #define CONFIG_SYS_TEXT_BASE 0xFFF00000
  34. /* these hardware addresses are pretty bogus, please change them to
  35. suit your needs */
  36. /* first ethernet */
  37. #define CONFIG_ETHADDR 00:00:5b:ee:de:ad
  38. #define CONFIG_IPADDR 192.168.0.105
  39. #define CONFIG_SERVERIP 192.168.0.100
  40. #define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */
  41. #define CONFIG_BAUDRATE 9600 /* console baudrate */
  42. #undef CONFIG_WATCHDOG
  43. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  44. #define CONFIG_ZERO_BOOTDELAY_CHECK
  45. #undef CONFIG_BOOTARGS
  46. #define CONFIG_BOOTCOMMAND \
  47. "bootp 1000000; " \
  48. "setenv bootargs root=ramfs console=ttyS00,9600 " \
  49. "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
  50. "${netmask}:${hostname}:eth0:none; " \
  51. "bootm"
  52. #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
  53. #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
  54. /*
  55. * BOOTP options
  56. */
  57. #define CONFIG_BOOTP_SUBNETMASK
  58. #define CONFIG_BOOTP_GATEWAY
  59. #define CONFIG_BOOTP_HOSTNAME
  60. #define CONFIG_BOOTP_BOOTPATH
  61. #define CONFIG_BOOTP_BOOTFILESIZE
  62. /*
  63. * Command line configuration.
  64. */
  65. #include <config_cmd_default.h>
  66. #define CONFIG_CMD_PCI
  67. #define CONFIG_CMD_JFFS2
  68. #define CONFIG_CMD_SCSI
  69. #define CONFIG_CMD_IDE
  70. #define CONFIG_CMD_DATE
  71. #define CONFIG_CMD_FDC
  72. #define CONFIG_CMD_ELF
  73. /*
  74. * Miscellaneous configurable options
  75. */
  76. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  77. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  78. /*
  79. * choose between COM1 and COM2 as serial console
  80. */
  81. #define CONFIG_CONS_INDEX 1
  82. #if defined(CONFIG_CMD_KGDB)
  83. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  84. #else
  85. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  86. #endif
  87. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  88. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  89. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  90. #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
  91. #define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
  92. #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
  93. #define CONFIG_SYS_HZ 1000 /* dec. freq: 1 ms ticks */
  94. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  95. /*
  96. * Low Level Configuration Settings
  97. * (address mappings, register initial values, etc.)
  98. * You should know what you are doing if you make changes here.
  99. */
  100. #define CONFIG_SYS_BOARD_ASM_INIT
  101. #define CONFIG_MISC_INIT_R
  102. /*
  103. * Choose the address mapping scheme for the MPC106 mem controller.
  104. * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
  105. */
  106. #define CONFIG_SYS_ADDRESS_MAP_A
  107. #ifdef CONFIG_SYS_ADDRESS_MAP_A
  108. #define CONFIG_SYS_PCI_MEMORY_BUS 0x80000000
  109. #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
  110. #define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
  111. #define CONFIG_SYS_PCI_MEM_BUS 0x00000000
  112. #define CONFIG_SYS_PCI_MEM_PHYS 0xc0000000
  113. #define CONFIG_SYS_PCI_MEM_SIZE 0x3f000000
  114. #define CONFIG_SYS_ISA_MEM_BUS 0
  115. #define CONFIG_SYS_ISA_MEM_PHYS 0
  116. #define CONFIG_SYS_ISA_MEM_SIZE 0
  117. #define CONFIG_SYS_PCI_IO_BUS 0x1000
  118. #define CONFIG_SYS_PCI_IO_PHYS 0x81000000
  119. #define CONFIG_SYS_PCI_IO_SIZE 0x01000000-CONFIG_SYS_PCI_IO_BUS
  120. #define CONFIG_SYS_ISA_IO_BUS 0x00000000
  121. #define CONFIG_SYS_ISA_IO_PHYS 0x80000000
  122. #define CONFIG_SYS_ISA_IO_SIZE 0x00800000
  123. #else
  124. #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
  125. #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
  126. #define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
  127. #define CONFIG_SYS_PCI_MEM_BUS 0x80000000
  128. #define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
  129. #define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
  130. #define CONFIG_SYS_ISA_MEM_BUS 0x00000000
  131. #define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
  132. #define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
  133. #define CONFIG_SYS_PCI_IO_BUS 0x00800000
  134. #define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
  135. #define CONFIG_SYS_PCI_IO_SIZE 0x00400000
  136. #define CONFIG_SYS_ISA_IO_BUS 0x00000000
  137. #define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
  138. #define CONFIG_SYS_ISA_IO_SIZE 0x00800000
  139. #endif /*CONFIG_SYS_ADDRESS_MAP_A */
  140. #define CONFIG_SYS_60X_PCI_MEM_OFFSET 0x00000000
  141. /* driver defines FDC,IDE,... */
  142. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
  143. #define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
  144. #define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
  145. /*
  146. * Start addresses for the final memory configuration
  147. * (Set up by the startup code)
  148. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  149. */
  150. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  151. #define CONFIG_SYS_FLASH_BASE 0xfff00000
  152. /*
  153. * Definitions for initial stack pointer and data area
  154. */
  155. #define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
  156. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
  157. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  158. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  159. /*
  160. * Flash mapping/organization on the MPC10x.
  161. */
  162. #define FLASH_BASE0_PRELIM 0xff800000
  163. #define FLASH_BASE1_PRELIM 0xffc00000
  164. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  165. #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
  166. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  167. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  168. /*
  169. * JFFS2 partitions
  170. *
  171. */
  172. /* No command line, one static partition */
  173. #undef CONFIG_CMD_MTDPARTS
  174. #define CONFIG_JFFS2_DEV "nor"
  175. #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
  176. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  177. /* mtdparts command line support
  178. *
  179. * Note: fake mtd_id used, no linux mtd map file
  180. */
  181. /*
  182. #define CONFIG_CMD_MTDPARTS
  183. #define MTDIDS_DEFAULT "nor0=bab7xx-0"
  184. #define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)"
  185. */
  186. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  187. #define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
  188. #define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
  189. #undef CONFIG_SYS_MEMTEST
  190. /*
  191. * Environment settings
  192. */
  193. #define CONFIG_ENV_OVERWRITE
  194. #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
  195. #define CONFIG_SYS_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
  196. #define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
  197. /*
  198. * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
  199. * user applications can use the remaining space for other purposes.
  200. */
  201. #define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x800)
  202. #define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x400)
  203. #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
  204. #define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
  205. /*
  206. * Serial devices
  207. */
  208. #define CONFIG_SYS_NS16550
  209. #define CONFIG_SYS_NS16550_SERIAL
  210. #define CONFIG_SYS_NS16550_REG_SIZE 1
  211. #define CONFIG_SYS_NS16550_CLK 1843200
  212. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
  213. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
  214. /*
  215. * PCI stuff
  216. */
  217. #define CONFIG_PCI /* include pci support */
  218. #define CONFIG_SYS_EARLY_PCI_INIT
  219. #define CONFIG_PCI_PNP /* pci plug-and-play */
  220. #define CONFIG_PCI_HOST PCI_HOST_AUTO
  221. #undef CONFIG_PCI_SCAN_SHOW
  222. /*
  223. * Video console (graphic: SMI LynxEM, keyboard: i8042)
  224. */
  225. #define CONFIG_VIDEO
  226. #define CONFIG_CFB_CONSOLE
  227. #define CONFIG_VIDEO_SMI_LYNXEM
  228. #define CONFIG_I8042_KBD
  229. #define CONFIG_VIDEO_LOGO
  230. #define CONFIG_CONSOLE_TIME
  231. #define CONFIG_CONSOLE_EXTRA_INFO
  232. #define CONFIG_CONSOLE_CURSOR
  233. #define CONFIG_SYS_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */
  234. /*
  235. * IDE/SCSI globals
  236. */
  237. #ifndef __ASSEMBLY__
  238. extern unsigned int eltec_board;
  239. extern unsigned int ata_reset_time;
  240. extern unsigned int scsi_reset_time;
  241. extern unsigned short scsi_dev_id;
  242. extern unsigned int scsi_max_scsi_id;
  243. extern unsigned char scsi_sym53c8xx_ccf;
  244. #endif
  245. /*
  246. * ATAPI Support (experimental)
  247. */
  248. #define CONFIG_ATAPI
  249. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
  250. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
  251. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_60X_PCI_IO_OFFSET /* base address */
  252. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
  253. #define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
  254. #define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
  255. #define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
  256. #define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
  257. #define ATA_RESET_TIME (ata_reset_time)
  258. #undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
  259. #undef CONFIG_IDE_LED /* no led for ide supported */
  260. /*
  261. * SCSI support (experimental) only SYM53C8xx supported
  262. */
  263. #define CONFIG_SCSI_SYM53C8XX
  264. #define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */
  265. #define CONFIG_SYS_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */
  266. #define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
  267. #define CONFIG_SYS_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */
  268. #define CONFIG_SYS_SCSI_MAX_DEVICE (15 * CONFIG_SYS_SCSI_MAX_LUN) /* max. Target devices */
  269. #define CONFIG_SYS_SCSI_SPIN_UP_TIME (scsi_reset_time)
  270. /*
  271. * Partion suppport
  272. */
  273. #define CONFIG_DOS_PARTITION
  274. #define CONFIG_MAC_PARTITION
  275. #define CONFIG_ISO_PARTITION
  276. /*
  277. * Winbond Configuration
  278. */
  279. #define CONFIG_WINBOND_83C553 1 /* has a winbond bridge */
  280. #define CONFIG_SYS_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
  281. #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
  282. #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
  283. /*
  284. * NS87308 Configuration
  285. */
  286. #define CONFIG_NS87308 /* Nat Semi super-io cntr on ISA bus */
  287. #define CONFIG_SYS_NS87308_BADDR_10 1
  288. #define CONFIG_SYS_NS87308_DEVS (CONFIG_SYS_NS87308_UART1 | \
  289. CONFIG_SYS_NS87308_UART2 | \
  290. CONFIG_SYS_NS87308_KBC1 | \
  291. CONFIG_SYS_NS87308_MOUSE | \
  292. CONFIG_SYS_NS87308_FDC | \
  293. CONFIG_SYS_NS87308_RARP | \
  294. CONFIG_SYS_NS87308_GPIO | \
  295. CONFIG_SYS_NS87308_POWRMAN | \
  296. CONFIG_SYS_NS87308_RTC_APC )
  297. #define CONFIG_SYS_NS87308_PS2MOD
  298. #define CONFIG_SYS_NS87308_GPIO_BASE 0x0220
  299. #define CONFIG_SYS_NS87308_PWMAN_BASE 0x0460
  300. #define CONFIG_SYS_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */
  301. /*
  302. * set up the NVRAM access registers
  303. * NVRAM's controlled by the configurable CS line from the 87308
  304. */
  305. #define CONFIG_SYS_NS87308_CS0_BASE 0x0076
  306. #define CONFIG_SYS_NS87308_CS0_CONF 0x40
  307. #define CONFIG_SYS_NS87308_CS1_BASE 0x0070
  308. #define CONFIG_SYS_NS87308_CS1_CONF 0x1C
  309. #define CONFIG_SYS_NS87308_CS2_BASE 0x0071
  310. #define CONFIG_SYS_NS87308_CS2_CONF 0x1C
  311. #define CONFIG_RTC_MK48T59
  312. /*
  313. * Initial BATs
  314. */
  315. #if 1
  316. #define CONFIG_SYS_IBAT0L 0
  317. #define CONFIG_SYS_IBAT0U 0
  318. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
  319. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
  320. #define CONFIG_SYS_IBAT1L 0
  321. #define CONFIG_SYS_IBAT1U 0
  322. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  323. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  324. #define CONFIG_SYS_IBAT2L 0
  325. #define CONFIG_SYS_IBAT2U 0
  326. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  327. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  328. #define CONFIG_SYS_IBAT3L 0
  329. #define CONFIG_SYS_IBAT3U 0
  330. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  331. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  332. #else
  333. /* SDRAM */
  334. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
  335. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  336. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
  337. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
  338. /* address range for flashes */
  339. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
  340. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
  341. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  342. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  343. /* ISA IO space */
  344. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
  345. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
  346. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  347. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  348. /* ISA memory space */
  349. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
  350. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
  351. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  352. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  353. #endif
  354. /*
  355. * Speed settings are board specific
  356. */
  357. #ifndef __ASSEMBLY__
  358. extern unsigned long bab7xx_get_bus_freq (void);
  359. extern unsigned long bab7xx_get_gclk_freq (void);
  360. #endif
  361. #define CONFIG_SYS_BUS_CLK bab7xx_get_bus_freq()
  362. #define CONFIG_SYS_CPU_CLK bab7xx_get_gclk_freq()
  363. /*
  364. * For booting Linux, the board info and command line data
  365. * have to be in the first 8 MB of memory, since this is
  366. * the maximum mapped by the Linux kernel during initialization.
  367. */
  368. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  369. /*
  370. * Cache Configuration
  371. */
  372. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
  373. #if defined(CONFIG_CMD_KGDB)
  374. #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  375. #endif
  376. /*
  377. * L2 Cache Configuration is board specific for BAB740/BAB750
  378. * Init values read from revision srom.
  379. */
  380. #undef CONFIG_SYS_L2
  381. #define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
  382. L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
  383. #define L2_ENABLE (L2_INIT | L2CR_L2E)
  384. #define CONFIG_SYS_L2_BAB7xx
  385. #define CONFIG_NET_MULTI /* Multi ethernet cards support */
  386. #define CONFIG_TULIP
  387. #define CONFIG_TULIP_SELECT_MEDIA
  388. #endif /* __CONFIG_H */