ATUM8548.h 13 KB

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  1. /*
  2. * Copyright 2007
  3. * Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
  4. *
  5. * Copyright 2004, 2007 Freescale Semiconductor.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * atum8548 board configuration file
  27. *
  28. * Please refer to doc/README.atum8548 for more info.
  29. *
  30. */
  31. #ifndef __CONFIG_H
  32. #define __CONFIG_H
  33. /* Debug Options, Disable in production
  34. #define ET_DEBUG 1
  35. #define CONFIG_PANIC_HANG 1
  36. #define DEBUG 1
  37. */
  38. /* CPLD Configuration Options */
  39. #define MPC85xx_ATUM_CLKOCR 0x80000002
  40. /* High Level Configuration Options */
  41. #define CONFIG_BOOKE 1 /* BOOKE */
  42. #define CONFIG_E500 1 /* BOOKE e500 family */
  43. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  44. #define CONFIG_MPC8548 1 /* MPC8548 specific */
  45. #ifndef CONFIG_SYS_TEXT_BASE
  46. #define CONFIG_SYS_TEXT_BASE 0xfff80000
  47. #endif
  48. #define CONFIG_PCI 1 /* enable any pci type devices */
  49. #define CONFIG_PCI1 1 /* PCI controller 1 */
  50. #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
  51. #define CONFIG_PCI2 1 /* PCI controller 2 */
  52. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  53. #define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
  54. #define CONFIG_ENV_OVERWRITE
  55. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  56. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  57. #define CONFIG_SYS_CLK_FREQ 33000000
  58. /*
  59. * These can be toggled for performance analysis, otherwise use default.
  60. */
  61. #define CONFIG_L2_CACHE /* toggle L2 cache */
  62. #define CONFIG_BTB /* toggle branch predition */
  63. /*
  64. * Only possible on E500 Version 2 or newer cores.
  65. */
  66. #define CONFIG_ENABLE_36BIT_PHYS 1
  67. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
  68. #define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
  69. #define CONFIG_ENABLE_36BIT_PHYS 1
  70. #undef CONFIG_SYS_DRAM_TEST
  71. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  72. #define CONFIG_SYS_MEMTEST_END 0x00400000
  73. /*
  74. * Base addresses -- Note these are effective addresses where the
  75. * actual resources get mapped (not physical addresses)
  76. */
  77. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  78. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  79. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  80. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  81. #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
  82. /* DDR Setup */
  83. #define CONFIG_FSL_DDR2
  84. #undef CONFIG_FSL_DDR_INTERACTIVE
  85. #define CONFIG_DDR_ECC /* only for ECC DDR module */
  86. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
  87. #define CONFIG_DDR_SPD
  88. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  89. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  90. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  91. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  92. #define CONFIG_VERY_BIG_RAM
  93. #define CONFIG_NUM_DDR_CONTROLLERS 1
  94. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  95. #define CONFIG_CHIP_SELECTS_PER_CTRL 2
  96. /* I2C addresses of SPD EEPROMs */
  97. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  98. /* Manually set up DDR parameters */
  99. #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */
  100. #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
  101. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
  102. #define CONFIG_SYS_DDR_TIMING_0 0x00260802
  103. #define CONFIG_SYS_DDR_TIMING_1 0x38355322
  104. #define CONFIG_SYS_DDR_TIMING_2 0x039048c7
  105. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  106. #define CONFIG_SYS_DDR_MODE 0x00000432
  107. #define CONFIG_SYS_DDR_INTERVAL 0x05150100
  108. #define DDR_SDRAM_CFG 0x43000000
  109. #undef CONFIG_CLOCKS_IN_MHZ
  110. /*
  111. * Local Bus Definitions
  112. */
  113. /*
  114. * FLASH on the Local Bus
  115. * based on flash chip S29GL01GP
  116. * One bank, 128M, using the CFI driver.
  117. * Boot from BR0 bank at 0xf800_0000
  118. *
  119. * BR0:
  120. * Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
  121. * Port Size = 16 bits = BRx[19:20] = 10
  122. * Use GPCM = BRx[24:26] = 000
  123. * Valid = BRx[31] = 1
  124. *
  125. * 0 4 8 12 16 20 24 28
  126. * 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
  127. *
  128. * OR0:
  129. * Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
  130. * Reserved ORx[17:18] = 00
  131. * CSNT = ORx[20] = 1
  132. * ACS = half cycle delay = ORx[21:22] = 11
  133. * SCY = 6 = ORx[24:27] = 0110
  134. * TRLX = use relaxed timing = ORx[29] = 1
  135. * EAD = use external address latch delay = OR[31] = 1
  136. *
  137. * 0 4 8 12 16 20 24 28
  138. * 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
  139. */
  140. #define CONFIG_SYS_BOOT_BLOCK 0xf8000000 /* boot TLB block */
  141. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */
  142. #define CONFIG_SYS_BR0_PRELIM 0xf8001001
  143. #define CONFIG_SYS_OR0_PRELIM 0xf8000E65
  144. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  145. #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
  146. #undef CONFIG_SYS_FLASH_CHECKSUM
  147. #define CONFIG_SYS_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
  148. #define CONFIG_SYS_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
  149. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  150. #define CONFIG_FLASH_CFI_DRIVER 1
  151. #define CONFIG_SYS_FLASH_CFI 1
  152. #define CONFIG_SYS_FLASH_EMPTY_INFO
  153. /*
  154. * Flash on the LocalBus
  155. */
  156. #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
  157. /* Memory */
  158. #define CONFIG_SYS_INIT_RAM_LOCK 1
  159. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  160. #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
  161. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
  162. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  163. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  164. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  165. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  166. /* Serial Port */
  167. #define CONFIG_CONS_INDEX 1
  168. #define CONFIG_SYS_NS16550
  169. #define CONFIG_SYS_NS16550_SERIAL
  170. #define CONFIG_SYS_NS16550_REG_SIZE 1
  171. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  172. #define CONFIG_SYS_BAUDRATE_TABLE \
  173. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  174. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  175. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  176. /* Use the HUSH parser */
  177. #define CONFIG_SYS_HUSH_PARSER
  178. #ifdef CONFIG_SYS_HUSH_PARSER
  179. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  180. #endif
  181. /* pass open firmware flat tree */
  182. #define CONFIG_OF_LIBFDT 1
  183. #define CONFIG_OF_BOARD_SETUP 1
  184. /*
  185. * I2C
  186. */
  187. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  188. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  189. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  190. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  191. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  192. #define CONFIG_SYS_I2C_SLAVE 0x7F
  193. #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  194. #define CONFIG_SYS_I2C_OFFSET 0x3000
  195. /*
  196. * General PCI
  197. * Memory space is mapped 1-1, but I/O space must start from 0.
  198. */
  199. #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
  200. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  201. #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
  202. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  203. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  204. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  205. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  206. #ifdef CONFIG_PCI2
  207. #define CONFIG_SYS_PCI2_MEM_BUS 0xC0000000
  208. #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BUS
  209. #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
  210. #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
  211. #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
  212. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  213. #endif
  214. #ifdef CONFIG_PCIE1
  215. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  216. #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
  217. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  218. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  219. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
  220. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
  221. #endif
  222. #if !defined(CONFIG_PCI_PNP)
  223. #define PCI_ENET0_IOADDR 0xe0000000
  224. #define PCI_ENET0_MEMADDR 0xe0000000
  225. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  226. #endif
  227. #if defined(CONFIG_PCI)
  228. #define CONFIG_NET_MULTI
  229. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  230. #undef CONFIG_EEPRO100
  231. #undef CONFIG_TULIP
  232. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  233. #endif /* CONFIG_PCI */
  234. #if defined(CONFIG_TSEC_ENET)
  235. #ifndef CONFIG_NET_MULTI
  236. #define CONFIG_NET_MULTI 1
  237. #endif
  238. #define CONFIG_MII 1 /* MII PHY management */
  239. #define CONFIG_TSEC1 1
  240. #define CONFIG_TSEC1_NAME "eTSEC0"
  241. #define CONFIG_TSEC2 1
  242. #define CONFIG_TSEC2_NAME "eTSEC1"
  243. #define CONFIG_TSEC3 1
  244. #define CONFIG_TSEC3_NAME "eTSEC2"
  245. #define CONFIG_TSEC4 1
  246. #define CONFIG_TSEC4_NAME "eTSEC3"
  247. #undef CONFIG_MPC85XX_FEC
  248. #define TSEC1_PHY_ADDR 0
  249. #define TSEC2_PHY_ADDR 1
  250. #define TSEC3_PHY_ADDR 2
  251. #define TSEC4_PHY_ADDR 3
  252. #define TSEC1_PHYIDX 0
  253. #define TSEC2_PHYIDX 0
  254. #define TSEC3_PHYIDX 0
  255. #define TSEC4_PHYIDX 0
  256. #define TSEC1_FLAGS TSEC_GIGABIT
  257. #define TSEC2_FLAGS TSEC_GIGABIT
  258. #define TSEC3_FLAGS TSEC_GIGABIT
  259. #define TSEC4_FLAGS TSEC_GIGABIT
  260. /* Options are: eTSEC[0-3] */
  261. #define CONFIG_ETHPRIME "eTSEC2"
  262. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  263. #endif /* CONFIG_TSEC_ENET */
  264. /*
  265. * Environment
  266. */
  267. #define CONFIG_ENV_IS_IN_FLASH 1
  268. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  269. #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  270. #define CONFIG_ENV_SIZE 0x2000
  271. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  272. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  273. /*
  274. * BOOTP options
  275. */
  276. #define CONFIG_BOOTP_BOOTFILESIZE
  277. #define CONFIG_BOOTP_BOOTPATH
  278. #define CONFIG_BOOTP_GATEWAY
  279. #define CONFIG_BOOTP_HOSTNAME
  280. /*
  281. * Command line configuration.
  282. */
  283. #include <config_cmd_default.h>
  284. #define CONFIG_CMD_PING
  285. #define CONFIG_CMD_I2C
  286. #define CONFIG_CMD_MII
  287. #if defined(CONFIG_PCI)
  288. #define CONFIG_CMD_PCI
  289. #endif
  290. #undef CONFIG_WATCHDOG /* watchdog disabled */
  291. /*
  292. * Miscellaneous configurable options
  293. */
  294. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  295. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  296. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  297. #if defined(CONFIG_CMD_KGDB)
  298. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  299. #else
  300. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  301. #endif
  302. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  303. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  304. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  305. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  306. /*
  307. * For booting Linux, the board info and command line data
  308. * have to be in the first 8 MB of memory, since this is
  309. * the maximum mapped by the Linux kernel during initialization.
  310. */
  311. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
  312. #if defined(CONFIG_CMD_KGDB)
  313. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  314. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  315. #endif
  316. /*
  317. * Environment Configuration
  318. */
  319. /* The mac addresses for all ethernet interface */
  320. #if defined(CONFIG_TSEC_ENET)
  321. #define CONFIG_HAS_ETH0
  322. #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  323. #define CONFIG_HAS_ETH1
  324. #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  325. #define CONFIG_HAS_ETH2
  326. #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
  327. #define CONFIG_HAS_ETH3
  328. #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
  329. #endif
  330. #define CONFIG_IPADDR 10.101.43.142
  331. #define CONFIG_HOSTNAME atum
  332. #define CONFIG_ROOTPATH /nfsroot
  333. #define CONFIG_BOOTFILE /tftpboot/uImage.atum
  334. #define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
  335. #define CONFIG_SERVERIP 10.101.43.10
  336. #define CONFIG_GATEWAYIP 10.101.45.1
  337. #define CONFIG_NETMASK 255.255.248.0
  338. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  339. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  340. #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  341. #define CONFIG_BAUDRATE 115200
  342. #define CONFIG_NFSBOOTCOMMAND \
  343. "setenv bootargs root=/dev/nfs rw " \
  344. "nfsroot=$serverip:$rootpath " \
  345. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  346. "console=$consoledev,$baudrate $othbootargs;" \
  347. "tftp $loadaddr $bootfile;" \
  348. "tftp $dtbaddr $dtbfile;" \
  349. "bootm $loadaddr - $dtbaddr"
  350. #define CONFIG_RAMBOOTCOMMAND \
  351. "setenv bootargs root=/dev/ram rw " \
  352. "console=$consoledev,$baudrate $othbootargs;" \
  353. "tftp $ramdiskaddr $ramdiskfile;" \
  354. "tftp $loadaddr $bootfile;" \
  355. "tftp $dtbaddr $dtbfile;" \
  356. "bootm $loadaddr $ramdiskaddr $dtbaddr"
  357. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  358. #endif /* __CONFIG_H */