A3000.h 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312
  1. /*
  2. * (C) Copyright 2001, 2002, 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /* ------------------------------------------------------------------------- */
  24. /*
  25. * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
  26. * http://artismicro.com
  27. */
  28. /* ------------------------------------------------------------------------- */
  29. /*
  30. * board/config.h - configuration options, board specific
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /*
  35. * High Level Configuration Options
  36. * (easy to change)
  37. */
  38. #define CONFIG_MPC824X 1
  39. #define CONFIG_MPC8245 1
  40. #define CONFIG_A3000 1
  41. #define CONFIG_SYS_TEXT_BASE 0xFFF00000
  42. #define CONFIG_CONS_INDEX 1
  43. #define CONFIG_BAUDRATE 9600
  44. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  45. #define CONFIG_BOOTDELAY 5
  46. /*
  47. * BOOTP options
  48. */
  49. #define CONFIG_BOOTP_BOOTFILESIZE
  50. #define CONFIG_BOOTP_BOOTPATH
  51. #define CONFIG_BOOTP_GATEWAY
  52. #define CONFIG_BOOTP_HOSTNAME
  53. /*
  54. * Command line configuration.
  55. */
  56. #include <config_cmd_default.h>
  57. /*
  58. * Miscellaneous configurable options
  59. */
  60. #undef CONFIG_SYS_LONGHELP /* undef to save memory */
  61. #define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */
  62. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  63. /* Print Buffer Size
  64. */
  65. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  66. #define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
  67. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  68. #define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */
  69. /*-----------------------------------------------------------------------
  70. * PCI stuff
  71. *-----------------------------------------------------------------------
  72. */
  73. #define CONFIG_HARD_I2C 1 /* To enable I2C support */
  74. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  75. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  76. #define CONFIG_SYS_I2C_SLAVE 0x7F
  77. /*-----------------------------------------------------------------------
  78. * PCI stuff
  79. *-----------------------------------------------------------------------
  80. */
  81. #define CONFIG_PCI /* include pci support */
  82. #undef CONFIG_PCI_PNP
  83. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  84. #define CONFIG_NET_MULTI /* Multi ethernet cards support */
  85. /* #define CONFIG_TULIP */
  86. /* #define CONFIG_EEPRO100 */
  87. #define CONFIG_NATSEMI
  88. #define PCI_ENET0_IOADDR 0x80000000
  89. #define PCI_ENET0_MEMADDR 0x80000000
  90. #define PCI_ENET1_IOADDR 0x81000000
  91. #define PCI_ENET1_MEMADDR 0x81000000
  92. #define PCI_ENET2_IOADDR 0x82000000
  93. #define PCI_ENET2_MEMADDR 0x82000000
  94. #define PCI_ENET3_IOADDR 0x83000000
  95. #define PCI_ENET3_MEMADDR 0x83000000
  96. /*-----------------------------------------------------------------------
  97. * Start addresses for the final memory configuration
  98. * (Set up by the startup code)
  99. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  100. */
  101. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  102. #define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
  103. #define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
  104. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM
  105. #define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM }
  106. /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
  107. * reset vector is actually located at FFB00100, but the 8245
  108. * takes care of us.
  109. */
  110. #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
  111. #define CONFIG_SYS_EUMB_ADDR 0xFC000000
  112. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  113. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  114. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  115. #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
  116. #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
  117. /* Maximum amount of RAM.
  118. */
  119. #define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */
  120. #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
  121. #undef CONFIG_SYS_RAMBOOT
  122. #else
  123. #define CONFIG_SYS_RAMBOOT
  124. #endif
  125. /*
  126. * NS16550 Configuration
  127. */
  128. #define CONFIG_SYS_NS16550
  129. #define CONFIG_SYS_NS16550_SERIAL
  130. #define CONFIG_SYS_NS16550_REG_SIZE 1
  131. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  132. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
  133. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
  134. /*-----------------------------------------------------------------------
  135. * Definitions for initial stack pointer and data area
  136. */
  137. /* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
  138. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  139. #define CONFIG_SYS_INIT_RAM_SIZE 0x1000
  140. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  141. /*
  142. * Low Level Configuration Settings
  143. * (address mappings, register initial values, etc.)
  144. * You should know what you are doing if you make changes here.
  145. * For the detail description refer to the MPC8240 user's manual.
  146. */
  147. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  148. #define CONFIG_SYS_HZ 1000
  149. /* Bit-field values for MCCR1.
  150. */
  151. #define CONFIG_SYS_ROMNAL 7
  152. #define CONFIG_SYS_ROMFAL 11
  153. #define CONFIG_SYS_DBUS_SIZE 0x3
  154. /* Bit-field values for MCCR2.
  155. */
  156. #define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
  157. #define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
  158. /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
  159. */
  160. #define CONFIG_SYS_BSTOPRE 121
  161. /* Bit-field values for MCCR3.
  162. */
  163. #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
  164. /* Bit-field values for MCCR4.
  165. */
  166. #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
  167. #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
  168. #define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */
  169. #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
  170. #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
  171. #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
  172. #define CONFIG_SYS_EXTROM 1
  173. #define CONFIG_SYS_REGDIMM 0
  174. #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
  175. #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
  176. /* Memory bank settings.
  177. * Only bits 20-29 are actually used from these vales to set the
  178. * start/end addresses. The upper two bits will always be 0, and the lower
  179. * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
  180. * address. Refer to the MPC8240 book.
  181. */
  182. #define CONFIG_SYS_BANK0_START 0x00000000
  183. #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
  184. #define CONFIG_SYS_BANK0_ENABLE 1
  185. #define CONFIG_SYS_BANK1_START 0x3ff00000
  186. #define CONFIG_SYS_BANK1_END 0x3fffffff
  187. #define CONFIG_SYS_BANK1_ENABLE 0
  188. #define CONFIG_SYS_BANK2_START 0x3ff00000
  189. #define CONFIG_SYS_BANK2_END 0x3fffffff
  190. #define CONFIG_SYS_BANK2_ENABLE 0
  191. #define CONFIG_SYS_BANK3_START 0x3ff00000
  192. #define CONFIG_SYS_BANK3_END 0x3fffffff
  193. #define CONFIG_SYS_BANK3_ENABLE 0
  194. #define CONFIG_SYS_BANK4_START 0x3ff00000
  195. #define CONFIG_SYS_BANK4_END 0x3fffffff
  196. #define CONFIG_SYS_BANK4_ENABLE 0
  197. #define CONFIG_SYS_BANK5_START 0x3ff00000
  198. #define CONFIG_SYS_BANK5_END 0x3fffffff
  199. #define CONFIG_SYS_BANK5_ENABLE 0
  200. #define CONFIG_SYS_BANK6_START 0x3ff00000
  201. #define CONFIG_SYS_BANK6_END 0x3fffffff
  202. #define CONFIG_SYS_BANK6_ENABLE 0
  203. #define CONFIG_SYS_BANK7_START 0x3ff00000
  204. #define CONFIG_SYS_BANK7_END 0x3fffffff
  205. #define CONFIG_SYS_BANK7_ENABLE 0
  206. #define CONFIG_SYS_ODCR 0xff
  207. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  208. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  209. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
  210. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  211. #define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  212. #define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  213. #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  214. #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  215. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  216. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  217. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  218. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  219. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  220. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  221. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  222. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  223. /*
  224. * For booting Linux, the board info and command line data
  225. * have to be in the first 8 MB of memory, since this is
  226. * the maximum mapped by the Linux kernel during initialization.
  227. */
  228. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  229. /*-----------------------------------------------------------------------
  230. * FLASH organization
  231. */
  232. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
  233. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */
  234. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  235. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  236. /* Warining: environment is not EMBEDDED in the U-Boot code.
  237. * It's stored in flash separately.
  238. */
  239. #define CONFIG_ENV_IS_IN_FLASH 1
  240. #define CONFIG_ENV_ADDR 0xFFFE0000
  241. #define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */
  242. #define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */
  243. /*-----------------------------------------------------------------------
  244. * Cache Configuration
  245. */
  246. #define CONFIG_SYS_CACHELINE_SIZE 32
  247. #if defined(CONFIG_CMD_KGDB)
  248. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  249. #endif
  250. #endif /* __CONFIG_H */