early_init.S 5.6 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Thomas Koeller, tkoeller@gmx.net
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #ifndef __ASSEMBLY__
  24. #define __ASSEMBLY__ 1
  25. #endif
  26. #include <asm-offsets.h>
  27. #include <config.h>
  28. #include <asm/processor.h>
  29. #include <mpc824x.h>
  30. #include <ppc_asm.tmpl>
  31. #if defined(USE_DINK32)
  32. /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
  33. #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
  34. #else
  35. #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
  36. #endif
  37. .text
  38. /* Values to program into memory controller registers */
  39. tbl: .long MCCR1, MCCR1VAL
  40. .long MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
  41. .long MCCR3
  42. .long (((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
  43. (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
  44. (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT)
  45. .long MCCR4
  46. .long (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
  47. (CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
  48. (((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
  49. ((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
  50. (CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
  51. (CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
  52. ((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
  53. .long MSAR1
  54. .long (((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
  55. (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
  56. (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  57. (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  58. .long EMSAR1
  59. .long (((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
  60. (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
  61. (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  62. (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  63. .long MSAR2
  64. .long (((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
  65. (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
  66. (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  67. (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  68. .long EMSAR2
  69. .long (((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
  70. (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
  71. (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  72. (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  73. .long MEAR1
  74. .long (((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
  75. (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
  76. (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  77. (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  78. .long EMEAR1
  79. .long (((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
  80. (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
  81. (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  82. (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  83. .long MEAR2
  84. .long (((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 0) | \
  85. (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) | \
  86. (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
  87. (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
  88. .long EMEAR2
  89. .long (((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 0) | \
  90. (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) | \
  91. (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
  92. (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
  93. .long 0
  94. /*
  95. * Early CPU initialization. Set up memory controller, so we can access any RAM at all. This
  96. * must be done in assembly, since we have no stack at this point.
  97. */
  98. .global early_init_f
  99. early_init_f:
  100. mflr r10
  101. /* basic memory controller configuration */
  102. lis r3, CONFIG_ADDR_HIGH
  103. lis r4, CONFIG_DATA_HIGH
  104. bl lab
  105. lab: mflr r5
  106. lwzu r0, tbl - lab(r5)
  107. loop: lwz r1, 4(r5)
  108. stwbrx r0, 0, r3
  109. eieio
  110. stwbrx r1, 0, r4
  111. eieio
  112. lwzu r0, 8(r5)
  113. cmpli cr0, 0, r0, 0
  114. bne cr0, loop
  115. /* set bank enable bits */
  116. lis r0, MBER@h
  117. ori r0, 0, MBER@l
  118. li r1, CONFIG_SYS_BANK_ENABLE
  119. stwbrx r0, 0, r3
  120. eieio
  121. stb r1, 0(r4)
  122. eieio
  123. /* delay loop */
  124. lis r0, 0x0003
  125. mtctr r0
  126. delay: bdnz delay
  127. /* enable memory controller */
  128. lis r0, MCCR1@h
  129. ori r0, 0, MCCR1@l
  130. stwbrx r0, 0, r3
  131. eieio
  132. lwbrx r0, 0, r4
  133. oris r0, 0, MCCR1_MEMGO@h
  134. stwbrx r0, 0, r4
  135. eieio
  136. /* set up stack pointer */
  137. lis r1, CONFIG_SYS_INIT_SP_OFFSET@h
  138. ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
  139. mtlr r10
  140. blr