fads.h 18 KB

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  1. /*
  2. * (C) Copyright 2000-2004
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Derived from FADS860T definitions by Magnus Damm, Helmut Buchsbaum,
  6. * and Dan Malek
  7. *
  8. * Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
  9. *
  10. * This header file contains values common to all FADS family boards.
  11. *
  12. * See file CREDITS for list of people who contributed to this
  13. * project.
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation; either version 2 of
  18. * the License, or (at your option) any later version.
  19. *
  20. * This program is distributed in the hope that it will be useful,
  21. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23. * GNU General Public License for more details.
  24. *
  25. * You should have received a copy of the GNU General Public License
  26. * along with this program; if not, write to the Free Software
  27. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  28. * MA 02111-1307 USA
  29. */
  30. /****************************************************************************
  31. * Flash Memory Map as used by U-Boot:
  32. *
  33. * Start Address Length
  34. * +-----------------------+ 0xFE00_0000 Start of Flash -----------------
  35. * | | 0xFE00_0100 Reset Vector
  36. * + + 0xFE0?_????
  37. * | U-Boot code |
  38. * | |
  39. * +-----------------------+ 0xFE04_0000 (sector border)
  40. * | |
  41. * | |
  42. * | U-Boot environment |
  43. * | | ^
  44. * | | | U-Boot
  45. * +=======================+ 0xFE08_0000 (sector border) -----------------
  46. * | Available | | Applications
  47. * | ... | v
  48. *
  49. *****************************************************************************/
  50. #if 0
  51. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  52. #else
  53. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  54. #endif
  55. #define CONFIG_ENV_OVERWRITE
  56. #define CONFIG_NFSBOOTCOMMAND \
  57. "dhcp;" \
  58. "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
  59. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
  60. "bootm"
  61. #define CONFIG_BOOTCOMMAND \
  62. "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
  63. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
  64. "bootm fe080000"
  65. #undef CONFIG_BOOTARGS
  66. #undef CONFIG_WATCHDOG /* watchdog disabled */
  67. #if !defined(CONFIG_MPC885ADS)
  68. #define CONFIG_BZIP2 /* include support for bzip2 compressed images */
  69. #endif
  70. /*
  71. * New MPC86xADS and MPC885ADS provide two Ethernet connectivity options:
  72. * 10Mbit/s on SCC and 100Mbit/s on FEC. FADS provides SCC Ethernet on
  73. * motherboard and FEC Ethernet on daughterboard. All new PQ1 chips have
  74. * got FEC so FEC is the default.
  75. */
  76. #ifndef CONFIG_ADS
  77. #undef CONFIG_SCC1_ENET /* Disable SCC1 ethernet */
  78. #define CONFIG_FEC_ENET /* Use FEC ethernet */
  79. #else /* Old ADS has not got FEC option */
  80. #define CONFIG_SCC1_ENET /* Use SCC1 ethernet */
  81. #undef CONFIG_FEC_ENET /* No FEC ethernet */
  82. #endif /* !CONFIG_ADS */
  83. #if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
  84. #error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
  85. #endif
  86. #ifdef CONFIG_FEC_ENET
  87. #define CONFIG_SYS_DISCOVER_PHY
  88. #define CONFIG_MII_INIT 1
  89. #endif
  90. /*
  91. * BOOTP options
  92. */
  93. #define CONFIG_BOOTP_BOOTFILESIZE
  94. #define CONFIG_BOOTP_BOOTPATH
  95. #define CONFIG_BOOTP_GATEWAY
  96. #define CONFIG_BOOTP_HOSTNAME
  97. #if !defined(FADS_COMMANDS_ALREADY_DEFINED)
  98. /*
  99. * Command line configuration.
  100. */
  101. #include <config_cmd_default.h>
  102. #define CONFIG_CMD_ASKENV
  103. #define CONFIG_CMD_DHCP
  104. #define CONFIG_CMD_ECHO
  105. #define CONFIG_CMD_IMMAP
  106. #define CONFIG_CMD_JFFS2
  107. #define CONFIG_CMD_MII
  108. #define CONFIG_CMD_PCMCIA
  109. #define CONFIG_CMD_PING
  110. #endif
  111. /*
  112. * Miscellaneous configurable options
  113. */
  114. #define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
  115. #define CONFIG_SYS_HUSH_PARSER
  116. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  117. #define CONFIG_SYS_LONGHELP /* #undef to save memory */
  118. #if defined(CONFIG_CMD_KGDB)
  119. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  120. #else
  121. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  122. #endif
  123. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
  124. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  125. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  126. #define CONFIG_SYS_LOAD_ADDR 0x00100000
  127. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  128. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  129. /*
  130. * Low Level Configuration Settings
  131. * (address mappings, register initial values, etc.)
  132. * You should know what you are doing if you make changes here.
  133. */
  134. /*-----------------------------------------------------------------------
  135. * Internal Memory Mapped Register
  136. */
  137. #define CONFIG_SYS_IMMR 0xFF000000
  138. /*-----------------------------------------------------------------------
  139. * Definitions for initial stack pointer and data area (in DPRAM)
  140. */
  141. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  142. #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
  143. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  144. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  145. /*-----------------------------------------------------------------------
  146. * Start addresses for the final memory configuration
  147. * (Set up by the startup code)
  148. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  149. */
  150. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  151. #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
  152. #define CONFIG_SYS_SDRAM_SIZE 0x00800000 /* 8 Mbyte */
  153. /*
  154. * 2048 SDRAM rows
  155. * 1000 factor s -> ms
  156. * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
  157. * 4 Number of refresh cycles per period
  158. * 64 Refresh cycle in ms per number of rows
  159. */
  160. #define CONFIG_SYS_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
  161. #elif defined(CONFIG_FADS) /* Old/new FADS */
  162. #define CONFIG_SYS_SDRAM_SIZE 0x00400000 /* 4 Mbyte */
  163. #else /* Old ADS */
  164. #define CONFIG_SYS_SDRAM_SIZE 0x00000000 /* No SDRAM */
  165. #endif
  166. #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */
  167. #if (CONFIG_SYS_SDRAM_SIZE)
  168. #define CONFIG_SYS_MEMTEST_END CONFIG_SYS_SDRAM_SIZE /* 1 ... SDRAM_SIZE */
  169. #else
  170. #define CONFIG_SYS_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */
  171. #endif /* CONFIG_SYS_SDRAM_SIZE */
  172. /*
  173. * For booting Linux, the board info and command line data
  174. * have to be in the first 8 MB of memory, since this is
  175. * the maximum mapped by the Linux kernel during initialization.
  176. */
  177. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  178. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  179. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
  180. #ifdef CONFIG_BZIP2
  181. #define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
  182. #else
  183. #define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
  184. #endif /* CONFIG_BZIP2 */
  185. /*-----------------------------------------------------------------------
  186. * Flash organization
  187. */
  188. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
  189. #define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
  190. #define CONFIG_SYS_MAX_FLASH_BANKS 4 /* max number of memory banks */
  191. #define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
  192. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  193. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  194. #define CONFIG_ENV_IS_IN_FLASH 1
  195. #define CONFIG_ENV_SECT_SIZE 0x40000 /* see README - env sector total size */
  196. #define CONFIG_ENV_OFFSET CONFIG_ENV_SECT_SIZE
  197. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
  198. #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
  199. #define CONFIG_SYS_DIRECT_FLASH_TFTP
  200. #if defined(CONFIG_CMD_JFFS2)
  201. /*
  202. * JFFS2 partitions
  203. *
  204. */
  205. /* No command line, one static partition, whole device */
  206. #undef CONFIG_CMD_MTDPARTS
  207. #define CONFIG_JFFS2_DEV "nor0"
  208. #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
  209. #define CONFIG_JFFS2_PART_OFFSET 0x00000000
  210. /* mtdparts command line support */
  211. /* Note: fake mtd_id used, no linux mtd map file */
  212. /*
  213. #define CONFIG_CMD_MTDPARTS
  214. #define MTDIDS_DEFAULT "nor0=fads0,nor1=fads-1,nor2=fads-2,nor3=fads-3"
  215. #define MTDPARTS_DEFAULT "mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
  216. */
  217. #define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
  218. #endif
  219. /*-----------------------------------------------------------------------
  220. * Cache Configuration
  221. */
  222. #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  223. #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  224. /*-----------------------------------------------------------------------
  225. * I2C configuration
  226. */
  227. #if defined(CONFIG_CMD_I2C)
  228. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  229. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address defaults */
  230. #define CONFIG_SYS_I2C_SLAVE 0x7F
  231. #endif
  232. /*-----------------------------------------------------------------------
  233. * SYPCR - System Protection Control 11-9
  234. * SYPCR can only be written once after reset!
  235. *-----------------------------------------------------------------------
  236. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  237. */
  238. #if defined(CONFIG_WATCHDOG)
  239. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  240. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  241. #else
  242. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  243. #endif
  244. /*-----------------------------------------------------------------------
  245. * SIUMCR - SIU Module Configuration 11-6
  246. *-----------------------------------------------------------------------
  247. * PCMCIA config., multi-function pin tri-state
  248. */
  249. #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
  250. /*-----------------------------------------------------------------------
  251. * TBSCR - Time Base Status and Control 11-26
  252. *-----------------------------------------------------------------------
  253. * Clear Reference Interrupt Status, Timebase freezing enabled
  254. */
  255. #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
  256. /*-----------------------------------------------------------------------
  257. * PISCR - Periodic Interrupt Status and Control 11-31
  258. *-----------------------------------------------------------------------
  259. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  260. */
  261. #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
  262. /*-----------------------------------------------------------------------
  263. * SCCR - System Clock and reset Control Register 15-27
  264. *-----------------------------------------------------------------------
  265. * Set clock output, timebase and RTC source and divider,
  266. * power management and some other internal clocks
  267. */
  268. #define SCCR_MASK SCCR_EBDF11
  269. #define CONFIG_SYS_SCCR SCCR_TBS
  270. /*-----------------------------------------------------------------------
  271. * DER - Debug Enable Register
  272. *-----------------------------------------------------------------------
  273. * Set to zero to prevent the processor from entering debug mode
  274. */
  275. #define CONFIG_SYS_DER 0
  276. /* Because of the way the 860 starts up and assigns CS0 the entire
  277. * address space, we have to set the memory controller differently.
  278. * Normally, you write the option register first, and then enable the
  279. * chip select by writing the base register. For CS0, you must write
  280. * the base register first, followed by the option register.
  281. */
  282. /*
  283. * Init Memory Controller:
  284. *
  285. * BR0/OR0 (Flash)
  286. * BR1/OR1 (BCSR)
  287. */
  288. /* the other CS:s are determined by looking at parameters in BCSRx */
  289. #define BCSR_ADDR ((uint) 0xFF080000)
  290. #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
  291. /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
  292. #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
  293. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 8 Mbyte until detected */
  294. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
  295. /* BCSRx - Board Control and Status Registers */
  296. #define CONFIG_SYS_OR1_PRELIM 0xFFFF8110 /* 64Kbyte address space */
  297. #define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V)
  298. /* values according to the manual */
  299. #define BCSR0 ((uint) (BCSR_ADDR + 0x00))
  300. #define BCSR1 ((uint) (BCSR_ADDR + 0x04))
  301. #define BCSR2 ((uint) (BCSR_ADDR + 0x08))
  302. #define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
  303. #define BCSR4 ((uint) (BCSR_ADDR + 0x10))
  304. /*
  305. * (F)ADS bitvalues by Helmut Buchsbaum
  306. *
  307. * See User's Manual for a proper
  308. * description of the following structures
  309. */
  310. #define BCSR0_ERB ((uint)0x80000000)
  311. #define BCSR0_IP ((uint)0x40000000)
  312. #define BCSR0_BDIS ((uint)0x10000000)
  313. #define BCSR0_BPS_MASK ((uint)0x0C000000)
  314. #define BCSR0_ISB_MASK ((uint)0x01800000)
  315. #define BCSR0_DBGC_MASK ((uint)0x00600000)
  316. #define BCSR0_DBPC_MASK ((uint)0x00180000)
  317. #define BCSR0_EBDF_MASK ((uint)0x00060000)
  318. #define BCSR1_FLASH_EN ((uint)0x80000000)
  319. #define BCSR1_DRAM_EN ((uint)0x40000000)
  320. #define BCSR1_ETHEN ((uint)0x20000000)
  321. #define BCSR1_IRDEN ((uint)0x10000000)
  322. #define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
  323. #define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
  324. #define BCSR1_BCSR_EN ((uint)0x02000000)
  325. #define BCSR1_RS232EN_1 ((uint)0x01000000)
  326. #define BCSR1_PCCEN ((uint)0x00800000)
  327. #define BCSR1_PCCVCC0 ((uint)0x00400000)
  328. #define BCSR1_PCCVPP_MASK ((uint)0x00300000)
  329. #define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
  330. #define BCSR1_RS232EN_2 ((uint)0x00040000)
  331. #define BCSR1_SDRAM_EN ((uint)0x00020000)
  332. #define BCSR1_PCCVCC1 ((uint)0x00010000)
  333. #define BCSR1_PCCVCCON BCSR1_PCCVCC0
  334. #define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
  335. #define BCSR2_FLASH_PD_SHIFT 28
  336. #define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
  337. #define BCSR2_DRAM_PD_SHIFT 23
  338. #define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
  339. #define BCSR2_DBREVNR_MASK ((uint)0x00030000)
  340. #define BCSR3_DBID_MASK ((ushort)0x3800)
  341. #define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
  342. #define BCSR3_BREVNR0 ((ushort)0x0080)
  343. #define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
  344. #define BCSR3_BREVN1 ((ushort)0x0008)
  345. #define BCSR3_BREVN2_MASK ((ushort)0x0003)
  346. #define BCSR4_ETHLOOP ((uint)0x80000000)
  347. #define BCSR4_TFPLDL ((uint)0x40000000)
  348. #define BCSR4_TPSQEL ((uint)0x20000000)
  349. #define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
  350. #if defined(CONFIG_MPC823)
  351. #define BCSR4_USB_EN ((uint)0x08000000)
  352. #define BCSR4_USB_SPEED ((uint)0x04000000)
  353. #define BCSR4_VCCO ((uint)0x02000000)
  354. #define BCSR4_VIDEO_ON ((uint)0x00800000)
  355. #define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
  356. #define BCSR4_VIDEO_RST ((uint)0x00200000)
  357. #define BCSR4_MODEM_EN ((uint)0x00100000)
  358. #define BCSR4_DATA_VOICE ((uint)0x00080000)
  359. #elif defined(CONFIG_MPC850)
  360. #define BCSR4_DATA_VOICE ((uint)0x00080000)
  361. #elif defined(CONFIG_MPC860SAR)
  362. #define BCSR4_UTOPIA_EN ((uint)0x08000000)
  363. #else /* MPC860T and other chips with FEC */
  364. #define BCSR4_FETH_EN ((uint)0x08000000)
  365. #define BCSR4_FETHCFG0 ((uint)0x04000000)
  366. #define BCSR4_FETHFDE ((uint)0x02000000)
  367. #define BCSR4_FETHCFG1 ((uint)0x00400000)
  368. #define BCSR4_FETHRST ((uint)0x00200000)
  369. #endif
  370. /* BSCR5 exists on MPC86xADS and MPC885ADS only */
  371. #define CONFIG_SYS_PHYDEV_ADDR (BCSR_ADDR + 0x20000)
  372. #define BCSR5 (CONFIG_SYS_PHYDEV_ADDR + 0x300)
  373. #define BCSR5_MII2_EN 0x40
  374. #define BCSR5_MII2_RST 0x20
  375. #define BCSR5_T1_RST 0x10
  376. #define BCSR5_ATM155_RST 0x08
  377. #define BCSR5_ATM25_RST 0x04
  378. #define BCSR5_MII1_EN 0x02
  379. #define BCSR5_MII1_RST 0x01
  380. /* We don't use the 8259.
  381. */
  382. #define NR_8259_INTS 0
  383. /*-----------------------------------------------------------------------
  384. * PCMCIA stuff
  385. *-----------------------------------------------------------------------
  386. */
  387. #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
  388. #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
  389. #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
  390. #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
  391. #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
  392. #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  393. #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
  394. #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
  395. /*-----------------------------------------------------------------------
  396. * IDE/ATA stuff
  397. *-----------------------------------------------------------------------
  398. */
  399. #define CONFIG_MAC_PARTITION 1
  400. #define CONFIG_DOS_PARTITION 1
  401. #define CONFIG_ISO_PARTITION 1
  402. #undef CONFIG_ATAPI
  403. #if 0 /* does not make sense when CONFIG_CMD_IDE is not enabled, too */
  404. #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  405. #endif
  406. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  407. #undef CONFIG_IDE_LED /* LED for ide not supported */
  408. #undef CONFIG_IDE_RESET /* reset for ide not supported */
  409. #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
  410. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
  411. #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
  412. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  413. /* Offset for data I/O */
  414. #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  415. /* Offset for normal register accesses */
  416. #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
  417. /* Offset for alternate registers */
  418. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
  419. #define CONFIG_DISK_SPINUP_TIME 1000000
  420. /* #undef CONFIG_DISK_SPINUP_TIME */ /* usin Compact Flash */