init.S 3.7 KB

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  1. /*
  2. *
  3. * See file CREDITS for list of people who contributed to this
  4. * project.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of
  9. * the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19. * MA 02111-1307 USA
  20. */
  21. #include <asm-offsets.h>
  22. #include <ppc_asm.tmpl>
  23. #include <asm/mmu.h>
  24. #include <config.h>
  25. /*
  26. * TLB TABLE
  27. *
  28. * This table is used by the cpu boot code to setup the initial tlb
  29. * entries. Rather than make broad assumptions in the cpu source tree,
  30. * this table lets each board set things up however they like.
  31. *
  32. * Pointer to the table is returned in r1
  33. *
  34. */
  35. .section .bootpg,"ax"
  36. .globl tlbtab
  37. tlbtab:
  38. tlbtab_start
  39. /*
  40. * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  41. * speed up boot process. It is patched after relocation to enable SA_I
  42. */
  43. #ifndef CONFIG_NAND_SPL
  44. tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
  45. #else
  46. tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_RWX | SA_G )
  47. #endif
  48. /* TLB entries for DDR2 SDRAM are generated dynamically */
  49. #ifdef CONFIG_SYS_INIT_RAM_DCACHE
  50. /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  51. tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
  52. #endif
  53. /* TLB-entry for PCI Memory */
  54. tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
  55. tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
  56. tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
  57. tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
  58. /* TLB-entries for EBC */
  59. /* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
  60. * tlb entry.
  61. * This dummy entry is only for convinience in order not to modify the
  62. * amount of entries. Currently OS/9 relies on this :-)
  63. */
  64. tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_RWX | SA_IG )
  65. /* TLB-entry for NAND */
  66. tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_RWX | SA_IG )
  67. /* TLB-entry for Internal Registers & OCM */
  68. tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
  69. /*TLB-entry PCI registers*/
  70. tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
  71. /* TLB-entry for peripherals */
  72. tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
  73. /* TLB-entry PCI IO space */
  74. tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_RWX | SA_IG)
  75. /* TODO: what about high IO space */
  76. tlbtab_end
  77. #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  78. /*
  79. * For NAND booting the first TLB has to be reconfigured to full size
  80. * and with caching disabled after running from RAM!
  81. */
  82. #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
  83. #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
  84. #define TLB02 TLB2(AC_RWX | SA_IG)
  85. .globl reconfig_tlb0
  86. reconfig_tlb0:
  87. sync
  88. isync
  89. addi r4,r0,0x0000 /* TLB entry #0 */
  90. lis r5,TLB00@h
  91. ori r5,r5,TLB00@l
  92. tlbwe r5,r4,0x0000 /* Save it out */
  93. lis r5,TLB01@h
  94. ori r5,r5,TLB01@l
  95. tlbwe r5,r4,0x0001 /* Save it out */
  96. lis r5,TLB02@h
  97. ori r5,r5,TLB02@l
  98. tlbwe r5,r4,0x0002 /* Save it out */
  99. sync
  100. isync
  101. blr
  102. #endif