init.S 3.5 KB

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  1. /*
  2. * (C) Copyright 2007
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. #include <asm-offsets.h>
  26. #include <ppc_asm.tmpl>
  27. #include <config.h>
  28. #include <asm/mmu.h>
  29. /**************************************************************************
  30. * TLB TABLE
  31. *
  32. * This table is used by the cpu boot code to setup the initial tlb
  33. * entries. Rather than make broad assumptions in the cpu source tree,
  34. * this table lets each board set things up however they like.
  35. *
  36. * Pointer to the table is returned in r1
  37. *
  38. *************************************************************************/
  39. .section .bootpg,"ax"
  40. .globl tlbtab
  41. tlbtab:
  42. tlbtab_start
  43. /*
  44. * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
  45. * speed up boot process. It is patched after relocation to enable SA_I
  46. */
  47. #ifndef CONFIG_NAND_SPL
  48. tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_RWX | SA_G)
  49. #else
  50. tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_RWX | SA_G)
  51. tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
  52. #endif
  53. /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
  54. tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G)
  55. /* PCI base & peripherals */
  56. tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_RW | SA_IG)
  57. tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_RWX | SA_W|SA_I)
  58. tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_RWX | SA_W|SA_I)
  59. /* PCI */
  60. tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_RW | SA_IG)
  61. tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_RW | SA_IG)
  62. tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_RW | SA_IG)
  63. tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_RW | SA_IG)
  64. /* USB 2.0 Device */
  65. tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_RW | SA_IG)
  66. tlbtab_end
  67. #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  68. /*
  69. * For NAND booting the first TLB has to be reconfigured to full size
  70. * and with caching disabled after running from RAM!
  71. */
  72. #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
  73. #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
  74. #define TLB02 TLB2(AC_RWX | SA_IG)
  75. .globl reconfig_tlb0
  76. reconfig_tlb0:
  77. sync
  78. isync
  79. addi r4,r0,0x0000 /* TLB entry #0 */
  80. lis r5,TLB00@h
  81. ori r5,r5,TLB00@l
  82. tlbwe r5,r4,0x0000 /* Save it out */
  83. lis r5,TLB01@h
  84. ori r5,r5,TLB01@l
  85. tlbwe r5,r4,0x0001 /* Save it out */
  86. lis r5,TLB02@h
  87. ori r5,r5,TLB02@l
  88. tlbwe r5,r4,0x0002 /* Save it out */
  89. sync
  90. isync
  91. blr
  92. #endif