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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
  5. * Copyright Freescale Semiconductor, Inc. 2004, 2006, 2008.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
  27. */
  28. #include <asm-offsets.h>
  29. #include <config.h>
  30. #include <mpc83xx.h>
  31. #include <timestamp.h>
  32. #include <version.h>
  33. #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
  34. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  35. #include <ppc_asm.tmpl>
  36. #include <ppc_defs.h>
  37. #include <asm/cache.h>
  38. #include <asm/mmu.h>
  39. #include <asm/u-boot.h>
  40. #ifndef CONFIG_IDENT_STRING
  41. #define CONFIG_IDENT_STRING "MPC83XX"
  42. #endif
  43. /* We don't want the MMU yet.
  44. */
  45. #undef MSR_KERNEL
  46. /*
  47. * Floating Point enable, Machine Check and Recoverable Interr.
  48. */
  49. #ifdef DEBUG
  50. #define MSR_KERNEL (MSR_FP|MSR_RI)
  51. #else
  52. #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  53. #endif
  54. #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SYS_RAMBOOT)
  55. #define CONFIG_SYS_FLASHBOOT
  56. #endif
  57. /*
  58. * Set up GOT: Global Offset Table
  59. *
  60. * Use r12 to access the GOT
  61. */
  62. START_GOT
  63. GOT_ENTRY(_GOT2_TABLE_)
  64. GOT_ENTRY(__bss_start)
  65. GOT_ENTRY(_end)
  66. #ifndef CONFIG_NAND_SPL
  67. GOT_ENTRY(_FIXUP_TABLE_)
  68. GOT_ENTRY(_start)
  69. GOT_ENTRY(_start_of_vectors)
  70. GOT_ENTRY(_end_of_vectors)
  71. GOT_ENTRY(transfer_to_handler)
  72. #endif
  73. END_GOT
  74. /*
  75. * The Hard Reset Configuration Word (HRCW) table is in the first 64
  76. * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
  77. * times so the processor can fetch it out of flash whether the flash
  78. * is 8, 16, 32, or 64 bits wide (hardware trickery).
  79. */
  80. .text
  81. #define _HRCW_TABLE_ENTRY(w) \
  82. .fill 8,1,(((w)>>24)&0xff); \
  83. .fill 8,1,(((w)>>16)&0xff); \
  84. .fill 8,1,(((w)>> 8)&0xff); \
  85. .fill 8,1,(((w) )&0xff)
  86. _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_LOW)
  87. _HRCW_TABLE_ENTRY(CONFIG_SYS_HRCW_HIGH)
  88. /*
  89. * Magic number and version string - put it after the HRCW since it
  90. * cannot be first in flash like it is in many other processors.
  91. */
  92. .long 0x27051956 /* U-Boot Magic Number */
  93. .globl version_string
  94. version_string:
  95. .ascii U_BOOT_VERSION
  96. .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  97. .ascii " ", CONFIG_IDENT_STRING, "\0"
  98. .align 2
  99. .globl enable_addr_trans
  100. enable_addr_trans:
  101. /* enable address translation */
  102. mfmsr r5
  103. ori r5, r5, (MSR_IR | MSR_DR)
  104. mtmsr r5
  105. isync
  106. blr
  107. .globl disable_addr_trans
  108. disable_addr_trans:
  109. /* disable address translation */
  110. mflr r4
  111. mfmsr r3
  112. andi. r0, r3, (MSR_IR | MSR_DR)
  113. beqlr
  114. andc r3, r3, r0
  115. mtspr SRR0, r4
  116. mtspr SRR1, r3
  117. rfi
  118. .globl get_pvr
  119. get_pvr:
  120. mfspr r3, PVR
  121. blr
  122. .globl ppcDWstore
  123. ppcDWstore:
  124. lfd 1, 0(r4)
  125. stfd 1, 0(r3)
  126. blr
  127. .globl ppcDWload
  128. ppcDWload:
  129. lfd 1, 0(r3)
  130. stfd 1, 0(r4)
  131. blr
  132. #ifndef CONFIG_DEFAULT_IMMR
  133. #error CONFIG_DEFAULT_IMMR must be defined
  134. #endif /* CONFIG_SYS_DEFAULT_IMMR */
  135. #ifndef CONFIG_SYS_IMMR
  136. #define CONFIG_SYS_IMMR CONFIG_DEFAULT_IMMR
  137. #endif /* CONFIG_SYS_IMMR */
  138. /*
  139. * After configuration, a system reset exception is executed using the
  140. * vector at offset 0x100 relative to the base set by MSR[IP]. If
  141. * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
  142. * base address is 0xfff00000. In the case of a Power On Reset or Hard
  143. * Reset, the value of MSR[IP] is determined by the CIP field in the
  144. * HRCW.
  145. *
  146. * Other bits in the HRCW set up the Base Address and Port Size in BR0.
  147. * This determines the location of the boot ROM (flash or EPROM) in the
  148. * processor's address space at boot time. As long as the HRCW is set up
  149. * so that we eventually end up executing the code below when the
  150. * processor executes the reset exception, the actual values used should
  151. * not matter.
  152. *
  153. * Once we have got here, the address mask in OR0 is cleared so that the
  154. * bottom 32K of the boot ROM is effectively repeated all throughout the
  155. * processor's address space, after which we can jump to the absolute
  156. * address at which the boot ROM was linked at compile time, and proceed
  157. * to initialise the memory controller without worrying if the rug will
  158. * be pulled out from under us, so to speak (it will be fine as long as
  159. * we configure BR0 with the same boot ROM link address).
  160. */
  161. . = EXC_OFF_SYS_RESET
  162. .globl _start
  163. _start: /* time t 0 */
  164. lis r4, CONFIG_DEFAULT_IMMR@h
  165. nop
  166. mfmsr r5 /* save msr contents */
  167. /* 83xx manuals prescribe a specific sequence for updating IMMRBAR. */
  168. bl 1f
  169. 1: mflr r7
  170. lis r3, CONFIG_SYS_IMMR@h
  171. ori r3, r3, CONFIG_SYS_IMMR@l
  172. lwz r6, IMMRBAR(r4)
  173. isync
  174. stw r3, IMMRBAR(r4)
  175. lwz r6, 0(r7) /* Arbitrary external load */
  176. isync
  177. lwz r6, IMMRBAR(r3)
  178. isync
  179. /* Initialise the E300 processor core */
  180. /*------------------------------------------*/
  181. #ifdef CONFIG_NAND_SPL
  182. /* The FCM begins execution after only the first page
  183. * is loaded. Wait for the rest before branching
  184. * to another flash page.
  185. */
  186. 1: lwz r6, 0x50b0(r3)
  187. andi. r6, r6, 1
  188. beq 1b
  189. #endif
  190. bl init_e300_core
  191. #ifdef CONFIG_SYS_FLASHBOOT
  192. /* Inflate flash location so it appears everywhere, calculate */
  193. /* the absolute address in final location of the FLASH, jump */
  194. /* there and deflate the flash size back to minimal size */
  195. /*------------------------------------------------------------*/
  196. bl map_flash_by_law1
  197. lis r4, (CONFIG_SYS_MONITOR_BASE)@h
  198. ori r4, r4, (CONFIG_SYS_MONITOR_BASE)@l
  199. addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
  200. mtlr r5
  201. blr
  202. in_flash:
  203. #if 1 /* Remapping flash with LAW0. */
  204. bl remap_flash_by_law0
  205. #endif
  206. #endif /* CONFIG_SYS_FLASHBOOT */
  207. /* setup the bats */
  208. bl setup_bats
  209. sync
  210. /*
  211. * Cache must be enabled here for stack-in-cache trick.
  212. * This means we need to enable the BATS.
  213. * This means:
  214. * 1) for the EVB, original gt regs need to be mapped
  215. * 2) need to have an IBAT for the 0xf region,
  216. * we are running there!
  217. * Cache should be turned on after BATs, since by default
  218. * everything is write-through.
  219. * The init-mem BAT can be reused after reloc. The old
  220. * gt-regs BAT can be reused after board_init_f calls
  221. * board_early_init_f (EVB only).
  222. */
  223. /* enable address translation */
  224. bl enable_addr_trans
  225. sync
  226. /* enable the data cache */
  227. bl dcache_enable
  228. sync
  229. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  230. bl lock_ram_in_cache
  231. sync
  232. #endif
  233. /* set up the stack pointer in our newly created
  234. * cache-ram (r1) */
  235. lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
  236. ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
  237. li r0, 0 /* Make room for stack frame header and */
  238. stwu r0, -4(r1) /* clear final stack frame so that */
  239. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  240. /* let the C-code set up the rest */
  241. /* */
  242. /* Be careful to keep code relocatable & stack humble */
  243. /*------------------------------------------------------*/
  244. GET_GOT /* initialize GOT access */
  245. /* r3: IMMR */
  246. lis r3, CONFIG_SYS_IMMR@h
  247. /* run low-level CPU init code (in Flash)*/
  248. bl cpu_init_f
  249. /* run 1st part of board init code (in Flash)*/
  250. bl board_init_f
  251. /* NOTREACHED - board_init_f() does not return */
  252. #ifndef CONFIG_NAND_SPL
  253. /*
  254. * Vector Table
  255. */
  256. .globl _start_of_vectors
  257. _start_of_vectors:
  258. /* Machine check */
  259. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  260. /* Data Storage exception. */
  261. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  262. /* Instruction Storage exception. */
  263. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  264. /* External Interrupt exception. */
  265. #ifndef FIXME
  266. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  267. #endif
  268. /* Alignment exception. */
  269. . = 0x600
  270. Alignment:
  271. EXCEPTION_PROLOG(SRR0, SRR1)
  272. mfspr r4,DAR
  273. stw r4,_DAR(r21)
  274. mfspr r5,DSISR
  275. stw r5,_DSISR(r21)
  276. addi r3,r1,STACK_FRAME_OVERHEAD
  277. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  278. /* Program check exception */
  279. . = 0x700
  280. ProgramCheck:
  281. EXCEPTION_PROLOG(SRR0, SRR1)
  282. addi r3,r1,STACK_FRAME_OVERHEAD
  283. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  284. MSR_KERNEL, COPY_EE)
  285. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  286. /* I guess we could implement decrementer, and may have
  287. * to someday for timekeeping.
  288. */
  289. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  290. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  291. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  292. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  293. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  294. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  295. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  296. STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
  297. STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
  298. STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
  299. #ifdef DEBUG
  300. . = 0x1300
  301. /*
  302. * This exception occurs when the program counter matches the
  303. * Instruction Address Breakpoint Register (IABR).
  304. *
  305. * I want the cpu to halt if this occurs so I can hunt around
  306. * with the debugger and look at things.
  307. *
  308. * When DEBUG is defined, both machine check enable (in the MSR)
  309. * and checkstop reset enable (in the reset mode register) are
  310. * turned off and so a checkstop condition will result in the cpu
  311. * halting.
  312. *
  313. * I force the cpu into a checkstop condition by putting an illegal
  314. * instruction here (at least this is the theory).
  315. *
  316. * well - that didnt work, so just do an infinite loop!
  317. */
  318. 1: b 1b
  319. #else
  320. STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
  321. #endif
  322. STD_EXCEPTION(0x1400, SMI, UnknownException)
  323. STD_EXCEPTION(0x1500, Trap_15, UnknownException)
  324. STD_EXCEPTION(0x1600, Trap_16, UnknownException)
  325. STD_EXCEPTION(0x1700, Trap_17, UnknownException)
  326. STD_EXCEPTION(0x1800, Trap_18, UnknownException)
  327. STD_EXCEPTION(0x1900, Trap_19, UnknownException)
  328. STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
  329. STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
  330. STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
  331. STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
  332. STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
  333. STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
  334. STD_EXCEPTION(0x2000, Trap_20, UnknownException)
  335. STD_EXCEPTION(0x2100, Trap_21, UnknownException)
  336. STD_EXCEPTION(0x2200, Trap_22, UnknownException)
  337. STD_EXCEPTION(0x2300, Trap_23, UnknownException)
  338. STD_EXCEPTION(0x2400, Trap_24, UnknownException)
  339. STD_EXCEPTION(0x2500, Trap_25, UnknownException)
  340. STD_EXCEPTION(0x2600, Trap_26, UnknownException)
  341. STD_EXCEPTION(0x2700, Trap_27, UnknownException)
  342. STD_EXCEPTION(0x2800, Trap_28, UnknownException)
  343. STD_EXCEPTION(0x2900, Trap_29, UnknownException)
  344. STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
  345. STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
  346. STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
  347. STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
  348. STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
  349. STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
  350. .globl _end_of_vectors
  351. _end_of_vectors:
  352. . = 0x3000
  353. /*
  354. * This code finishes saving the registers to the exception frame
  355. * and jumps to the appropriate handler for the exception.
  356. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  357. */
  358. .globl transfer_to_handler
  359. transfer_to_handler:
  360. stw r22,_NIP(r21)
  361. lis r22,MSR_POW@h
  362. andc r23,r23,r22
  363. stw r23,_MSR(r21)
  364. SAVE_GPR(7, r21)
  365. SAVE_4GPRS(8, r21)
  366. SAVE_8GPRS(12, r21)
  367. SAVE_8GPRS(24, r21)
  368. mflr r23
  369. andi. r24,r23,0x3f00 /* get vector offset */
  370. stw r24,TRAP(r21)
  371. li r22,0
  372. stw r22,RESULT(r21)
  373. lwz r24,0(r23) /* virtual address of handler */
  374. lwz r23,4(r23) /* where to go when done */
  375. mtspr SRR0,r24
  376. mtspr SRR1,r20
  377. mtlr r23
  378. SYNC
  379. rfi /* jump to handler, enable MMU */
  380. int_return:
  381. mfmsr r28 /* Disable interrupts */
  382. li r4,0
  383. ori r4,r4,MSR_EE
  384. andc r28,r28,r4
  385. SYNC /* Some chip revs need this... */
  386. mtmsr r28
  387. SYNC
  388. lwz r2,_CTR(r1)
  389. lwz r0,_LINK(r1)
  390. mtctr r2
  391. mtlr r0
  392. lwz r2,_XER(r1)
  393. lwz r0,_CCR(r1)
  394. mtspr XER,r2
  395. mtcrf 0xFF,r0
  396. REST_10GPRS(3, r1)
  397. REST_10GPRS(13, r1)
  398. REST_8GPRS(23, r1)
  399. REST_GPR(31, r1)
  400. lwz r2,_NIP(r1) /* Restore environment */
  401. lwz r0,_MSR(r1)
  402. mtspr SRR0,r2
  403. mtspr SRR1,r0
  404. lwz r0,GPR0(r1)
  405. lwz r2,GPR2(r1)
  406. lwz r1,GPR1(r1)
  407. SYNC
  408. rfi
  409. #endif /* !CONFIG_NAND_SPL */
  410. /*
  411. * This code initialises the E300 processor core
  412. * (conforms to PowerPC 603e spec)
  413. * Note: expects original MSR contents to be in r5.
  414. */
  415. .globl init_e300_core
  416. init_e300_core: /* time t 10 */
  417. /* Initialize machine status; enable machine check interrupt */
  418. /*-----------------------------------------------------------*/
  419. li r3, MSR_KERNEL /* Set ME and RI flags */
  420. rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
  421. #ifdef DEBUG
  422. rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
  423. #endif
  424. SYNC /* Some chip revs need this... */
  425. mtmsr r3
  426. SYNC
  427. mtspr SRR1, r3 /* Make SRR1 match MSR */
  428. lis r3, CONFIG_SYS_IMMR@h
  429. #if defined(CONFIG_WATCHDOG)
  430. /* Initialise the Watchdog values and reset it (if req) */
  431. /*------------------------------------------------------*/
  432. lis r4, CONFIG_SYS_WATCHDOG_VALUE
  433. ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
  434. stw r4, SWCRR(r3)
  435. /* and reset it */
  436. li r4, 0x556C
  437. sth r4, SWSRR@l(r3)
  438. li r4, -0x55C7
  439. sth r4, SWSRR@l(r3)
  440. #else
  441. /* Disable Watchdog */
  442. /*-------------------*/
  443. lwz r4, SWCRR(r3)
  444. /* Check to see if its enabled for disabling
  445. once disabled by SW you can't re-enable */
  446. andi. r4, r4, 0x4
  447. beq 1f
  448. xor r4, r4, r4
  449. stw r4, SWCRR(r3)
  450. 1:
  451. #endif /* CONFIG_WATCHDOG */
  452. #if defined(CONFIG_MASK_AER_AO)
  453. /* Write the Arbiter Event Enable to mask Address Only traps. */
  454. /* This prevents the dcbz instruction from being trapped when */
  455. /* HID0_ABE Address Broadcast Enable is set and the MEMORY */
  456. /* COHERENCY bit is set in the WIMG bits, which is often */
  457. /* needed for PCI operation. */
  458. lwz r4, 0x0808(r3)
  459. rlwinm r0, r4, 0, ~AER_AO
  460. stw r0, 0x0808(r3)
  461. #endif /* CONFIG_MASK_AER_AO */
  462. /* Initialize the Hardware Implementation-dependent Registers */
  463. /* HID0 also contains cache control */
  464. /* - force invalidation of data and instruction caches */
  465. /*------------------------------------------------------*/
  466. lis r3, CONFIG_SYS_HID0_INIT@h
  467. ori r3, r3, (CONFIG_SYS_HID0_INIT | HID0_ICFI | HID0_DCFI)@l
  468. SYNC
  469. mtspr HID0, r3
  470. lis r3, CONFIG_SYS_HID0_FINAL@h
  471. ori r3, r3, (CONFIG_SYS_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l
  472. SYNC
  473. mtspr HID0, r3
  474. lis r3, CONFIG_SYS_HID2@h
  475. ori r3, r3, CONFIG_SYS_HID2@l
  476. SYNC
  477. mtspr HID2, r3
  478. /* Done! */
  479. /*------------------------------*/
  480. blr
  481. /* setup_bats - set them up to some initial state */
  482. .globl setup_bats
  483. setup_bats:
  484. addis r0, r0, 0x0000
  485. /* IBAT 0 */
  486. addis r4, r0, CONFIG_SYS_IBAT0L@h
  487. ori r4, r4, CONFIG_SYS_IBAT0L@l
  488. addis r3, r0, CONFIG_SYS_IBAT0U@h
  489. ori r3, r3, CONFIG_SYS_IBAT0U@l
  490. mtspr IBAT0L, r4
  491. mtspr IBAT0U, r3
  492. /* DBAT 0 */
  493. addis r4, r0, CONFIG_SYS_DBAT0L@h
  494. ori r4, r4, CONFIG_SYS_DBAT0L@l
  495. addis r3, r0, CONFIG_SYS_DBAT0U@h
  496. ori r3, r3, CONFIG_SYS_DBAT0U@l
  497. mtspr DBAT0L, r4
  498. mtspr DBAT0U, r3
  499. /* IBAT 1 */
  500. addis r4, r0, CONFIG_SYS_IBAT1L@h
  501. ori r4, r4, CONFIG_SYS_IBAT1L@l
  502. addis r3, r0, CONFIG_SYS_IBAT1U@h
  503. ori r3, r3, CONFIG_SYS_IBAT1U@l
  504. mtspr IBAT1L, r4
  505. mtspr IBAT1U, r3
  506. /* DBAT 1 */
  507. addis r4, r0, CONFIG_SYS_DBAT1L@h
  508. ori r4, r4, CONFIG_SYS_DBAT1L@l
  509. addis r3, r0, CONFIG_SYS_DBAT1U@h
  510. ori r3, r3, CONFIG_SYS_DBAT1U@l
  511. mtspr DBAT1L, r4
  512. mtspr DBAT1U, r3
  513. /* IBAT 2 */
  514. addis r4, r0, CONFIG_SYS_IBAT2L@h
  515. ori r4, r4, CONFIG_SYS_IBAT2L@l
  516. addis r3, r0, CONFIG_SYS_IBAT2U@h
  517. ori r3, r3, CONFIG_SYS_IBAT2U@l
  518. mtspr IBAT2L, r4
  519. mtspr IBAT2U, r3
  520. /* DBAT 2 */
  521. addis r4, r0, CONFIG_SYS_DBAT2L@h
  522. ori r4, r4, CONFIG_SYS_DBAT2L@l
  523. addis r3, r0, CONFIG_SYS_DBAT2U@h
  524. ori r3, r3, CONFIG_SYS_DBAT2U@l
  525. mtspr DBAT2L, r4
  526. mtspr DBAT2U, r3
  527. /* IBAT 3 */
  528. addis r4, r0, CONFIG_SYS_IBAT3L@h
  529. ori r4, r4, CONFIG_SYS_IBAT3L@l
  530. addis r3, r0, CONFIG_SYS_IBAT3U@h
  531. ori r3, r3, CONFIG_SYS_IBAT3U@l
  532. mtspr IBAT3L, r4
  533. mtspr IBAT3U, r3
  534. /* DBAT 3 */
  535. addis r4, r0, CONFIG_SYS_DBAT3L@h
  536. ori r4, r4, CONFIG_SYS_DBAT3L@l
  537. addis r3, r0, CONFIG_SYS_DBAT3U@h
  538. ori r3, r3, CONFIG_SYS_DBAT3U@l
  539. mtspr DBAT3L, r4
  540. mtspr DBAT3U, r3
  541. #ifdef CONFIG_HIGH_BATS
  542. /* IBAT 4 */
  543. addis r4, r0, CONFIG_SYS_IBAT4L@h
  544. ori r4, r4, CONFIG_SYS_IBAT4L@l
  545. addis r3, r0, CONFIG_SYS_IBAT4U@h
  546. ori r3, r3, CONFIG_SYS_IBAT4U@l
  547. mtspr IBAT4L, r4
  548. mtspr IBAT4U, r3
  549. /* DBAT 4 */
  550. addis r4, r0, CONFIG_SYS_DBAT4L@h
  551. ori r4, r4, CONFIG_SYS_DBAT4L@l
  552. addis r3, r0, CONFIG_SYS_DBAT4U@h
  553. ori r3, r3, CONFIG_SYS_DBAT4U@l
  554. mtspr DBAT4L, r4
  555. mtspr DBAT4U, r3
  556. /* IBAT 5 */
  557. addis r4, r0, CONFIG_SYS_IBAT5L@h
  558. ori r4, r4, CONFIG_SYS_IBAT5L@l
  559. addis r3, r0, CONFIG_SYS_IBAT5U@h
  560. ori r3, r3, CONFIG_SYS_IBAT5U@l
  561. mtspr IBAT5L, r4
  562. mtspr IBAT5U, r3
  563. /* DBAT 5 */
  564. addis r4, r0, CONFIG_SYS_DBAT5L@h
  565. ori r4, r4, CONFIG_SYS_DBAT5L@l
  566. addis r3, r0, CONFIG_SYS_DBAT5U@h
  567. ori r3, r3, CONFIG_SYS_DBAT5U@l
  568. mtspr DBAT5L, r4
  569. mtspr DBAT5U, r3
  570. /* IBAT 6 */
  571. addis r4, r0, CONFIG_SYS_IBAT6L@h
  572. ori r4, r4, CONFIG_SYS_IBAT6L@l
  573. addis r3, r0, CONFIG_SYS_IBAT6U@h
  574. ori r3, r3, CONFIG_SYS_IBAT6U@l
  575. mtspr IBAT6L, r4
  576. mtspr IBAT6U, r3
  577. /* DBAT 6 */
  578. addis r4, r0, CONFIG_SYS_DBAT6L@h
  579. ori r4, r4, CONFIG_SYS_DBAT6L@l
  580. addis r3, r0, CONFIG_SYS_DBAT6U@h
  581. ori r3, r3, CONFIG_SYS_DBAT6U@l
  582. mtspr DBAT6L, r4
  583. mtspr DBAT6U, r3
  584. /* IBAT 7 */
  585. addis r4, r0, CONFIG_SYS_IBAT7L@h
  586. ori r4, r4, CONFIG_SYS_IBAT7L@l
  587. addis r3, r0, CONFIG_SYS_IBAT7U@h
  588. ori r3, r3, CONFIG_SYS_IBAT7U@l
  589. mtspr IBAT7L, r4
  590. mtspr IBAT7U, r3
  591. /* DBAT 7 */
  592. addis r4, r0, CONFIG_SYS_DBAT7L@h
  593. ori r4, r4, CONFIG_SYS_DBAT7L@l
  594. addis r3, r0, CONFIG_SYS_DBAT7U@h
  595. ori r3, r3, CONFIG_SYS_DBAT7U@l
  596. mtspr DBAT7L, r4
  597. mtspr DBAT7U, r3
  598. #endif
  599. isync
  600. /* invalidate all tlb's
  601. *
  602. * From the 603e User Manual: "The 603e provides the ability to
  603. * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
  604. * instruction invalidates the TLB entry indexed by the EA, and
  605. * operates on both the instruction and data TLBs simultaneously
  606. * invalidating four TLB entries (both sets in each TLB). The
  607. * index corresponds to bits 15-19 of the EA. To invalidate all
  608. * entries within both TLBs, 32 tlbie instructions should be
  609. * issued, incrementing this field by one each time."
  610. *
  611. * "Note that the tlbia instruction is not implemented on the
  612. * 603e."
  613. *
  614. * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
  615. * incrementing by 0x1000 each time. The code below is sort of
  616. * based on code in "flush_tlbs" from arch/powerpc/kernel/head.S
  617. *
  618. */
  619. lis r3, 0
  620. lis r5, 2
  621. 1:
  622. tlbie r3
  623. addi r3, r3, 0x1000
  624. cmp 0, 0, r3, r5
  625. blt 1b
  626. blr
  627. /* Cache functions.
  628. *
  629. * Note: requires that all cache bits in
  630. * HID0 are in the low half word.
  631. */
  632. #ifndef CONFIG_NAND_SPL
  633. .globl icache_enable
  634. icache_enable:
  635. mfspr r3, HID0
  636. ori r3, r3, HID0_ICE
  637. li r4, HID0_ICFI|HID0_ILOCK
  638. andc r3, r3, r4
  639. ori r4, r3, HID0_ICFI
  640. isync
  641. mtspr HID0, r4 /* sets enable and invalidate, clears lock */
  642. isync
  643. mtspr HID0, r3 /* clears invalidate */
  644. blr
  645. .globl icache_disable
  646. icache_disable:
  647. mfspr r3, HID0
  648. lis r4, 0
  649. ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK
  650. andc r3, r3, r4
  651. isync
  652. mtspr HID0, r3 /* clears invalidate, enable and lock */
  653. blr
  654. .globl icache_status
  655. icache_status:
  656. mfspr r3, HID0
  657. rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
  658. blr
  659. #endif /* !CONFIG_NAND_SPL */
  660. .globl dcache_enable
  661. dcache_enable:
  662. mfspr r3, HID0
  663. li r5, HID0_DCFI|HID0_DLOCK
  664. andc r3, r3, r5
  665. ori r3, r3, HID0_DCE
  666. sync
  667. mtspr HID0, r3 /* enable, no invalidate */
  668. blr
  669. .globl dcache_disable
  670. dcache_disable:
  671. mflr r4
  672. bl flush_dcache /* uses r3 and r5 */
  673. mfspr r3, HID0
  674. li r5, HID0_DCE|HID0_DLOCK
  675. andc r3, r3, r5
  676. ori r5, r3, HID0_DCFI
  677. sync
  678. mtspr HID0, r5 /* sets invalidate, clears enable and lock */
  679. sync
  680. mtspr HID0, r3 /* clears invalidate */
  681. mtlr r4
  682. blr
  683. .globl dcache_status
  684. dcache_status:
  685. mfspr r3, HID0
  686. rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
  687. blr
  688. .globl flush_dcache
  689. flush_dcache:
  690. lis r3, 0
  691. lis r5, CONFIG_SYS_CACHELINE_SIZE
  692. 1: cmp 0, 1, r3, r5
  693. bge 2f
  694. lwz r5, 0(r3)
  695. lis r5, CONFIG_SYS_CACHELINE_SIZE
  696. addi r3, r3, 0x4
  697. b 1b
  698. 2: blr
  699. /*-------------------------------------------------------------------*/
  700. /*
  701. * void relocate_code (addr_sp, gd, addr_moni)
  702. *
  703. * This "function" does not return, instead it continues in RAM
  704. * after relocating the monitor code.
  705. *
  706. * r3 = dest
  707. * r4 = src
  708. * r5 = length in bytes
  709. * r6 = cachelinesize
  710. */
  711. .globl relocate_code
  712. relocate_code:
  713. mr r1, r3 /* Set new stack pointer */
  714. mr r9, r4 /* Save copy of Global Data pointer */
  715. mr r10, r5 /* Save copy of Destination Address */
  716. GET_GOT
  717. mr r3, r5 /* Destination Address */
  718. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  719. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  720. lwz r5, GOT(__bss_start)
  721. sub r5, r5, r4
  722. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  723. /*
  724. * Fix GOT pointer:
  725. *
  726. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE)
  727. * + Destination Address
  728. *
  729. * Offset:
  730. */
  731. sub r15, r10, r4
  732. /* First our own GOT */
  733. add r12, r12, r15
  734. /* then the one used by the C code */
  735. add r30, r30, r15
  736. /*
  737. * Now relocate code
  738. */
  739. cmplw cr1,r3,r4
  740. addi r0,r5,3
  741. srwi. r0,r0,2
  742. beq cr1,4f /* In place copy is not necessary */
  743. beq 7f /* Protect against 0 count */
  744. mtctr r0
  745. bge cr1,2f
  746. la r8,-4(r4)
  747. la r7,-4(r3)
  748. /* copy */
  749. 1: lwzu r0,4(r8)
  750. stwu r0,4(r7)
  751. bdnz 1b
  752. addi r0,r5,3
  753. srwi. r0,r0,2
  754. mtctr r0
  755. la r8,-4(r4)
  756. la r7,-4(r3)
  757. /* and compare */
  758. 20: lwzu r20,4(r8)
  759. lwzu r21,4(r7)
  760. xor. r22, r20, r21
  761. bne 30f
  762. bdnz 20b
  763. b 4f
  764. /* compare failed */
  765. 30: li r3, 0
  766. blr
  767. 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
  768. add r8,r4,r0
  769. add r7,r3,r0
  770. 3: lwzu r0,-4(r8)
  771. stwu r0,-4(r7)
  772. bdnz 3b
  773. /*
  774. * Now flush the cache: note that we must start from a cache aligned
  775. * address. Otherwise we might miss one cache line.
  776. */
  777. 4: cmpwi r6,0
  778. add r5,r3,r5
  779. beq 7f /* Always flush prefetch queue in any case */
  780. subi r0,r6,1
  781. andc r3,r3,r0
  782. mr r4,r3
  783. 5: dcbst 0,r4
  784. add r4,r4,r6
  785. cmplw r4,r5
  786. blt 5b
  787. sync /* Wait for all dcbst to complete on bus */
  788. mr r4,r3
  789. 6: icbi 0,r4
  790. add r4,r4,r6
  791. cmplw r4,r5
  792. blt 6b
  793. 7: sync /* Wait for all icbi to complete on bus */
  794. isync
  795. /*
  796. * We are done. Do not return, instead branch to second part of board
  797. * initialization, now running from RAM.
  798. */
  799. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  800. mtlr r0
  801. blr
  802. in_ram:
  803. /*
  804. * Relocation Function, r12 point to got2+0x8000
  805. *
  806. * Adjust got2 pointers, no need to check for 0, this code
  807. * already puts a few entries in the table.
  808. */
  809. li r0,__got2_entries@sectoff@l
  810. la r3,GOT(_GOT2_TABLE_)
  811. lwz r11,GOT(_GOT2_TABLE_)
  812. mtctr r0
  813. sub r11,r3,r11
  814. addi r3,r3,-4
  815. 1: lwzu r0,4(r3)
  816. cmpwi r0,0
  817. beq- 2f
  818. add r0,r0,r11
  819. stw r0,0(r3)
  820. 2: bdnz 1b
  821. #ifndef CONFIG_NAND_SPL
  822. /*
  823. * Now adjust the fixups and the pointers to the fixups
  824. * in case we need to move ourselves again.
  825. */
  826. li r0,__fixup_entries@sectoff@l
  827. lwz r3,GOT(_FIXUP_TABLE_)
  828. cmpwi r0,0
  829. mtctr r0
  830. addi r3,r3,-4
  831. beq 4f
  832. 3: lwzu r4,4(r3)
  833. lwzux r0,r4,r11
  834. cmpwi r0,0
  835. add r0,r0,r11
  836. stw r10,0(r3)
  837. beq- 5f
  838. stw r0,0(r4)
  839. 5: bdnz 3b
  840. 4:
  841. #endif
  842. clear_bss:
  843. /*
  844. * Now clear BSS segment
  845. */
  846. lwz r3,GOT(__bss_start)
  847. #if defined(CONFIG_HYMOD)
  848. /*
  849. * For HYMOD - the environment is the very last item in flash.
  850. * The real .bss stops just before environment starts, so only
  851. * clear up to that point.
  852. *
  853. * taken from mods for FADS board
  854. */
  855. lwz r4,GOT(environment)
  856. #else
  857. lwz r4,GOT(_end)
  858. #endif
  859. cmplw 0, r3, r4
  860. beq 6f
  861. li r0, 0
  862. 5:
  863. stw r0, 0(r3)
  864. addi r3, r3, 4
  865. cmplw 0, r3, r4
  866. bne 5b
  867. 6:
  868. mr r3, r9 /* Global Data pointer */
  869. mr r4, r10 /* Destination Address */
  870. bl board_init_r
  871. #ifndef CONFIG_NAND_SPL
  872. /*
  873. * Copy exception vector code to low memory
  874. *
  875. * r3: dest_addr
  876. * r7: source address, r8: end address, r9: target address
  877. */
  878. .globl trap_init
  879. trap_init:
  880. mflr r4 /* save link register */
  881. GET_GOT
  882. lwz r7, GOT(_start)
  883. lwz r8, GOT(_end_of_vectors)
  884. li r9, 0x100 /* reset vector always at 0x100 */
  885. cmplw 0, r7, r8
  886. bgelr /* return if r7>=r8 - just in case */
  887. 1:
  888. lwz r0, 0(r7)
  889. stw r0, 0(r9)
  890. addi r7, r7, 4
  891. addi r9, r9, 4
  892. cmplw 0, r7, r8
  893. bne 1b
  894. /*
  895. * relocate `hdlr' and `int_return' entries
  896. */
  897. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  898. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  899. 2:
  900. bl trap_reloc
  901. addi r7, r7, 0x100 /* next exception vector */
  902. cmplw 0, r7, r8
  903. blt 2b
  904. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  905. bl trap_reloc
  906. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  907. bl trap_reloc
  908. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  909. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  910. 3:
  911. bl trap_reloc
  912. addi r7, r7, 0x100 /* next exception vector */
  913. cmplw 0, r7, r8
  914. blt 3b
  915. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  916. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  917. 4:
  918. bl trap_reloc
  919. addi r7, r7, 0x100 /* next exception vector */
  920. cmplw 0, r7, r8
  921. blt 4b
  922. mfmsr r3 /* now that the vectors have */
  923. lis r7, MSR_IP@h /* relocated into low memory */
  924. ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
  925. andc r3, r3, r7 /* (if it was on) */
  926. SYNC /* Some chip revs need this... */
  927. mtmsr r3
  928. SYNC
  929. mtlr r4 /* restore link register */
  930. blr
  931. #endif /* !CONFIG_NAND_SPL */
  932. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  933. lock_ram_in_cache:
  934. /* Allocate Initial RAM in data cache.
  935. */
  936. lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
  937. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
  938. li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
  939. (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
  940. mtctr r4
  941. 1:
  942. dcbz r0, r3
  943. addi r3, r3, 32
  944. bdnz 1b
  945. /* Lock the data cache */
  946. mfspr r0, HID0
  947. ori r0, r0, HID0_DLOCK
  948. sync
  949. mtspr HID0, r0
  950. sync
  951. blr
  952. #ifndef CONFIG_NAND_SPL
  953. .globl unlock_ram_in_cache
  954. unlock_ram_in_cache:
  955. /* invalidate the INIT_RAM section */
  956. lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
  957. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
  958. li r4, ((CONFIG_SYS_INIT_RAM_SIZE & ~31) + \
  959. (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
  960. mtctr r4
  961. 1: icbi r0, r3
  962. dcbi r0, r3
  963. addi r3, r3, 32
  964. bdnz 1b
  965. sync /* Wait for all icbi to complete on bus */
  966. isync
  967. /* Unlock the data cache and invalidate it */
  968. mfspr r3, HID0
  969. li r5, HID0_DLOCK|HID0_DCFI
  970. andc r3, r3, r5 /* no invalidate, unlock */
  971. ori r5, r3, HID0_DCFI /* invalidate, unlock */
  972. sync
  973. mtspr HID0, r5 /* invalidate, unlock */
  974. sync
  975. mtspr HID0, r3 /* no invalidate, unlock */
  976. blr
  977. #endif /* !CONFIG_NAND_SPL */
  978. #endif /* CONFIG_SYS_INIT_RAM_LOCK */
  979. #ifdef CONFIG_SYS_FLASHBOOT
  980. map_flash_by_law1:
  981. /* When booting from ROM (Flash or EPROM), clear the */
  982. /* Address Mask in OR0 so ROM appears everywhere */
  983. /*----------------------------------------------------*/
  984. lis r3, (CONFIG_SYS_IMMR)@h /* r3 <= CONFIG_SYS_IMMR */
  985. lwz r4, OR0@l(r3)
  986. li r5, 0x7fff /* r5 <= 0x00007FFFF */
  987. and r4, r4, r5
  988. stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
  989. /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
  990. * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
  991. * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
  992. * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
  993. * 0xFF800. From the hard resetting to here, the processor fetched and
  994. * executed the instructions one by one. There is not absolutely
  995. * jumping happened. Laterly, the u-boot code has to do an absolutely
  996. * jumping to tell the CPU instruction fetching component what the
  997. * u-boot TEXT base address is. Because the TEXT base resides in the
  998. * boot ROM memory space, to garantee the code can run smoothly after
  999. * that jumping, we must map in the entire boot ROM by Local Access
  1000. * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
  1001. * address for boot ROM, such as 0xFE000000. In this case, the default
  1002. * LBIU Local Access Widow 0 will not cover this memory space. So, we
  1003. * need another window to map in it.
  1004. */
  1005. lis r4, (CONFIG_SYS_FLASH_BASE)@h
  1006. ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
  1007. stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CONFIG_SYS_FLASH_BASE */
  1008. /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR1 */
  1009. lis r4, (0x80000012)@h
  1010. ori r4, r4, (0x80000012)@l
  1011. li r5, CONFIG_SYS_FLASH_SIZE
  1012. 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
  1013. addi r4, r4, 1
  1014. bne 1b
  1015. stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
  1016. blr
  1017. /* Though all the LBIU Local Access Windows and LBC Banks will be
  1018. * initialized in the C code, we'd better configure boot ROM's
  1019. * window 0 and bank 0 correctly at here.
  1020. */
  1021. remap_flash_by_law0:
  1022. /* Initialize the BR0 with the boot ROM starting address. */
  1023. lwz r4, BR0(r3)
  1024. li r5, 0x7FFF
  1025. and r4, r4, r5
  1026. lis r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@h
  1027. ori r5, r5, (CONFIG_SYS_FLASH_BASE & 0xFFFF8000)@l
  1028. or r5, r5, r4
  1029. stw r5, BR0(r3) /* r5 <= (CONFIG_SYS_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
  1030. lwz r4, OR0(r3)
  1031. lis r5, ~((CONFIG_SYS_FLASH_SIZE << 4) - 1)
  1032. or r4, r4, r5
  1033. stw r4, OR0(r3)
  1034. lis r4, (CONFIG_SYS_FLASH_BASE)@h
  1035. ori r4, r4, (CONFIG_SYS_FLASH_BASE)@l
  1036. stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CONFIG_SYS_FLASH_BASE */
  1037. /* Store 0x80000012 + log2(CONFIG_SYS_FLASH_SIZE) into LBLAWAR0 */
  1038. lis r4, (0x80000012)@h
  1039. ori r4, r4, (0x80000012)@l
  1040. li r5, CONFIG_SYS_FLASH_SIZE
  1041. 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
  1042. addi r4, r4, 1
  1043. bne 1b
  1044. stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
  1045. xor r4, r4, r4
  1046. stw r4, LBLAWBAR1(r3)
  1047. stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */
  1048. blr
  1049. #endif /* CONFIG_SYS_FLASHBOOT */