start.S 13 KB

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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
  5. * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * File: start.S
  27. *
  28. * Discription: startup code
  29. *
  30. */
  31. #include <asm-offsets.h>
  32. #include <config.h>
  33. #include <mpc5xx.h>
  34. #include <timestamp.h>
  35. #include <version.h>
  36. #define CONFIG_5xx 1 /* needed for Linux kernel header files */
  37. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  38. #include <ppc_asm.tmpl>
  39. #include <ppc_defs.h>
  40. #include <linux/config.h>
  41. #include <asm/processor.h>
  42. #include <asm/u-boot.h>
  43. #ifndef CONFIG_IDENT_STRING
  44. #define CONFIG_IDENT_STRING ""
  45. #endif
  46. /* We don't have a MMU.
  47. */
  48. #undef MSR_KERNEL
  49. #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
  50. /*
  51. * Set up GOT: Global Offset Table
  52. *
  53. * Use r12 to access the GOT
  54. */
  55. START_GOT
  56. GOT_ENTRY(_GOT2_TABLE_)
  57. GOT_ENTRY(_FIXUP_TABLE_)
  58. GOT_ENTRY(_start)
  59. GOT_ENTRY(_start_of_vectors)
  60. GOT_ENTRY(_end_of_vectors)
  61. GOT_ENTRY(transfer_to_handler)
  62. GOT_ENTRY(__init_end)
  63. GOT_ENTRY(_end)
  64. GOT_ENTRY(__bss_start)
  65. END_GOT
  66. /*
  67. * r3 - 1st arg to board_init(): IMMP pointer
  68. * r4 - 2nd arg to board_init(): boot flag
  69. */
  70. .text
  71. .long 0x27051956 /* U-Boot Magic Number */
  72. .globl version_string
  73. version_string:
  74. .ascii U_BOOT_VERSION
  75. .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  76. .ascii CONFIG_IDENT_STRING, "\0"
  77. . = EXC_OFF_SYS_RESET
  78. .globl _start
  79. _start:
  80. mfspr r3, 638
  81. li r4, CONFIG_SYS_ISB /* Set ISB bit */
  82. or r3, r3, r4
  83. mtspr 638, r3
  84. /* Initialize machine status; enable machine check interrupt */
  85. /*----------------------------------------------------------------------*/
  86. li r3, MSR_KERNEL /* Set ME, RI flags */
  87. mtmsr r3
  88. mtspr SRR1, r3 /* Make SRR1 match MSR */
  89. /* Initialize debug port registers */
  90. /*----------------------------------------------------------------------*/
  91. xor r0, r0, r0 /* Clear R0 */
  92. mtspr LCTRL1, r0 /* Initialize debug port regs */
  93. mtspr LCTRL2, r0
  94. mtspr COUNTA, r0
  95. mtspr COUNTB, r0
  96. #if defined(CONFIG_PATI)
  97. /* the external flash access on PATI fails if programming the PLL to 40MHz.
  98. * Copy the PLL programming code to the internal RAM and execute it
  99. *----------------------------------------------------------------------*/
  100. lis r3, CONFIG_SYS_MONITOR_BASE@h
  101. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  102. addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
  103. lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
  104. ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
  105. mtlr r4
  106. addis r5,0,0x0
  107. ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
  108. mtctr r5
  109. addi r3, r3, -4
  110. addi r4, r4, -4
  111. 0:
  112. lwzu r0,4(r3)
  113. stwu r0,4(r4)
  114. bdnz 0b /* copy loop */
  115. blrl
  116. #endif
  117. /*
  118. * Calculate absolute address in FLASH and jump there
  119. *----------------------------------------------------------------------*/
  120. lis r3, CONFIG_SYS_MONITOR_BASE@h
  121. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  122. addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  123. mtlr r3
  124. blr
  125. in_flash:
  126. /* Initialize some SPRs that are hard to access from C */
  127. /*----------------------------------------------------------------------*/
  128. lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */
  129. lis r2, CONFIG_SYS_INIT_SP_ADDR@h
  130. ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
  131. /* Note: R0 is still 0 here */
  132. stwu r0, -4(r1) /* Clear final stack frame so that */
  133. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  134. /*
  135. * Disable serialized ifetch and show cycles
  136. * (i.e. set processor to normal mode) for maximum
  137. * performance.
  138. */
  139. li r2, 0x0007
  140. mtspr ICTRL, r2
  141. /* Set up debug mode entry */
  142. lis r2, CONFIG_SYS_DER@h
  143. ori r2, r2, CONFIG_SYS_DER@l
  144. mtspr DER, r2
  145. /* Let the C-code set up the rest */
  146. /* */
  147. /* Be careful to keep code relocatable ! */
  148. /*----------------------------------------------------------------------*/
  149. GET_GOT /* initialize GOT access */
  150. /* r3: IMMR */
  151. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  152. bl board_init_f /* run 1st part of board init code (from Flash) */
  153. /* NOTREACHED - board_init_f() does not return */
  154. .globl _start_of_vectors
  155. _start_of_vectors:
  156. /* Machine check */
  157. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  158. /* Data Storage exception. "Never" generated on the 860. */
  159. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  160. /* Instruction Storage exception. "Never" generated on the 860. */
  161. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  162. /* External Interrupt exception. */
  163. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  164. /* Alignment exception. */
  165. . = 0x600
  166. Alignment:
  167. EXCEPTION_PROLOG(SRR0, SRR1)
  168. mfspr r4,DAR
  169. stw r4,_DAR(r21)
  170. mfspr r5,DSISR
  171. stw r5,_DSISR(r21)
  172. addi r3,r1,STACK_FRAME_OVERHEAD
  173. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  174. /* Program check exception */
  175. . = 0x700
  176. ProgramCheck:
  177. EXCEPTION_PROLOG(SRR0, SRR1)
  178. addi r3,r1,STACK_FRAME_OVERHEAD
  179. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  180. MSR_KERNEL, COPY_EE)
  181. /* FPU on MPC5xx available. We will use it later.
  182. */
  183. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  184. /* I guess we could implement decrementer, and may have
  185. * to someday for timekeeping.
  186. */
  187. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  188. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  189. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  190. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  191. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  192. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  193. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  194. /* On the MPC8xx, this is a software emulation interrupt. It occurs
  195. * for all unimplemented and illegal instructions.
  196. */
  197. STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
  198. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  199. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  200. STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
  201. STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
  202. STD_EXCEPTION(0x1500, Reserved5, UnknownException)
  203. STD_EXCEPTION(0x1600, Reserved6, UnknownException)
  204. STD_EXCEPTION(0x1700, Reserved7, UnknownException)
  205. STD_EXCEPTION(0x1800, Reserved8, UnknownException)
  206. STD_EXCEPTION(0x1900, Reserved9, UnknownException)
  207. STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
  208. STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
  209. STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
  210. STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
  211. STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
  212. STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
  213. .globl _end_of_vectors
  214. _end_of_vectors:
  215. . = 0x2000
  216. /*
  217. * This code finishes saving the registers to the exception frame
  218. * and jumps to the appropriate handler for the exception.
  219. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  220. */
  221. .globl transfer_to_handler
  222. transfer_to_handler:
  223. stw r22,_NIP(r21)
  224. lis r22,MSR_POW@h
  225. andc r23,r23,r22
  226. stw r23,_MSR(r21)
  227. SAVE_GPR(7, r21)
  228. SAVE_4GPRS(8, r21)
  229. SAVE_8GPRS(12, r21)
  230. SAVE_8GPRS(24, r21)
  231. mflr r23
  232. andi. r24,r23,0x3f00 /* get vector offset */
  233. stw r24,TRAP(r21)
  234. li r22,0
  235. stw r22,RESULT(r21)
  236. mtspr SPRG2,r22 /* r1 is now kernel sp */
  237. lwz r24,0(r23) /* virtual address of handler */
  238. lwz r23,4(r23) /* where to go when done */
  239. mtspr SRR0,r24
  240. mtspr SRR1,r20
  241. mtlr r23
  242. SYNC
  243. rfi /* jump to handler, enable MMU */
  244. int_return:
  245. mfmsr r28 /* Disable interrupts */
  246. li r4,0
  247. ori r4,r4,MSR_EE
  248. andc r28,r28,r4
  249. SYNC /* Some chip revs need this... */
  250. mtmsr r28
  251. SYNC
  252. lwz r2,_CTR(r1)
  253. lwz r0,_LINK(r1)
  254. mtctr r2
  255. mtlr r0
  256. lwz r2,_XER(r1)
  257. lwz r0,_CCR(r1)
  258. mtspr XER,r2
  259. mtcrf 0xFF,r0
  260. REST_10GPRS(3, r1)
  261. REST_10GPRS(13, r1)
  262. REST_8GPRS(23, r1)
  263. REST_GPR(31, r1)
  264. lwz r2,_NIP(r1) /* Restore environment */
  265. lwz r0,_MSR(r1)
  266. mtspr SRR0,r2
  267. mtspr SRR1,r0
  268. lwz r0,GPR0(r1)
  269. lwz r2,GPR2(r1)
  270. lwz r1,GPR1(r1)
  271. SYNC
  272. rfi
  273. /*
  274. * unsigned int get_immr (unsigned int mask)
  275. *
  276. * return (mask ? (IMMR & mask) : IMMR);
  277. */
  278. .globl get_immr
  279. get_immr:
  280. mr r4,r3 /* save mask */
  281. mfspr r3, IMMR /* IMMR */
  282. cmpwi 0,r4,0 /* mask != 0 ? */
  283. beq 4f
  284. and r3,r3,r4 /* IMMR & mask */
  285. 4:
  286. blr
  287. .globl get_pvr
  288. get_pvr:
  289. mfspr r3, PVR
  290. blr
  291. /*------------------------------------------------------------------------------*/
  292. /*
  293. * void relocate_code (addr_sp, gd, addr_moni)
  294. *
  295. * This "function" does not return, instead it continues in RAM
  296. * after relocating the monitor code.
  297. *
  298. * r3 = dest
  299. * r4 = src
  300. * r5 = length in bytes
  301. * r6 = cachelinesize
  302. */
  303. .globl relocate_code
  304. relocate_code:
  305. mr r1, r3 /* Set new stack pointer in SRAM */
  306. mr r9, r4 /* Save copy of global data pointer in SRAM */
  307. mr r10, r5 /* Save copy of monitor destination Address in SRAM */
  308. GET_GOT
  309. mr r3, r5 /* Destination Address */
  310. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  311. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  312. lwz r5, GOT(__init_end)
  313. sub r5, r5, r4
  314. /*
  315. * Fix GOT pointer:
  316. *
  317. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  318. *
  319. * Offset:
  320. */
  321. sub r15, r10, r4
  322. /* First our own GOT */
  323. add r12, r12, r15
  324. /* the the one used by the C code */
  325. add r30, r30, r15
  326. /*
  327. * Now relocate code
  328. */
  329. cmplw cr1,r3,r4
  330. addi r0,r5,3
  331. srwi. r0,r0,2
  332. beq cr1,4f /* In place copy is not necessary */
  333. beq 4f /* Protect against 0 count */
  334. mtctr r0
  335. bge cr1,2f
  336. la r8,-4(r4)
  337. la r7,-4(r3)
  338. 1: lwzu r0,4(r8)
  339. stwu r0,4(r7)
  340. bdnz 1b
  341. b 4f
  342. 2: slwi r0,r0,2
  343. add r8,r4,r0
  344. add r7,r3,r0
  345. 3: lwzu r0,-4(r8)
  346. stwu r0,-4(r7)
  347. bdnz 3b
  348. 4: sync
  349. isync
  350. /*
  351. * We are done. Do not return, instead branch to second part of board
  352. * initialization, now running from RAM.
  353. */
  354. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  355. mtlr r0
  356. blr
  357. in_ram:
  358. /*
  359. * Relocation Function, r12 point to got2+0x8000
  360. *
  361. * Adjust got2 pointers, no need to check for 0, this code
  362. * already puts a few entries in the table.
  363. */
  364. li r0,__got2_entries@sectoff@l
  365. la r3,GOT(_GOT2_TABLE_)
  366. lwz r11,GOT(_GOT2_TABLE_)
  367. mtctr r0
  368. sub r11,r3,r11
  369. addi r3,r3,-4
  370. 1: lwzu r0,4(r3)
  371. cmpwi r0,0
  372. beq- 2f
  373. add r0,r0,r11
  374. stw r0,0(r3)
  375. 2: bdnz 1b
  376. /*
  377. * Now adjust the fixups and the pointers to the fixups
  378. * in case we need to move ourselves again.
  379. */
  380. li r0,__fixup_entries@sectoff@l
  381. lwz r3,GOT(_FIXUP_TABLE_)
  382. cmpwi r0,0
  383. mtctr r0
  384. addi r3,r3,-4
  385. beq 4f
  386. 3: lwzu r4,4(r3)
  387. lwzux r0,r4,r11
  388. cmpwi r0,0
  389. add r0,r0,r11
  390. stw r10,0(r3)
  391. beq- 5f
  392. stw r0,0(r4)
  393. 5: bdnz 3b
  394. 4:
  395. clear_bss:
  396. /*
  397. * Now clear BSS segment
  398. */
  399. lwz r3,GOT(__bss_start)
  400. lwz r4,GOT(_end)
  401. cmplw 0, r3, r4
  402. beq 6f
  403. li r0, 0
  404. 5:
  405. stw r0, 0(r3)
  406. addi r3, r3, 4
  407. cmplw 0, r3, r4
  408. bne 5b
  409. 6:
  410. mr r3, r9 /* Global Data pointer */
  411. mr r4, r10 /* Destination Address */
  412. bl board_init_r
  413. /*
  414. * Copy exception vector code to low memory
  415. *
  416. * r3: dest_addr
  417. * r7: source address, r8: end address, r9: target address
  418. */
  419. .globl trap_init
  420. trap_init:
  421. mflr r4 /* save link register */
  422. GET_GOT
  423. lwz r7, GOT(_start)
  424. lwz r8, GOT(_end_of_vectors)
  425. li r9, 0x100 /* reset vector always at 0x100 */
  426. cmplw 0, r7, r8
  427. bgelr /* return if r7>=r8 - just in case */
  428. 1:
  429. lwz r0, 0(r7)
  430. stw r0, 0(r9)
  431. addi r7, r7, 4
  432. addi r9, r9, 4
  433. cmplw 0, r7, r8
  434. bne 1b
  435. /*
  436. * relocate `hdlr' and `int_return' entries
  437. */
  438. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  439. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  440. 2:
  441. bl trap_reloc
  442. addi r7, r7, 0x100 /* next exception vector */
  443. cmplw 0, r7, r8
  444. blt 2b
  445. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  446. bl trap_reloc
  447. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  448. bl trap_reloc
  449. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  450. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  451. 3:
  452. bl trap_reloc
  453. addi r7, r7, 0x100 /* next exception vector */
  454. cmplw 0, r7, r8
  455. blt 3b
  456. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  457. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  458. 4:
  459. bl trap_reloc
  460. addi r7, r7, 0x100 /* next exception vector */
  461. cmplw 0, r7, r8
  462. blt 4b
  463. mtlr r4 /* restore link register */
  464. blr
  465. #if defined(CONFIG_PATI)
  466. /* Program the PLL */
  467. pll_prog_code_start:
  468. lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
  469. ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
  470. lis r3, (0x55ccaa33)@h
  471. ori r3, r3, (0x55ccaa33)@l
  472. stw r3, 0(r4)
  473. lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
  474. ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
  475. lis r3, CONFIG_SYS_PLPRCR@h
  476. ori r3, r3, CONFIG_SYS_PLPRCR@l
  477. stw r3, 0(r4)
  478. addis r3,0,0x0
  479. ori r3,r3,0xA000
  480. mtctr r3
  481. ..spinlp:
  482. bdnz ..spinlp /* spin loop */
  483. blr
  484. pll_prog_code_end:
  485. nop
  486. blr
  487. #endif