immap_5275.h 7.2 KB

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  1. /*
  2. * MCF5274/5 Internal Memory Map
  3. *
  4. * Copyright (c) 2005 Arthur Shipkowski <art@videon-central.com>
  5. * Based on work Copyright (c) 2003 Josef Baumgartner
  6. * <josef.baumgartner@telex.de>
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #ifndef __IMMAP_5275__
  27. #define __IMMAP_5275__
  28. #define MMAP_SCM (CONFIG_SYS_MBAR + 0x00000000)
  29. #define MMAP_SDRAM (CONFIG_SYS_MBAR + 0x00000040)
  30. #define MMAP_FBCS (CONFIG_SYS_MBAR + 0x00000080)
  31. #define MMAP_DMA0 (CONFIG_SYS_MBAR + 0x00000100)
  32. #define MMAP_DMA1 (CONFIG_SYS_MBAR + 0x00000110)
  33. #define MMAP_DMA2 (CONFIG_SYS_MBAR + 0x00000120)
  34. #define MMAP_DMA3 (CONFIG_SYS_MBAR + 0x00000130)
  35. #define MMAP_UART0 (CONFIG_SYS_MBAR + 0x00000200)
  36. #define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000240)
  37. #define MMAP_UART2 (CONFIG_SYS_MBAR + 0x00000280)
  38. #define MMAP_I2C (CONFIG_SYS_MBAR + 0x00000300)
  39. #define MMAP_QSPI (CONFIG_SYS_MBAR + 0x00000340)
  40. #define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000400)
  41. #define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000440)
  42. #define MMAP_DTMR2 (CONFIG_SYS_MBAR + 0x00000480)
  43. #define MMAP_DTMR3 (CONFIG_SYS_MBAR + 0x000004C0)
  44. #define MMAP_INTC0 (CONFIG_SYS_MBAR + 0x00000C00)
  45. #define MMAP_INTC1 (CONFIG_SYS_MBAR + 0x00000D00)
  46. #define MMAP_INTCACK (CONFIG_SYS_MBAR + 0x00000F00)
  47. #define MMAP_FEC0 (CONFIG_SYS_MBAR + 0x00001000)
  48. #define MMAP_FEC0FIFO (CONFIG_SYS_MBAR + 0x00001400)
  49. #define MMAP_FEC1 (CONFIG_SYS_MBAR + 0x00001800)
  50. #define MMAP_FEC1FIFO (CONFIG_SYS_MBAR + 0x00001C00)
  51. #define MMAP_GPIO (CONFIG_SYS_MBAR + 0x00100000)
  52. #define MMAP_RCM (CONFIG_SYS_MBAR + 0x00110000)
  53. #define MMAP_CCM (CONFIG_SYS_MBAR + 0x00110004)
  54. #define MMAP_PLL (CONFIG_SYS_MBAR + 0x00120000)
  55. #define MMAP_EPORT (CONFIG_SYS_MBAR + 0x00130000)
  56. #define MMAP_WDOG (CONFIG_SYS_MBAR + 0x00140000)
  57. #define MMAP_PIT0 (CONFIG_SYS_MBAR + 0x00150000)
  58. #define MMAP_PIT1 (CONFIG_SYS_MBAR + 0x00160000)
  59. #define MMAP_PIT2 (CONFIG_SYS_MBAR + 0x00170000)
  60. #define MMAP_PIT3 (CONFIG_SYS_MBAR + 0x00180000)
  61. #define MMAP_MDHA (CONFIG_SYS_MBAR + 0x00190000)
  62. #define MMAP_RNG (CONFIG_SYS_MBAR + 0x001A0000)
  63. #define MMAP_SKHA (CONFIG_SYS_MBAR + 0x001B0000)
  64. #define MMAP_USB (CONFIG_SYS_MBAR + 0x001C0000)
  65. #define MMAP_PWM0 (CONFIG_SYS_MBAR + 0x001D0000)
  66. #include <asm/coldfire/eport.h>
  67. #include <asm/coldfire/flexbus.h>
  68. #include <asm/coldfire/intctrl.h>
  69. #include <asm/coldfire/mdha.h>
  70. #include <asm/coldfire/pwm.h>
  71. #include <asm/coldfire/qspi.h>
  72. #include <asm/coldfire/rng.h>
  73. #include <asm/coldfire/skha.h>
  74. /* System configuration registers
  75. */
  76. typedef struct sys_ctrl {
  77. u32 ipsbar;
  78. u32 res1;
  79. u32 rambar;
  80. u32 res2;
  81. u8 crsr;
  82. u8 cwcr;
  83. u8 lpicr;
  84. u8 cwsr;
  85. u8 res3[8];
  86. u32 mpark;
  87. u8 mpr;
  88. u8 res4[3];
  89. u8 pacr0;
  90. u8 pacr1;
  91. u8 pacr2;
  92. u8 pacr3;
  93. u8 pacr4;
  94. u8 res5;
  95. u8 pacr5;
  96. u8 pacr6;
  97. u8 pacr7;
  98. u8 res6;
  99. u8 pacr8;
  100. u8 res7;
  101. u8 gpacr;
  102. u8 res8[3];
  103. } sysctrl_t;
  104. /* SDRAM controller registers, offset: 0x040
  105. */
  106. typedef struct sdram_ctrl {
  107. u32 sdmr;
  108. u32 sdcr;
  109. u32 sdcfg1;
  110. u32 sdcfg2;
  111. u32 sdbar0;
  112. u32 sdbmr0;
  113. u32 sdbar1;
  114. u32 sdbmr1;
  115. } sdramctrl_t;
  116. /* DMA module registers, offset 0x100
  117. */
  118. typedef struct dma_ctrl {
  119. u32 sar;
  120. u32 dar;
  121. u32 dsrbcr;
  122. u32 dcr;
  123. } dma_t;
  124. /* GPIO port registers
  125. */
  126. typedef struct gpio_ctrl {
  127. /* Port Output Data Registers */
  128. u8 podr_res1[4];
  129. u8 podr_busctl;
  130. u8 podr_addr;
  131. u8 podr_res2[2];
  132. u8 podr_cs;
  133. u8 podr_res3;
  134. u8 podr_fec0h;
  135. u8 podr_fec0l;
  136. u8 podr_feci2c;
  137. u8 podr_qspi;
  138. u8 podr_sdram;
  139. u8 podr_timerh;
  140. u8 podr_timerl;
  141. u8 podr_uartl;
  142. u8 podr_fec1h;
  143. u8 podr_fec1l;
  144. u8 podr_bs;
  145. u8 podr_res4;
  146. u8 podr_usbh;
  147. u8 podr_usbl;
  148. u8 podr_uarth;
  149. u8 podr_res5[3];
  150. /* Port Data Direction Registers */
  151. u8 pddr_res1[4];
  152. u8 pddr_busctl;
  153. u8 pddr_addr;
  154. u8 pddr_res2[2];
  155. u8 pddr_cs;
  156. u8 pddr_res3;
  157. u8 pddr_fec0h;
  158. u8 pddr_fec0l;
  159. u8 pddr_feci2c;
  160. u8 pddr_qspi;
  161. u8 pddr_sdram;
  162. u8 pddr_timerh;
  163. u8 pddr_timerl;
  164. u8 pddr_uartl;
  165. u8 pddr_fec1h;
  166. u8 pddr_fec1l;
  167. u8 pddr_bs;
  168. u8 pddr_res4;
  169. u8 pddr_usbh;
  170. u8 pddr_usbl;
  171. u8 pddr_uarth;
  172. u8 pddr_res5[3];
  173. /* Port Pin Data/Set Registers */
  174. u8 ppdsdr_res1[4];
  175. u8 ppdsdr_busctl;
  176. u8 ppdsdr_addr;
  177. u8 ppdsdr_res2[2];
  178. u8 ppdsdr_cs;
  179. u8 ppdsdr_res3;
  180. u8 ppdsdr_fec0h;
  181. u8 ppdsdr_fec0l;
  182. u8 ppdsdr_feci2c;
  183. u8 ppdsdr_qspi;
  184. u8 ppdsdr_sdram;
  185. u8 ppdsdr_timerh;
  186. u8 ppdsdr_timerl;
  187. u8 ppdsdr_uartl;
  188. u8 ppdsdr_fec1h;
  189. u8 ppdsdr_fec1l;
  190. u8 ppdsdr_bs;
  191. u8 ppdsdr_res4;
  192. u8 ppdsdr_usbh;
  193. u8 ppdsdr_usbl;
  194. u8 ppdsdr_uarth;
  195. u8 ppdsdr_res5[3];
  196. /* Port Clear Output Data Registers */
  197. u8 pclrr_res1[4];
  198. u8 pclrr_busctl;
  199. u8 pclrr_addr;
  200. u8 pclrr_res2[2];
  201. u8 pclrr_cs;
  202. u8 pclrr_res3;
  203. u8 pclrr_fec0h;
  204. u8 pclrr_fec0l;
  205. u8 pclrr_feci2c;
  206. u8 pclrr_qspi;
  207. u8 pclrr_sdram;
  208. u8 pclrr_timerh;
  209. u8 pclrr_timerl;
  210. u8 pclrr_uartl;
  211. u8 pclrr_fec1h;
  212. u8 pclrr_fec1l;
  213. u8 pclrr_bs;
  214. u8 pclrr_res4;
  215. u8 pclrr_usbh;
  216. u8 pclrr_usbl;
  217. u8 pclrr_uarth;
  218. u8 pclrr_res5[3];
  219. /* Pin Assignment Registers */
  220. u8 par_addr;
  221. u8 par_cs;
  222. u16 par_busctl;
  223. u8 par_res1[2];
  224. u16 par_usb;
  225. u8 par_fec0hl;
  226. u8 par_fec1hl;
  227. u16 par_timer;
  228. u16 par_uart;
  229. u16 par_qspi;
  230. u16 par_sdram;
  231. u16 par_feci2c;
  232. u8 par_bs;
  233. u8 par_res2[3];
  234. } gpio_t;
  235. /* Watchdog registers
  236. */
  237. typedef struct wdog_ctrl {
  238. u16 wcr;
  239. u16 wmr;
  240. u16 wcntr;
  241. u16 wsr;
  242. u8 res4[114];
  243. } wdog_t;
  244. /* USB module registers
  245. */
  246. typedef struct usb {
  247. u16 res1;
  248. u16 fnr;
  249. u16 res2;
  250. u16 fnmr;
  251. u16 res3;
  252. u16 rfmr;
  253. u16 res4;
  254. u16 rfmmr;
  255. u8 res5[3];
  256. u8 far;
  257. u32 asr;
  258. u32 drr1;
  259. u32 drr2;
  260. u16 res6;
  261. u16 specr;
  262. u16 res7;
  263. u16 ep0sr;
  264. u32 iep0cfg;
  265. u32 oep0cfg;
  266. u32 ep1cfg;
  267. u32 ep2cfg;
  268. u32 ep3cfg;
  269. u32 ep4cfg;
  270. u32 ep5cfg;
  271. u32 ep6cfg;
  272. u32 ep7cfg;
  273. u32 ep0ctl;
  274. u16 res8;
  275. u16 ep1ctl;
  276. u16 res9;
  277. u16 ep2ctl;
  278. u16 res10;
  279. u16 ep3ctl;
  280. u16 res11;
  281. u16 ep4ctl;
  282. u16 res12;
  283. u16 ep5ctl;
  284. u16 res13;
  285. u16 ep6ctl;
  286. u16 res14;
  287. u16 ep7ctl;
  288. u32 ep0isr;
  289. u16 res15;
  290. u16 ep1isr;
  291. u16 res16;
  292. u16 ep2isr;
  293. u16 res17;
  294. u16 ep3isr;
  295. u16 res18;
  296. u16 ep4isr;
  297. u16 res19;
  298. u16 ep5isr;
  299. u16 res20;
  300. u16 ep6isr;
  301. u16 res21;
  302. u16 ep7isr;
  303. u32 ep0imr;
  304. u16 res22;
  305. u16 ep1imr;
  306. u16 res23;
  307. u16 ep2imr;
  308. u16 res24;
  309. u16 ep3imr;
  310. u16 res25;
  311. u16 ep4imr;
  312. u16 res26;
  313. u16 ep5imr;
  314. u16 res27;
  315. u16 ep6imr;
  316. u16 res28;
  317. u16 ep7imr;
  318. u32 ep0dr;
  319. u32 ep1dr;
  320. u32 ep2dr;
  321. u32 ep3dr;
  322. u32 ep4dr;
  323. u32 ep5dr;
  324. u32 ep6dr;
  325. u32 ep7dr;
  326. u16 res29;
  327. u16 ep0dpr;
  328. u16 res30;
  329. u16 ep1dpr;
  330. u16 res31;
  331. u16 ep2dpr;
  332. u16 res32;
  333. u16 ep3dpr;
  334. u16 res33;
  335. u16 ep4dpr;
  336. u16 res34;
  337. u16 ep5dpr;
  338. u16 res35;
  339. u16 ep6dpr;
  340. u16 res36;
  341. u16 ep7dpr;
  342. u8 res37[788];
  343. u8 cfgram[1024];
  344. } usb_t;
  345. /* PLL module registers
  346. */
  347. typedef struct pll_ctrl {
  348. u32 syncr;
  349. u32 synsr;
  350. } pll_t;
  351. typedef struct rcm {
  352. u8 rcr;
  353. u8 rsr;
  354. } rcm_t;
  355. #endif /* __IMMAP_5275__ */