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  1. /*
  2. * armboot - Startup Code for ARM920 CPU-core
  3. *
  4. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  5. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  6. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <asm-offsets.h>
  27. #include <config.h>
  28. #include <version.h>
  29. /*
  30. *************************************************************************
  31. *
  32. * Jump vector table as in table 3.1 in [1]
  33. *
  34. *************************************************************************
  35. */
  36. .globl _start
  37. _start: b reset
  38. ldr pc, _undefined_instruction
  39. ldr pc, _software_interrupt
  40. ldr pc, _prefetch_abort
  41. ldr pc, _data_abort
  42. ldr pc, _not_used
  43. ldr pc, _irq
  44. ldr pc, _fiq
  45. _undefined_instruction: .word undefined_instruction
  46. _software_interrupt: .word software_interrupt
  47. _prefetch_abort: .word prefetch_abort
  48. _data_abort: .word data_abort
  49. _not_used: .word not_used
  50. _irq: .word irq
  51. _fiq: .word fiq
  52. .balignl 16,0xdeadbeef
  53. /*
  54. *************************************************************************
  55. *
  56. * Startup Code (reset vector)
  57. *
  58. * do important init only if we don't start from memory!
  59. * relocate armboot to ram
  60. * setup stack
  61. * jump to second stage
  62. *
  63. *************************************************************************
  64. */
  65. .globl _TEXT_BASE
  66. _TEXT_BASE:
  67. .word CONFIG_SYS_TEXT_BASE
  68. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  69. .globl _armboot_start
  70. _armboot_start:
  71. .word _start
  72. #endif
  73. /*
  74. * These are defined in the board-specific linker script.
  75. */
  76. .globl _bss_start
  77. _bss_start:
  78. .word __bss_start
  79. .globl _bss_end
  80. _bss_end:
  81. .word _end
  82. #ifdef CONFIG_USE_IRQ
  83. /* IRQ stack memory (calculated at run-time) */
  84. .globl IRQ_STACK_START
  85. IRQ_STACK_START:
  86. .word 0x0badc0de
  87. /* IRQ stack memory (calculated at run-time) */
  88. .globl FIQ_STACK_START
  89. FIQ_STACK_START:
  90. .word 0x0badc0de
  91. #endif
  92. #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  93. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  94. .globl IRQ_STACK_START_IN
  95. IRQ_STACK_START_IN:
  96. .word 0x0badc0de
  97. .globl _datarel_start
  98. _datarel_start:
  99. .word __datarel_start
  100. .globl _datarelrolocal_start
  101. _datarelrolocal_start:
  102. .word __datarelrolocal_start
  103. .globl _datarellocal_start
  104. _datarellocal_start:
  105. .word __datarellocal_start
  106. .globl _datarelro_start
  107. _datarelro_start:
  108. .word __datarelro_start
  109. .globl _got_start
  110. _got_start:
  111. .word __got_start
  112. .globl _got_end
  113. _got_end:
  114. .word __got_end
  115. /*
  116. * the actual reset code
  117. */
  118. reset:
  119. /*
  120. * set the cpu to SVC32 mode
  121. */
  122. mrs r0,cpsr
  123. bic r0,r0,#0x1f
  124. orr r0,r0,#0xd3
  125. msr cpsr,r0
  126. #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
  127. #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
  128. #define pCLKSET 0x80000420 /* clock divisor register */
  129. /* disable watchdog, set watchdog control register to
  130. * all zeros (default reset)
  131. */
  132. ldr r0, =pWDTCTL
  133. mov r1, #0x0
  134. str r1, [r0]
  135. /*
  136. * mask all IRQs by setting all bits in the INTENC register (default)
  137. */
  138. mov r1, #0xffffffff
  139. ldr r0, =pINTENC
  140. str r1, [r0]
  141. /* FCLK:HCLK:PCLK = 1:2:2 */
  142. /* default FCLK is 200 MHz, using 14.7456 MHz fin */
  143. ldr r0, =pCLKSET
  144. ldr r1, =0x0004ee39
  145. @ ldr r1, =0x0005ee39 @ 1: 2: 4
  146. str r1, [r0]
  147. /*
  148. * we do sys-critical inits only at reboot,
  149. * not when booting from ram!
  150. */
  151. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  152. bl cpu_init_crit
  153. #endif
  154. /* Set stackpointer in internal RAM to call board_init_f */
  155. call_board_init_f:
  156. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  157. ldr r0,=0x00000000
  158. bl board_init_f
  159. /*------------------------------------------------------------------------------*/
  160. /*
  161. * void relocate_code (addr_sp, gd, addr_moni)
  162. *
  163. * This "function" does not return, instead it continues in RAM
  164. * after relocating the monitor code.
  165. *
  166. */
  167. .globl relocate_code
  168. relocate_code:
  169. mov r4, r0 /* save addr_sp */
  170. mov r5, r1 /* save addr of gd */
  171. mov r6, r2 /* save addr of destination */
  172. mov r7, r2 /* save addr of destination */
  173. /* Set up the stack */
  174. stack_setup:
  175. mov sp, r4
  176. adr r0, _start
  177. ldr r2, _TEXT_BASE
  178. ldr r3, _bss_start
  179. sub r2, r3, r2 /* r2 <- size of armboot */
  180. add r2, r0, r2 /* r2 <- source end address */
  181. cmp r0, r6
  182. beq clear_bss
  183. #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  184. copy_loop:
  185. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  186. stmia r6!, {r9-r10} /* copy to target address [r1] */
  187. cmp r0, r2 /* until source end address [r2] */
  188. blo copy_loop
  189. #ifndef CONFIG_PRELOADER
  190. /* fix got entries */
  191. ldr r1, _TEXT_BASE /* Text base */
  192. mov r0, r7 /* reloc addr */
  193. ldr r2, _got_start /* addr in Flash */
  194. ldr r3, _got_end /* addr in Flash */
  195. sub r3, r3, r1
  196. add r3, r3, r0
  197. sub r2, r2, r1
  198. add r2, r2, r0
  199. fixloop:
  200. ldr r4, [r2]
  201. sub r4, r4, r1
  202. add r4, r4, r0
  203. str r4, [r2]
  204. add r2, r2, #4
  205. cmp r2, r3
  206. bne fixloop
  207. #endif
  208. #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
  209. clear_bss:
  210. #ifndef CONFIG_PRELOADER
  211. ldr r0, _bss_start
  212. ldr r1, _bss_end
  213. ldr r3, _TEXT_BASE /* Text base */
  214. mov r4, r7 /* reloc addr */
  215. sub r0, r0, r3
  216. add r0, r0, r4
  217. sub r1, r1, r3
  218. add r1, r1, r4
  219. mov r2, #0x00000000 /* clear */
  220. clbss_l:str r2, [r0] /* clear loop... */
  221. add r0, r0, #4
  222. cmp r0, r1
  223. bne clbss_l
  224. #endif
  225. /*
  226. * We are done. Do not return, instead branch to second part of board
  227. * initialization, now running from RAM.
  228. */
  229. ldr r0, _TEXT_BASE
  230. ldr r2, _board_init_r
  231. sub r2, r2, r0
  232. add r2, r2, r7 /* position from board_init_r in RAM */
  233. /* setup parameters for board_init_r */
  234. mov r0, r5 /* gd_t */
  235. mov r1, r7 /* dest_addr */
  236. /* jump to it ... */
  237. mov lr, r2
  238. mov pc, lr
  239. _board_init_r: .word board_init_r
  240. #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
  241. /*
  242. * the actual reset code
  243. */
  244. reset:
  245. /*
  246. * set the cpu to SVC32 mode
  247. */
  248. mrs r0,cpsr
  249. bic r0,r0,#0x1f
  250. orr r0,r0,#0xd3
  251. msr cpsr,r0
  252. #define pWDTCTL 0x80001400 /* Watchdog Timer control register */
  253. #define pINTENC 0x8000050C /* Interupt-Controller enable clear register */
  254. #define pCLKSET 0x80000420 /* clock divisor register */
  255. /* disable watchdog, set watchdog control register to
  256. * all zeros (default reset)
  257. */
  258. ldr r0, =pWDTCTL
  259. mov r1, #0x0
  260. str r1, [r0]
  261. /*
  262. * mask all IRQs by setting all bits in the INTENC register (default)
  263. */
  264. mov r1, #0xffffffff
  265. ldr r0, =pINTENC
  266. str r1, [r0]
  267. /* FCLK:HCLK:PCLK = 1:2:2 */
  268. /* default FCLK is 200 MHz, using 14.7456 MHz fin */
  269. ldr r0, =pCLKSET
  270. ldr r1, =0x0004ee39
  271. @ ldr r1, =0x0005ee39 @ 1: 2: 4
  272. str r1, [r0]
  273. /*
  274. * we do sys-critical inits only at reboot,
  275. * not when booting from ram!
  276. */
  277. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  278. bl cpu_init_crit
  279. #endif
  280. #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  281. relocate: /* relocate U-Boot to RAM */
  282. adr r0, _start /* r0 <- current position of code */
  283. ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
  284. cmp r0, r1 /* don't reloc during debug */
  285. beq stack_setup
  286. ldr r2, _armboot_start
  287. ldr r3, _bss_start
  288. sub r2, r3, r2 /* r2 <- size of armboot */
  289. add r2, r0, r2 /* r2 <- source end address */
  290. copy_loop:
  291. ldmia r0!, {r3-r10} /* copy from source address [r0] */
  292. stmia r1!, {r3-r10} /* copy to target address [r1] */
  293. cmp r0, r2 /* until source end address [r2] */
  294. blo copy_loop
  295. #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
  296. /* Set up the stack */
  297. stack_setup:
  298. ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
  299. sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
  300. sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */
  301. #ifdef CONFIG_USE_IRQ
  302. sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
  303. #endif
  304. sub sp, r0, #12 /* leave 3 words for abort-stack */
  305. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  306. clear_bss:
  307. ldr r0, _bss_start /* find start of bss segment */
  308. @add r0, r0, #4 /* start at first byte of bss */
  309. /* why inc. 4 bytes past then? */
  310. ldr r1, _bss_end /* stop here */
  311. mov r2, #0x00000000 /* clear */
  312. clbss_l:str r2, [r0] /* clear loop... */
  313. add r0, r0, #4
  314. cmp r0, r1
  315. blo clbss_l
  316. ldr pc, _start_armboot
  317. _start_armboot: .word start_armboot
  318. #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
  319. /*
  320. *************************************************************************
  321. *
  322. * CPU_init_critical registers
  323. *
  324. * setup important registers
  325. * setup memory timing
  326. *
  327. *************************************************************************
  328. */
  329. cpu_init_crit:
  330. /*
  331. * flush v4 I/D caches
  332. */
  333. mov r0, #0
  334. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  335. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  336. /*
  337. * disable MMU stuff and caches
  338. */
  339. mrc p15, 0, r0, c1, c0, 0
  340. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  341. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  342. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  343. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  344. orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
  345. mcr p15, 0, r0, c1, c0, 0
  346. /*
  347. * before relocating, we have to setup RAM timing
  348. * because memory timing is board-dependend, you will
  349. * find a lowlevel_init.S in your board directory.
  350. */
  351. mov ip, lr
  352. bl lowlevel_init
  353. mov lr, ip
  354. mov pc, lr
  355. /*
  356. *************************************************************************
  357. *
  358. * Interrupt handling
  359. *
  360. *************************************************************************
  361. */
  362. @
  363. @ IRQ stack frame.
  364. @
  365. #define S_FRAME_SIZE 72
  366. #define S_OLD_R0 68
  367. #define S_PSR 64
  368. #define S_PC 60
  369. #define S_LR 56
  370. #define S_SP 52
  371. #define S_IP 48
  372. #define S_FP 44
  373. #define S_R10 40
  374. #define S_R9 36
  375. #define S_R8 32
  376. #define S_R7 28
  377. #define S_R6 24
  378. #define S_R5 20
  379. #define S_R4 16
  380. #define S_R3 12
  381. #define S_R2 8
  382. #define S_R1 4
  383. #define S_R0 0
  384. #define MODE_SVC 0x13
  385. #define I_BIT 0x80
  386. /*
  387. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  388. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  389. */
  390. .macro bad_save_user_regs
  391. sub sp, sp, #S_FRAME_SIZE
  392. stmia sp, {r0 - r12} @ Calling r0-r12
  393. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  394. ldr r2, _armboot_start
  395. sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
  396. sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
  397. #else
  398. ldr r2, IRQ_STACK_START_IN
  399. #endif
  400. ldmia r2, {r2 - r3} @ get pc, cpsr
  401. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  402. add r5, sp, #S_SP
  403. mov r1, lr
  404. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  405. mov r0, sp
  406. .endm
  407. .macro irq_save_user_regs
  408. sub sp, sp, #S_FRAME_SIZE
  409. stmia sp, {r0 - r12} @ Calling r0-r12
  410. add r8, sp, #S_PC
  411. stmdb r8, {sp, lr}^ @ Calling SP, LR
  412. str lr, [r8, #0] @ Save calling PC
  413. mrs r6, spsr
  414. str r6, [r8, #4] @ Save CPSR
  415. str r0, [r8, #8] @ Save OLD_R0
  416. mov r0, sp
  417. .endm
  418. .macro irq_restore_user_regs
  419. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  420. mov r0, r0
  421. ldr lr, [sp, #S_PC] @ Get PC
  422. add sp, sp, #S_FRAME_SIZE
  423. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  424. .endm
  425. .macro get_bad_stack
  426. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  427. ldr r13, _armboot_start @ setup our mode stack
  428. sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
  429. sub r13, r13, #(GENERATED_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
  430. #else
  431. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  432. #endif
  433. str lr, [r13] @ save caller lr / spsr
  434. mrs lr, spsr
  435. str lr, [r13, #4]
  436. mov r13, #MODE_SVC @ prepare SVC-Mode
  437. @ msr spsr_c, r13
  438. msr spsr, r13
  439. mov lr, pc
  440. movs pc, lr
  441. .endm
  442. .macro get_irq_stack @ setup IRQ stack
  443. ldr sp, IRQ_STACK_START
  444. .endm
  445. .macro get_fiq_stack @ setup FIQ stack
  446. ldr sp, FIQ_STACK_START
  447. .endm
  448. /*
  449. * exception handlers
  450. */
  451. .align 5
  452. undefined_instruction:
  453. get_bad_stack
  454. bad_save_user_regs
  455. bl do_undefined_instruction
  456. .align 5
  457. software_interrupt:
  458. get_bad_stack
  459. bad_save_user_regs
  460. bl do_software_interrupt
  461. .align 5
  462. prefetch_abort:
  463. get_bad_stack
  464. bad_save_user_regs
  465. bl do_prefetch_abort
  466. .align 5
  467. data_abort:
  468. get_bad_stack
  469. bad_save_user_regs
  470. bl do_data_abort
  471. .align 5
  472. not_used:
  473. get_bad_stack
  474. bad_save_user_regs
  475. bl do_not_used
  476. #ifdef CONFIG_USE_IRQ
  477. .align 5
  478. irq:
  479. get_irq_stack
  480. irq_save_user_regs
  481. bl do_irq
  482. irq_restore_user_regs
  483. .align 5
  484. fiq:
  485. get_fiq_stack
  486. /* someone ought to write a more effiction fiq_save_user_regs */
  487. irq_save_user_regs
  488. bl do_fiq
  489. irq_restore_user_regs
  490. #else
  491. .align 5
  492. irq:
  493. get_bad_stack
  494. bad_save_user_regs
  495. bl do_irq
  496. .align 5
  497. fiq:
  498. get_bad_stack
  499. bad_save_user_regs
  500. bl do_fiq
  501. #endif
  502. .align 5
  503. .globl reset_cpu
  504. reset_cpu:
  505. bl disable_interrupts
  506. /* Disable watchdog */
  507. ldr r1, =pWDTCTL
  508. mov r3, #0
  509. str r3, [r1]
  510. /* reset counter */
  511. ldr r3, =0x00001984
  512. str r3, [r1, #4]
  513. /* Enable the watchdog */
  514. mov r3, #1
  515. str r3, [r1]
  516. _loop_forever:
  517. b _loop_forever