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  1. /* vi: set ts=8 sw=8 noet: */
  2. /*
  3. * u-boot - Startup Code for XScale IXP
  4. *
  5. * Copyright (C) 2003 Kyle Harris <kharris@nexus-tech.net>
  6. *
  7. * Based on startup code example contained in the
  8. * Intel IXP4xx Programmer's Guide and past u-boot Start.S
  9. * samples.
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #include <asm-offsets.h>
  30. #include <config.h>
  31. #include <version.h>
  32. #include <asm/arch/ixp425.h>
  33. #define MMU_Control_M 0x001 /* Enable MMU */
  34. #define MMU_Control_A 0x002 /* Enable address alignment faults */
  35. #define MMU_Control_C 0x004 /* Enable cache */
  36. #define MMU_Control_W 0x008 /* Enable write-buffer */
  37. #define MMU_Control_P 0x010 /* Compatability: 32 bit code */
  38. #define MMU_Control_D 0x020 /* Compatability: 32 bit data */
  39. #define MMU_Control_L 0x040 /* Compatability: */
  40. #define MMU_Control_B 0x080 /* Enable Big-Endian */
  41. #define MMU_Control_S 0x100 /* Enable system protection */
  42. #define MMU_Control_R 0x200 /* Enable ROM protection */
  43. #define MMU_Control_I 0x1000 /* Enable Instruction cache */
  44. #define MMU_Control_X 0x2000 /* Set interrupt vectors at 0xFFFF0000 */
  45. #define MMU_Control_Init (MMU_Control_P|MMU_Control_D|MMU_Control_L)
  46. /*
  47. * Macro definitions
  48. */
  49. /* Delay a bit */
  50. .macro DELAY_FOR cycles, reg0
  51. ldr \reg0, =\cycles
  52. subs \reg0, \reg0, #1
  53. subne pc, pc, #0xc
  54. .endm
  55. /* wait for coprocessor write complete */
  56. .macro CPWAIT reg
  57. mrc p15,0,\reg,c2,c0,0
  58. mov \reg,\reg
  59. sub pc,pc,#4
  60. .endm
  61. .globl _start
  62. _start: b reset
  63. ldr pc, _undefined_instruction
  64. ldr pc, _software_interrupt
  65. ldr pc, _prefetch_abort
  66. ldr pc, _data_abort
  67. ldr pc, _not_used
  68. ldr pc, _irq
  69. ldr pc, _fiq
  70. _undefined_instruction: .word undefined_instruction
  71. _software_interrupt: .word software_interrupt
  72. _prefetch_abort: .word prefetch_abort
  73. _data_abort: .word data_abort
  74. _not_used: .word not_used
  75. _irq: .word irq
  76. _fiq: .word fiq
  77. .balignl 16,0xdeadbeef
  78. /*
  79. * Startup Code (reset vector)
  80. *
  81. * do important init only if we don't start from memory!
  82. * - relocate armboot to ram
  83. * - setup stack
  84. * - jump to second stage
  85. */
  86. .globl _TEXT_BASE
  87. _TEXT_BASE:
  88. .word CONFIG_SYS_TEXT_BASE
  89. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  90. .globl _armboot_start
  91. _armboot_start:
  92. .word _start
  93. #endif
  94. /*
  95. * These are defined in the board-specific linker script.
  96. */
  97. .globl _bss_start
  98. _bss_start:
  99. .word __bss_start
  100. .globl _bss_end
  101. _bss_end:
  102. .word _end
  103. #ifdef CONFIG_USE_IRQ
  104. /* IRQ stack memory (calculated at run-time) */
  105. .globl IRQ_STACK_START
  106. IRQ_STACK_START:
  107. .word 0x0badc0de
  108. /* IRQ stack memory (calculated at run-time) */
  109. .globl FIQ_STACK_START
  110. FIQ_STACK_START:
  111. .word 0x0badc0de
  112. #endif
  113. #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  114. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  115. .globl IRQ_STACK_START_IN
  116. IRQ_STACK_START_IN:
  117. .word 0x0badc0de
  118. .globl _datarel_start
  119. _datarel_start:
  120. .word __datarel_start
  121. .globl _datarelrolocal_start
  122. _datarelrolocal_start:
  123. .word __datarelrolocal_start
  124. .globl _datarellocal_start
  125. _datarellocal_start:
  126. .word __datarellocal_start
  127. .globl _datarelro_start
  128. _datarelro_start:
  129. .word __datarelro_start
  130. .globl _got_start
  131. _got_start:
  132. .word __got_start
  133. .globl _got_end
  134. _got_end:
  135. .word __got_end
  136. /*
  137. * the actual reset code
  138. */
  139. reset:
  140. /* disable mmu, set big-endian */
  141. mov r0, #0xf8
  142. mcr p15, 0, r0, c1, c0, 0
  143. CPWAIT r0
  144. /* invalidate I & D caches & BTB */
  145. mcr p15, 0, r0, c7, c7, 0
  146. CPWAIT r0
  147. /* invalidate I & Data TLB */
  148. mcr p15, 0, r0, c8, c7, 0
  149. CPWAIT r0
  150. /* drain write and fill buffers */
  151. mcr p15, 0, r0, c7, c10, 4
  152. CPWAIT r0
  153. /* disable write buffer coalescing */
  154. mrc p15, 0, r0, c1, c0, 1
  155. orr r0, r0, #1
  156. mcr p15, 0, r0, c1, c0, 1
  157. CPWAIT r0
  158. /* set EXP CS0 to the optimum timing */
  159. ldr r1, =CONFIG_SYS_EXP_CS0
  160. ldr r2, =IXP425_EXP_CS0
  161. str r1, [r2]
  162. /* make sure flash is visible at 0 */
  163. #if 0
  164. ldr r2, =IXP425_EXP_CFG0
  165. ldr r1, [r2]
  166. orr r1, r1, #0x80000000
  167. str r1, [r2]
  168. #endif
  169. mov r1, #CONFIG_SYS_SDR_CONFIG
  170. ldr r2, =IXP425_SDR_CONFIG
  171. str r1, [r2]
  172. /* disable refresh cycles */
  173. mov r1, #0
  174. ldr r3, =IXP425_SDR_REFRESH
  175. str r1, [r3]
  176. /* send nop command */
  177. mov r1, #3
  178. ldr r4, =IXP425_SDR_IR
  179. str r1, [r4]
  180. DELAY_FOR 0x4000, r0
  181. /* set SDRAM internal refresh val */
  182. ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
  183. str r1, [r3]
  184. DELAY_FOR 0x4000, r0
  185. /* send precharge-all command to close all open banks */
  186. mov r1, #2
  187. str r1, [r4]
  188. DELAY_FOR 0x4000, r0
  189. /* provide 8 auto-refresh cycles */
  190. mov r1, #4
  191. mov r5, #8
  192. 111: str r1, [r4]
  193. DELAY_FOR 0x100, r0
  194. subs r5, r5, #1
  195. bne 111b
  196. /* set mode register in sdram */
  197. mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
  198. str r1, [r4]
  199. DELAY_FOR 0x4000, r0
  200. /* send normal operation command */
  201. mov r1, #6
  202. str r1, [r4]
  203. DELAY_FOR 0x4000, r0
  204. /* copy */
  205. mov r0, #0
  206. mov r4, r0
  207. add r2, r0, #CONFIG_SYS_MONITOR_LEN
  208. mov r1, #0x10000000
  209. mov r5, r1
  210. 30:
  211. ldr r3, [r0], #4
  212. str r3, [r1], #4
  213. cmp r0, r2
  214. bne 30b
  215. /* invalidate I & D caches & BTB */
  216. mcr p15, 0, r0, c7, c7, 0
  217. CPWAIT r0
  218. /* invalidate I & Data TLB */
  219. mcr p15, 0, r0, c8, c7, 0
  220. CPWAIT r0
  221. /* drain write and fill buffers */
  222. mcr p15, 0, r0, c7, c10, 4
  223. CPWAIT r0
  224. /* move flash to 0x50000000 */
  225. ldr r2, =IXP425_EXP_CFG0
  226. ldr r1, [r2]
  227. bic r1, r1, #0x80000000
  228. str r1, [r2]
  229. nop
  230. nop
  231. nop
  232. nop
  233. nop
  234. nop
  235. /* invalidate I & Data TLB */
  236. mcr p15, 0, r0, c8, c7, 0
  237. CPWAIT r0
  238. /* enable I cache */
  239. mrc p15, 0, r0, c1, c0, 0
  240. orr r0, r0, #MMU_Control_I
  241. mcr p15, 0, r0, c1, c0, 0
  242. CPWAIT r0
  243. mrs r0,cpsr /* set the cpu to SVC32 mode */
  244. bic r0,r0,#0x1f /* (superviser mode, M=10011) */
  245. orr r0,r0,#0x13
  246. msr cpsr,r0
  247. /* Set stackpointer in internal RAM to call board_init_f */
  248. call_board_init_f:
  249. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  250. ldr r0,=0x00000000
  251. bl board_init_f
  252. /*------------------------------------------------------------------------------*/
  253. /*
  254. * void relocate_code (addr_sp, gd, addr_moni)
  255. *
  256. * This "function" does not return, instead it continues in RAM
  257. * after relocating the monitor code.
  258. *
  259. */
  260. .globl relocate_code
  261. relocate_code:
  262. mov r4, r0 /* save addr_sp */
  263. mov r5, r1 /* save addr of gd */
  264. mov r6, r2 /* save addr of destination */
  265. mov r7, r2 /* save addr of destination */
  266. /* Set up the stack */
  267. stack_setup:
  268. mov sp, r4
  269. adr r0, _start
  270. ldr r2, _TEXT_BASE
  271. ldr r3, _bss_start
  272. sub r2, r3, r2 /* r2 <- size of armboot */
  273. add r2, r0, r2 /* r2 <- source end address */
  274. cmp r0, r6
  275. beq clear_bss
  276. #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  277. copy_loop:
  278. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  279. stmia r6!, {r9-r10} /* copy to target address [r1] */
  280. cmp r0, r2 /* until source end address [r2] */
  281. blo copy_loop
  282. #ifndef CONFIG_PRELOADER
  283. /* fix got entries */
  284. ldr r1, _TEXT_BASE /* Text base */
  285. mov r0, r7 /* reloc addr */
  286. ldr r2, _got_start /* addr in Flash */
  287. ldr r3, _got_end /* addr in Flash */
  288. sub r3, r3, r1
  289. add r3, r3, r0
  290. sub r2, r2, r1
  291. add r2, r2, r0
  292. fixloop:
  293. ldr r4, [r2]
  294. sub r4, r4, r1
  295. add r4, r4, r0
  296. str r4, [r2]
  297. add r2, r2, #4
  298. cmp r2, r3
  299. bne fixloop
  300. #endif
  301. #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
  302. clear_bss:
  303. #ifndef CONFIG_PRELOADER
  304. ldr r0, _bss_start
  305. ldr r1, _bss_end
  306. ldr r3, _TEXT_BASE /* Text base */
  307. mov r4, r7 /* reloc addr */
  308. sub r0, r0, r3
  309. add r0, r0, r4
  310. sub r1, r1, r3
  311. add r1, r1, r4
  312. mov r2, #0x00000000 /* clear */
  313. clbss_l:str r2, [r0] /* clear loop... */
  314. add r0, r0, #4
  315. cmp r0, r1
  316. bne clbss_l
  317. bl coloured_LED_init
  318. bl red_LED_on
  319. #endif
  320. /*
  321. * We are done. Do not return, instead branch to second part of board
  322. * initialization, now running from RAM.
  323. */
  324. ldr r0, _TEXT_BASE
  325. ldr r2, _board_init_r
  326. sub r2, r2, r0
  327. add r2, r2, r7 /* position from board_init_r in RAM */
  328. /* setup parameters for board_init_r */
  329. mov r0, r5 /* gd_t */
  330. mov r1, r7 /* dest_addr */
  331. /* jump to it ... */
  332. mov lr, r2
  333. mov pc, lr
  334. _board_init_r: .word board_init_r
  335. #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
  336. /****************************************************************************/
  337. /* */
  338. /* the actual reset code */
  339. /* */
  340. /****************************************************************************/
  341. reset:
  342. /* disable mmu, set big-endian */
  343. mov r0, #0xf8
  344. mcr p15, 0, r0, c1, c0, 0
  345. CPWAIT r0
  346. /* invalidate I & D caches & BTB */
  347. mcr p15, 0, r0, c7, c7, 0
  348. CPWAIT r0
  349. /* invalidate I & Data TLB */
  350. mcr p15, 0, r0, c8, c7, 0
  351. CPWAIT r0
  352. /* drain write and fill buffers */
  353. mcr p15, 0, r0, c7, c10, 4
  354. CPWAIT r0
  355. /* disable write buffer coalescing */
  356. mrc p15, 0, r0, c1, c0, 1
  357. orr r0, r0, #1
  358. mcr p15, 0, r0, c1, c0, 1
  359. CPWAIT r0
  360. /* set EXP CS0 to the optimum timing */
  361. ldr r1, =CONFIG_SYS_EXP_CS0
  362. ldr r2, =IXP425_EXP_CS0
  363. str r1, [r2]
  364. /* make sure flash is visible at 0 */
  365. #if 0
  366. ldr r2, =IXP425_EXP_CFG0
  367. ldr r1, [r2]
  368. orr r1, r1, #0x80000000
  369. str r1, [r2]
  370. #endif
  371. mov r1, #CONFIG_SYS_SDR_CONFIG
  372. ldr r2, =IXP425_SDR_CONFIG
  373. str r1, [r2]
  374. /* disable refresh cycles */
  375. mov r1, #0
  376. ldr r3, =IXP425_SDR_REFRESH
  377. str r1, [r3]
  378. /* send nop command */
  379. mov r1, #3
  380. ldr r4, =IXP425_SDR_IR
  381. str r1, [r4]
  382. DELAY_FOR 0x4000, r0
  383. /* set SDRAM internal refresh val */
  384. ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT
  385. str r1, [r3]
  386. DELAY_FOR 0x4000, r0
  387. /* send precharge-all command to close all open banks */
  388. mov r1, #2
  389. str r1, [r4]
  390. DELAY_FOR 0x4000, r0
  391. /* provide 8 auto-refresh cycles */
  392. mov r1, #4
  393. mov r5, #8
  394. 111: str r1, [r4]
  395. DELAY_FOR 0x100, r0
  396. subs r5, r5, #1
  397. bne 111b
  398. /* set mode register in sdram */
  399. mov r1, #CONFIG_SYS_SDR_MODE_CONFIG
  400. str r1, [r4]
  401. DELAY_FOR 0x4000, r0
  402. /* send normal operation command */
  403. mov r1, #6
  404. str r1, [r4]
  405. DELAY_FOR 0x4000, r0
  406. /* copy */
  407. mov r0, #0
  408. mov r4, r0
  409. add r2, r0, #CONFIG_SYS_MONITOR_LEN
  410. mov r1, #0x10000000
  411. mov r5, r1
  412. 30:
  413. ldr r3, [r0], #4
  414. str r3, [r1], #4
  415. cmp r0, r2
  416. bne 30b
  417. /* invalidate I & D caches & BTB */
  418. mcr p15, 0, r0, c7, c7, 0
  419. CPWAIT r0
  420. /* invalidate I & Data TLB */
  421. mcr p15, 0, r0, c8, c7, 0
  422. CPWAIT r0
  423. /* drain write and fill buffers */
  424. mcr p15, 0, r0, c7, c10, 4
  425. CPWAIT r0
  426. /* move flash to 0x50000000 */
  427. ldr r2, =IXP425_EXP_CFG0
  428. ldr r1, [r2]
  429. bic r1, r1, #0x80000000
  430. str r1, [r2]
  431. nop
  432. nop
  433. nop
  434. nop
  435. nop
  436. nop
  437. /* invalidate I & Data TLB */
  438. mcr p15, 0, r0, c8, c7, 0
  439. CPWAIT r0
  440. /* enable I cache */
  441. mrc p15, 0, r0, c1, c0, 0
  442. orr r0, r0, #MMU_Control_I
  443. mcr p15, 0, r0, c1, c0, 0
  444. CPWAIT r0
  445. mrs r0,cpsr /* set the cpu to SVC32 mode */
  446. bic r0,r0,#0x1f /* (superviser mode, M=10011) */
  447. orr r0,r0,#0x13
  448. msr cpsr,r0
  449. #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  450. relocate: /* relocate U-Boot to RAM */
  451. adr r0, _start /* r0 <- current position of code */
  452. ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
  453. cmp r0, r1 /* don't reloc during debug */
  454. beq stack_setup
  455. ldr r2, _armboot_start
  456. ldr r3, _bss_start
  457. sub r2, r3, r2 /* r2 <- size of armboot */
  458. add r2, r0, r2 /* r2 <- source end address */
  459. copy_loop:
  460. ldmia r0!, {r3-r10} /* copy from source address [r0] */
  461. stmia r1!, {r3-r10} /* copy to target address [r1] */
  462. cmp r0, r2 /* until source end address [r2] */
  463. blo copy_loop
  464. #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
  465. /* Set up the stack */
  466. stack_setup:
  467. ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
  468. sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
  469. sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */
  470. #ifdef CONFIG_USE_IRQ
  471. sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
  472. #endif
  473. sub sp, r0, #12 /* leave 3 words for abort-stack */
  474. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  475. clear_bss:
  476. ldr r0, _bss_start /* find start of bss segment */
  477. ldr r1, _bss_end /* stop here */
  478. mov r2, #0x00000000 /* clear */
  479. clbss_l:str r2, [r0] /* clear loop... */
  480. add r0, r0, #4
  481. cmp r0, r1
  482. blo clbss_l
  483. ldr pc, _start_armboot
  484. _start_armboot: .word start_armboot
  485. #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
  486. /****************************************************************************/
  487. /* */
  488. /* Interrupt handling */
  489. /* */
  490. /****************************************************************************/
  491. /* IRQ stack frame */
  492. #define S_FRAME_SIZE 72
  493. #define S_OLD_R0 68
  494. #define S_PSR 64
  495. #define S_PC 60
  496. #define S_LR 56
  497. #define S_SP 52
  498. #define S_IP 48
  499. #define S_FP 44
  500. #define S_R10 40
  501. #define S_R9 36
  502. #define S_R8 32
  503. #define S_R7 28
  504. #define S_R6 24
  505. #define S_R5 20
  506. #define S_R4 16
  507. #define S_R3 12
  508. #define S_R2 8
  509. #define S_R1 4
  510. #define S_R0 0
  511. #define MODE_SVC 0x13
  512. /* use bad_save_user_regs for abort/prefetch/undef/swi ... */
  513. .macro bad_save_user_regs
  514. sub sp, sp, #S_FRAME_SIZE
  515. stmia sp, {r0 - r12} /* Calling r0-r12 */
  516. add r8, sp, #S_PC
  517. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  518. ldr r2, _armboot_start
  519. sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
  520. sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
  521. #else
  522. ldr r2, IRQ_STACK_START_IN
  523. #endif
  524. ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */
  525. add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */
  526. add r5, sp, #S_SP
  527. mov r1, lr
  528. stmia r5, {r0 - r4} /* save sp_SVC, lr_SVC, pc, cpsr, old_r */
  529. mov r0, sp
  530. .endm
  531. /* use irq_save_user_regs / irq_restore_user_regs for */
  532. /* IRQ/FIQ handling */
  533. .macro irq_save_user_regs
  534. sub sp, sp, #S_FRAME_SIZE
  535. stmia sp, {r0 - r12} /* Calling r0-r12 */
  536. add r8, sp, #S_PC
  537. stmdb r8, {sp, lr}^ /* Calling SP, LR */
  538. str lr, [r8, #0] /* Save calling PC */
  539. mrs r6, spsr
  540. str r6, [r8, #4] /* Save CPSR */
  541. str r0, [r8, #8] /* Save OLD_R0 */
  542. mov r0, sp
  543. .endm
  544. .macro irq_restore_user_regs
  545. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  546. mov r0, r0
  547. ldr lr, [sp, #S_PC] @ Get PC
  548. add sp, sp, #S_FRAME_SIZE
  549. subs pc, lr, #4 @ return & move spsr_svc into cpsr
  550. .endm
  551. .macro get_bad_stack
  552. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  553. ldr r13, _armboot_start @ setup our mode stack
  554. sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
  555. sub r13, r13, #(GENERATED_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
  556. #else
  557. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  558. #endif
  559. str lr, [r13] @ save caller lr / spsr
  560. mrs lr, spsr
  561. str lr, [r13, #4]
  562. mov r13, #MODE_SVC @ prepare SVC-Mode
  563. msr spsr_c, r13
  564. mov lr, pc
  565. movs pc, lr
  566. .endm
  567. .macro get_irq_stack @ setup IRQ stack
  568. ldr sp, IRQ_STACK_START
  569. .endm
  570. .macro get_fiq_stack @ setup FIQ stack
  571. ldr sp, FIQ_STACK_START
  572. .endm
  573. /****************************************************************************/
  574. /* */
  575. /* exception handlers */
  576. /* */
  577. /****************************************************************************/
  578. .align 5
  579. undefined_instruction:
  580. get_bad_stack
  581. bad_save_user_regs
  582. bl do_undefined_instruction
  583. .align 5
  584. software_interrupt:
  585. get_bad_stack
  586. bad_save_user_regs
  587. bl do_software_interrupt
  588. .align 5
  589. prefetch_abort:
  590. get_bad_stack
  591. bad_save_user_regs
  592. bl do_prefetch_abort
  593. .align 5
  594. data_abort:
  595. get_bad_stack
  596. bad_save_user_regs
  597. bl do_data_abort
  598. .align 5
  599. not_used:
  600. get_bad_stack
  601. bad_save_user_regs
  602. bl do_not_used
  603. #ifdef CONFIG_USE_IRQ
  604. .align 5
  605. irq:
  606. get_irq_stack
  607. irq_save_user_regs
  608. bl do_irq
  609. irq_restore_user_regs
  610. .align 5
  611. fiq:
  612. get_fiq_stack
  613. irq_save_user_regs /* someone ought to write a more */
  614. bl do_fiq /* effiction fiq_save_user_regs */
  615. irq_restore_user_regs
  616. #else
  617. .align 5
  618. irq:
  619. get_bad_stack
  620. bad_save_user_regs
  621. bl do_irq
  622. .align 5
  623. fiq:
  624. get_bad_stack
  625. bad_save_user_regs
  626. bl do_fiq
  627. #endif
  628. /****************************************************************************/
  629. /* */
  630. /* Reset function: Use Watchdog to reset */
  631. /* */
  632. /****************************************************************************/
  633. .align 5
  634. .globl reset_cpu
  635. reset_cpu:
  636. ldr r1, =0x482e
  637. ldr r2, =IXP425_OSWK
  638. str r1, [r2]
  639. ldr r1, =0x0fff
  640. ldr r2, =IXP425_OSWT
  641. str r1, [r2]
  642. ldr r1, =0x5
  643. ldr r2, =IXP425_OSWE
  644. str r1, [r2]
  645. b reset_endless
  646. reset_endless:
  647. b reset_endless
  648. #ifdef CONFIG_USE_IRQ
  649. .LC0: .word loops_per_jiffy
  650. /*
  651. * 0 <= r0 <= 2000
  652. */
  653. .globl __udelay
  654. __udelay:
  655. mov r2, #0x6800
  656. orr r2, r2, #0x00db
  657. mul r0, r2, r0
  658. ldr r2, .LC0
  659. ldr r2, [r2] @ max = 0x0fffffff
  660. mov r0, r0, lsr #11 @ max = 0x00003fff
  661. mov r2, r2, lsr #11 @ max = 0x0003ffff
  662. mul r0, r2, r0 @ max = 2^32-1
  663. movs r0, r0, lsr #6
  664. delay_loop:
  665. subs r0, r0, #1
  666. bne delay_loop
  667. mov pc, lr
  668. #endif /* CONFIG_USE_IRQ */