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  1. /*
  2. * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core
  3. *
  4. * Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
  5. *
  6. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  7. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  8. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  9. * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
  10. * Copyright (c) 2003 Kshitij <kshitij@ti.com>
  11. * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim@ti.com>
  12. *
  13. * See file CREDITS for list of people who contributed to this
  14. * project.
  15. *
  16. * This program is free software; you can redistribute it and/or
  17. * modify it under the terms of the GNU General Public License as
  18. * published by the Free Software Foundation; either version 2 of
  19. * the License, or (at your option) any later version.
  20. *
  21. * This program is distributed in the hope that it will be useful,
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24. * GNU General Public License for more details.
  25. *
  26. * You should have received a copy of the GNU General Public License
  27. * along with this program; if not, write to the Free Software
  28. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  29. * MA 02111-1307 USA
  30. */
  31. #include <asm-offsets.h>
  32. #include <config.h>
  33. #include <version.h>
  34. .globl _start
  35. _start: b reset
  36. ldr pc, _undefined_instruction
  37. ldr pc, _software_interrupt
  38. ldr pc, _prefetch_abort
  39. ldr pc, _data_abort
  40. ldr pc, _not_used
  41. ldr pc, _irq
  42. ldr pc, _fiq
  43. _undefined_instruction: .word undefined_instruction
  44. _software_interrupt: .word software_interrupt
  45. _prefetch_abort: .word prefetch_abort
  46. _data_abort: .word data_abort
  47. _not_used: .word not_used
  48. _irq: .word irq
  49. _fiq: .word fiq
  50. _pad: .word 0x12345678 /* now 16*4=64 */
  51. .global _end_vect
  52. _end_vect:
  53. .balignl 16,0xdeadbeef
  54. /*************************************************************************
  55. *
  56. * Startup Code (reset vector)
  57. *
  58. * do important init only if we don't start from memory!
  59. * setup Memory and board specific bits prior to relocation.
  60. * relocate armboot to ram
  61. * setup stack
  62. *
  63. *************************************************************************/
  64. .globl _TEXT_BASE
  65. _TEXT_BASE:
  66. .word CONFIG_SYS_TEXT_BASE
  67. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  68. .globl _armboot_start
  69. _armboot_start:
  70. .word _start
  71. #endif
  72. /*
  73. * These are defined in the board-specific linker script.
  74. */
  75. .globl _bss_start_ofs
  76. _bss_start_ofs:
  77. .word __bss_start - _start
  78. .globl _bss_end_ofs
  79. _bss_end_ofs:
  80. .word _end - _start
  81. #ifdef CONFIG_USE_IRQ
  82. /* IRQ stack memory (calculated at run-time) */
  83. .globl IRQ_STACK_START
  84. IRQ_STACK_START:
  85. .word 0x0badc0de
  86. /* IRQ stack memory (calculated at run-time) */
  87. .globl FIQ_STACK_START
  88. FIQ_STACK_START:
  89. .word 0x0badc0de
  90. #endif
  91. #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  92. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  93. .globl IRQ_STACK_START_IN
  94. IRQ_STACK_START_IN:
  95. .word 0x0badc0de
  96. .globl _datarel_start_ofs
  97. _datarel_start_ofs:
  98. .word __datarel_start - _start
  99. .globl _datarelrolocal_start_ofs
  100. _datarelrolocal_start_ofs:
  101. .word __datarelrolocal_start - _start
  102. .globl _datarellocal_start_ofs
  103. _datarellocal_start_ofs:
  104. .word __datarellocal_start - _start
  105. .globl _datarelro_start_ofs
  106. _datarelro_start_ofs:
  107. .word __datarelro_start - _start
  108. .globl _got_start_ofs
  109. _got_start_ofs:
  110. .word __got_start - _start
  111. .globl _got_end_Ofs
  112. _got_end_ofs:
  113. .word __got_end - _start
  114. /*
  115. * the actual reset code
  116. */
  117. reset:
  118. /*
  119. * set the cpu to SVC32 mode
  120. */
  121. mrs r0, cpsr
  122. bic r0, r0, #0x1f
  123. orr r0, r0, #0xd3
  124. msr cpsr,r0
  125. #if (CONFIG_OMAP34XX)
  126. /* Copy vectors to mask ROM indirect addr */
  127. adr r0, _start @ r0 <- current position of code
  128. add r0, r0, #4 @ skip reset vector
  129. mov r2, #64 @ r2 <- size to copy
  130. add r2, r0, r2 @ r2 <- source end address
  131. mov r1, #SRAM_OFFSET0 @ build vect addr
  132. mov r3, #SRAM_OFFSET1
  133. add r1, r1, r3
  134. mov r3, #SRAM_OFFSET2
  135. add r1, r1, r3
  136. next:
  137. ldmia r0!, {r3 - r10} @ copy from source address [r0]
  138. stmia r1!, {r3 - r10} @ copy to target address [r1]
  139. cmp r0, r2 @ until source end address [r2]
  140. bne next @ loop until equal */
  141. #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
  142. /* No need to copy/exec the clock code - DPLL adjust already done
  143. * in NAND/oneNAND Boot.
  144. */
  145. bl cpy_clk_code @ put dpll adjust code behind vectors
  146. #endif /* NAND Boot */
  147. #endif
  148. /* the mask ROM code should have PLL and others stable */
  149. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  150. bl cpu_init_crit
  151. #endif
  152. /* Set stackpointer in internal RAM to call board_init_f */
  153. call_board_init_f:
  154. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  155. ldr r0,=0x00000000
  156. bl board_init_f
  157. /*------------------------------------------------------------------------------*/
  158. /*
  159. * void relocate_code (addr_sp, gd, addr_moni)
  160. *
  161. * This "function" does not return, instead it continues in RAM
  162. * after relocating the monitor code.
  163. *
  164. */
  165. .globl relocate_code
  166. relocate_code:
  167. mov r4, r0 /* save addr_sp */
  168. mov r5, r1 /* save addr of gd */
  169. mov r6, r2 /* save addr of destination */
  170. mov r7, r2 /* save addr of destination */
  171. /* Set up the stack */
  172. stack_setup:
  173. mov sp, r4
  174. #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  175. adr r0, _start
  176. ldr r2, _TEXT_BASE
  177. ldr r3, _bss_start_ofs
  178. add r2, r0, r3 /* r2 <- source end address */
  179. cmp r0, r6
  180. #ifndef CONFIG_PRELOADER
  181. beq jump_2_ram
  182. #endif
  183. copy_loop:
  184. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  185. stmia r6!, {r9-r10} /* copy to target address [r1] */
  186. cmp r0, r2 /* until source end address [r2] */
  187. blo copy_loop
  188. #ifndef CONFIG_PRELOADER
  189. /*
  190. * fix .rel.dyn relocations
  191. */
  192. ldr r0, _TEXT_BASE /* r0 <- Text base */
  193. sub r9, r7, r0 /* r9 <- relocation offset */
  194. ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
  195. add r10, r10, r0 /* r10 <- sym table in FLASH */
  196. ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
  197. add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
  198. ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
  199. add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
  200. fixloop:
  201. ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
  202. add r0, r0, r9 /* r0 <- location to fix up in RAM */
  203. ldr r1, [r2, #4]
  204. and r8, r1, #0xff
  205. cmp r8, #23 /* relative fixup? */
  206. beq fixrel
  207. cmp r8, #2 /* absolute fixup? */
  208. beq fixabs
  209. /* ignore unknown type of fixup */
  210. b fixnext
  211. fixabs:
  212. /* absolute fix: set location to (offset) symbol value */
  213. mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
  214. add r1, r10, r1 /* r1 <- address of symbol in table */
  215. ldr r1, [r1, #4] /* r1 <- symbol value */
  216. add r1, r9 /* r1 <- relocated sym addr */
  217. b fixnext
  218. fixrel:
  219. /* relative fix: increase location by offset */
  220. ldr r1, [r0]
  221. add r1, r1, r9
  222. fixnext:
  223. str r1, [r0]
  224. add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
  225. cmp r2, r3
  226. blo fixloop
  227. clear_bss:
  228. ldr r0, _bss_start_ofs
  229. ldr r1, _bss_end_ofs
  230. ldr r3, _TEXT_BASE /* Text base */
  231. mov r4, r7 /* reloc addr */
  232. add r0, r0, r4
  233. add r1, r1, r4
  234. mov r2, #0x00000000 /* clear */
  235. clbss_l:str r2, [r0] /* clear loop... */
  236. add r0, r0, #4
  237. cmp r0, r1
  238. bne clbss_l
  239. #endif /* #ifndef CONFIG_PRELOADER */
  240. #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
  241. /*
  242. * We are done. Do not return, instead branch to second part of board
  243. * initialization, now running from RAM.
  244. */
  245. jump_2_ram:
  246. ldr r0, _board_init_r_ofs
  247. adr r1, _start
  248. add r0, r0, r1
  249. add lr, r0, r9
  250. /* setup parameters for board_init_r */
  251. mov r0, r5 /* gd_t */
  252. mov r1, r7 /* dest_addr */
  253. /* jump to it ... */
  254. mov pc, lr
  255. _board_init_r_ofs:
  256. .word board_init_r - _start
  257. _rel_dyn_start_ofs:
  258. .word __rel_dyn_start - _start
  259. _rel_dyn_end_ofs:
  260. .word __rel_dyn_end - _start
  261. _dynsym_start_ofs:
  262. .word __dynsym_start - _start
  263. #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
  264. /*
  265. * the actual reset code
  266. */
  267. reset:
  268. /*
  269. * set the cpu to SVC32 mode
  270. */
  271. mrs r0, cpsr
  272. bic r0, r0, #0x1f
  273. orr r0, r0, #0xd3
  274. msr cpsr,r0
  275. #if (CONFIG_OMAP34XX)
  276. /* Copy vectors to mask ROM indirect addr */
  277. adr r0, _start @ r0 <- current position of code
  278. add r0, r0, #4 @ skip reset vector
  279. mov r2, #64 @ r2 <- size to copy
  280. add r2, r0, r2 @ r2 <- source end address
  281. mov r1, #SRAM_OFFSET0 @ build vect addr
  282. mov r3, #SRAM_OFFSET1
  283. add r1, r1, r3
  284. mov r3, #SRAM_OFFSET2
  285. add r1, r1, r3
  286. next:
  287. ldmia r0!, {r3 - r10} @ copy from source address [r0]
  288. stmia r1!, {r3 - r10} @ copy to target address [r1]
  289. cmp r0, r2 @ until source end address [r2]
  290. bne next @ loop until equal */
  291. #if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT)
  292. /* No need to copy/exec the clock code - DPLL adjust already done
  293. * in NAND/oneNAND Boot.
  294. */
  295. bl cpy_clk_code @ put dpll adjust code behind vectors
  296. #endif /* NAND Boot */
  297. #endif
  298. /* the mask ROM code should have PLL and others stable */
  299. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  300. bl cpu_init_crit
  301. #endif
  302. #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  303. relocate: @ relocate U-Boot to RAM
  304. adr r0, _start @ r0 <- current position of code
  305. ldr r1, _TEXT_BASE @ test if we run from flash or RAM
  306. cmp r0, r1 @ don't reloc during debug
  307. beq stack_setup
  308. ldr r2, _armboot_start
  309. ldr r3, _bss_start
  310. sub r2, r3, r2 @ r2 <- size of armboot
  311. add r2, r0, r2 @ r2 <- source end address
  312. copy_loop: @ copy 32 bytes at a time
  313. ldmia r0!, {r3 - r10} @ copy from source address [r0]
  314. stmia r1!, {r3 - r10} @ copy to target address [r1]
  315. cmp r0, r2 @ until source end address [r2]
  316. blo copy_loop
  317. #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
  318. /* Set up the stack */
  319. stack_setup:
  320. ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot
  321. sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area
  322. sub r0, r0, #GENERATED_GBL_DATA_SIZE @ bdinfo
  323. #ifdef CONFIG_USE_IRQ
  324. sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ)
  325. #endif
  326. sub sp, r0, #12 @ leave 3 words for abort-stack
  327. bic sp, sp, #7 @ 8-byte alignment for ABI compliance
  328. /* Clear BSS (if any). Is below tx (watch load addr - need space) */
  329. clear_bss:
  330. ldr r0, _bss_start @ find start of bss segment
  331. ldr r1, _bss_end @ stop here
  332. mov r2, #0x00000000 @ clear value
  333. clbss_l:
  334. str r2, [r0] @ clear BSS location
  335. cmp r0, r1 @ are we at the end yet
  336. add r0, r0, #4 @ increment clear index pointer
  337. bne clbss_l @ keep clearing till at end
  338. ldr pc, _start_armboot @ jump to C code
  339. _start_armboot: .word start_armboot
  340. #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
  341. /*************************************************************************
  342. *
  343. * CPU_init_critical registers
  344. *
  345. * setup important registers
  346. * setup memory timing
  347. *
  348. *************************************************************************/
  349. cpu_init_crit:
  350. /*
  351. * Invalidate L1 I/D
  352. */
  353. mov r0, #0 @ set up for MCR
  354. mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
  355. mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
  356. /*
  357. * disable MMU stuff and caches
  358. */
  359. mrc p15, 0, r0, c1, c0, 0
  360. bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
  361. bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
  362. orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
  363. orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB
  364. mcr p15, 0, r0, c1, c0, 0
  365. /*
  366. * Jump to board specific initialization...
  367. * The Mask ROM will have already initialized
  368. * basic memory. Go here to bump up clock rate and handle
  369. * wake up conditions.
  370. */
  371. mov ip, lr @ persevere link reg across call
  372. bl lowlevel_init @ go setup pll,mux,memory
  373. mov lr, ip @ restore link
  374. mov pc, lr @ back to my caller
  375. /*
  376. *************************************************************************
  377. *
  378. * Interrupt handling
  379. *
  380. *************************************************************************
  381. */
  382. @
  383. @ IRQ stack frame.
  384. @
  385. #define S_FRAME_SIZE 72
  386. #define S_OLD_R0 68
  387. #define S_PSR 64
  388. #define S_PC 60
  389. #define S_LR 56
  390. #define S_SP 52
  391. #define S_IP 48
  392. #define S_FP 44
  393. #define S_R10 40
  394. #define S_R9 36
  395. #define S_R8 32
  396. #define S_R7 28
  397. #define S_R6 24
  398. #define S_R5 20
  399. #define S_R4 16
  400. #define S_R3 12
  401. #define S_R2 8
  402. #define S_R1 4
  403. #define S_R0 0
  404. #define MODE_SVC 0x13
  405. #define I_BIT 0x80
  406. /*
  407. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  408. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  409. */
  410. .macro bad_save_user_regs
  411. sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current
  412. @ user stack
  413. stmia sp, {r0 - r12} @ Save user registers (now in
  414. @ svc mode) r0-r12
  415. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  416. ldr r2, _armboot_start
  417. sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
  418. sub r2, r2, #(GENERATED_GBL_DATA_SIZE + 8) @ set base 2 words into abort
  419. #else
  420. ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort
  421. @ stack
  422. #endif
  423. ldmia r2, {r2 - r3} @ get values for "aborted" pc
  424. @ and cpsr (into parm regs)
  425. add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
  426. add r5, sp, #S_SP
  427. mov r1, lr
  428. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  429. mov r0, sp @ save current stack into r0
  430. @ (param register)
  431. .endm
  432. .macro irq_save_user_regs
  433. sub sp, sp, #S_FRAME_SIZE
  434. stmia sp, {r0 - r12} @ Calling r0-r12
  435. add r8, sp, #S_PC @ !! R8 NEEDS to be saved !!
  436. @ a reserved stack spot would
  437. @ be good.
  438. stmdb r8, {sp, lr}^ @ Calling SP, LR
  439. str lr, [r8, #0] @ Save calling PC
  440. mrs r6, spsr
  441. str r6, [r8, #4] @ Save CPSR
  442. str r0, [r8, #8] @ Save OLD_R0
  443. mov r0, sp
  444. .endm
  445. .macro irq_restore_user_regs
  446. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  447. mov r0, r0
  448. ldr lr, [sp, #S_PC] @ Get PC
  449. add sp, sp, #S_FRAME_SIZE
  450. subs pc, lr, #4 @ return & move spsr_svc into
  451. @ cpsr
  452. .endm
  453. .macro get_bad_stack
  454. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  455. ldr r13, _armboot_start @ setup our mode stack (enter
  456. sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
  457. sub r13, r13, #(GENERATED_GBL_DATA_SIZE + 8) @ move to reserved a couple
  458. #else
  459. ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter
  460. @ in banked mode)
  461. #endif
  462. str lr, [r13] @ save caller lr in position 0
  463. @ of saved stack
  464. mrs lr, spsr @ get the spsr
  465. str lr, [r13, #4] @ save spsr in position 1 of
  466. @ saved stack
  467. mov r13, #MODE_SVC @ prepare SVC-Mode
  468. @ msr spsr_c, r13
  469. msr spsr, r13 @ switch modes, make sure
  470. @ moves will execute
  471. mov lr, pc @ capture return pc
  472. movs pc, lr @ jump to next instruction &
  473. @ switch modes.
  474. .endm
  475. .macro get_bad_stack_swi
  476. sub r13, r13, #4 @ space on current stack for
  477. @ scratch reg.
  478. str r0, [r13] @ save R0's value.
  479. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  480. ldr r0, _armboot_start @ get data regions start
  481. sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool
  482. sub r0, r0, #(GENERATED_GBL_DATA_SIZE + 8) @ move past gbl and a couple
  483. #else
  484. ldr r0, IRQ_STACK_START_IN @ get data regions start
  485. @ spots for abort stack
  486. #endif
  487. str lr, [r0] @ save caller lr in position 0
  488. @ of saved stack
  489. mrs r0, spsr @ get the spsr
  490. str lr, [r0, #4] @ save spsr in position 1 of
  491. @ saved stack
  492. ldr r0, [r13] @ restore r0
  493. add r13, r13, #4 @ pop stack entry
  494. .endm
  495. .macro get_irq_stack @ setup IRQ stack
  496. ldr sp, IRQ_STACK_START
  497. .endm
  498. .macro get_fiq_stack @ setup FIQ stack
  499. ldr sp, FIQ_STACK_START
  500. .endm
  501. /*
  502. * exception handlers
  503. */
  504. .align 5
  505. undefined_instruction:
  506. get_bad_stack
  507. bad_save_user_regs
  508. bl do_undefined_instruction
  509. .align 5
  510. software_interrupt:
  511. get_bad_stack_swi
  512. bad_save_user_regs
  513. bl do_software_interrupt
  514. .align 5
  515. prefetch_abort:
  516. get_bad_stack
  517. bad_save_user_regs
  518. bl do_prefetch_abort
  519. .align 5
  520. data_abort:
  521. get_bad_stack
  522. bad_save_user_regs
  523. bl do_data_abort
  524. .align 5
  525. not_used:
  526. get_bad_stack
  527. bad_save_user_regs
  528. bl do_not_used
  529. #ifdef CONFIG_USE_IRQ
  530. .align 5
  531. irq:
  532. get_irq_stack
  533. irq_save_user_regs
  534. bl do_irq
  535. irq_restore_user_regs
  536. .align 5
  537. fiq:
  538. get_fiq_stack
  539. /* someone ought to write a more effective fiq_save_user_regs */
  540. irq_save_user_regs
  541. bl do_fiq
  542. irq_restore_user_regs
  543. #else
  544. .align 5
  545. irq:
  546. get_bad_stack
  547. bad_save_user_regs
  548. bl do_irq
  549. .align 5
  550. fiq:
  551. get_bad_stack
  552. bad_save_user_regs
  553. bl do_fiq
  554. #endif