start.S 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661
  1. /*
  2. * armboot - Startup Code for ARM920 CPU-core
  3. *
  4. * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
  5. * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
  6. * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. #include <asm-offsets.h>
  27. #include <common.h>
  28. #include <config.h>
  29. /*
  30. *************************************************************************
  31. *
  32. * Jump vector table as in table 3.1 in [1]
  33. *
  34. *************************************************************************
  35. */
  36. .globl _start
  37. _start: b start_code
  38. ldr pc, _undefined_instruction
  39. ldr pc, _software_interrupt
  40. ldr pc, _prefetch_abort
  41. ldr pc, _data_abort
  42. ldr pc, _not_used
  43. ldr pc, _irq
  44. ldr pc, _fiq
  45. _undefined_instruction: .word undefined_instruction
  46. _software_interrupt: .word software_interrupt
  47. _prefetch_abort: .word prefetch_abort
  48. _data_abort: .word data_abort
  49. _not_used: .word not_used
  50. _irq: .word irq
  51. _fiq: .word fiq
  52. .balignl 16,0xdeadbeef
  53. /*
  54. *************************************************************************
  55. *
  56. * Startup Code (called from the ARM reset exception vector)
  57. *
  58. * do important init only if we don't start from memory!
  59. * relocate armboot to ram
  60. * setup stack
  61. * jump to second stage
  62. *
  63. *************************************************************************
  64. */
  65. .globl _TEXT_BASE
  66. _TEXT_BASE:
  67. .word CONFIG_SYS_TEXT_BASE
  68. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  69. .globl _armboot_start
  70. _armboot_start:
  71. .word _start
  72. #endif
  73. /*
  74. * These are defined in the board-specific linker script.
  75. */
  76. .globl _bss_start
  77. _bss_start:
  78. .word __bss_start
  79. .globl _bss_end
  80. _bss_end:
  81. .word _end
  82. #ifdef CONFIG_USE_IRQ
  83. /* IRQ stack memory (calculated at run-time) */
  84. .globl IRQ_STACK_START
  85. IRQ_STACK_START:
  86. .word 0x0badc0de
  87. /* IRQ stack memory (calculated at run-time) */
  88. .globl FIQ_STACK_START
  89. FIQ_STACK_START:
  90. .word 0x0badc0de
  91. #endif
  92. #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  93. /* IRQ stack memory (calculated at run-time) + 8 bytes */
  94. .globl IRQ_STACK_START_IN
  95. IRQ_STACK_START_IN:
  96. .word 0x0badc0de
  97. .globl _datarel_start
  98. _datarel_start:
  99. .word __datarel_start
  100. .globl _datarelrolocal_start
  101. _datarelrolocal_start:
  102. .word __datarelrolocal_start
  103. .globl _datarellocal_start
  104. _datarellocal_start:
  105. .word __datarellocal_start
  106. .globl _datarelro_start
  107. _datarelro_start:
  108. .word __datarelro_start
  109. .globl _got_start
  110. _got_start:
  111. .word __got_start
  112. .globl _got_end
  113. _got_end:
  114. .word __got_end
  115. /*
  116. * the actual start code
  117. */
  118. start_code:
  119. /*
  120. * set the cpu to SVC32 mode
  121. */
  122. mrs r0, cpsr
  123. bic r0, r0, #0x1f
  124. orr r0, r0, #0xd3
  125. msr cpsr, r0
  126. bl coloured_LED_init
  127. bl red_LED_on
  128. #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  129. /*
  130. * relocate exception table
  131. */
  132. ldr r0, =_start
  133. ldr r1, =0x0
  134. mov r2, #16
  135. copyex:
  136. subs r2, r2, #1
  137. ldr r3, [r0], #4
  138. str r3, [r1], #4
  139. bne copyex
  140. #endif
  141. #ifdef CONFIG_S3C24X0
  142. /* turn off the watchdog */
  143. # if defined(CONFIG_S3C2400)
  144. # define pWTCON 0x15300000
  145. # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
  146. # define CLKDIVN 0x14800014 /* clock divisor register */
  147. #else
  148. # define pWTCON 0x53000000
  149. # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
  150. # define INTSUBMSK 0x4A00001C
  151. # define CLKDIVN 0x4C000014 /* clock divisor register */
  152. # endif
  153. ldr r0, =pWTCON
  154. mov r1, #0x0
  155. str r1, [r0]
  156. /*
  157. * mask all IRQs by setting all bits in the INTMR - default
  158. */
  159. mov r1, #0xffffffff
  160. ldr r0, =INTMSK
  161. str r1, [r0]
  162. # if defined(CONFIG_S3C2410)
  163. ldr r1, =0x3ff
  164. ldr r0, =INTSUBMSK
  165. str r1, [r0]
  166. # endif
  167. /* FCLK:HCLK:PCLK = 1:2:4 */
  168. /* default FCLK is 120 MHz ! */
  169. ldr r0, =CLKDIVN
  170. mov r1, #3
  171. str r1, [r0]
  172. #endif /* CONFIG_S3C24X0 */
  173. /*
  174. * we do sys-critical inits only at reboot,
  175. * not when booting from ram!
  176. */
  177. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  178. bl cpu_init_crit
  179. #endif
  180. /* Set stackpointer in internal RAM to call board_init_f */
  181. call_board_init_f:
  182. ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
  183. ldr r0,=0x00000000
  184. bl board_init_f
  185. /*------------------------------------------------------------------------------*/
  186. /*
  187. * void relocate_code (addr_sp, gd, addr_moni)
  188. *
  189. * This "function" does not return, instead it continues in RAM
  190. * after relocating the monitor code.
  191. *
  192. */
  193. .globl relocate_code
  194. relocate_code:
  195. mov r4, r0 /* save addr_sp */
  196. mov r5, r1 /* save addr of gd */
  197. mov r6, r2 /* save addr of destination */
  198. mov r7, r2 /* save addr of destination */
  199. /* Set up the stack */
  200. stack_setup:
  201. mov sp, r4
  202. adr r0, _start
  203. ldr r2, _TEXT_BASE
  204. ldr r3, _bss_start
  205. sub r2, r3, r2 /* r2 <- size of armboot */
  206. add r2, r0, r2 /* r2 <- source end address */
  207. cmp r0, r6
  208. beq clear_bss
  209. #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  210. copy_loop:
  211. ldmia r0!, {r9-r10} /* copy from source address [r0] */
  212. stmia r6!, {r9-r10} /* copy to target address [r1] */
  213. cmp r0, r2 /* until source end address [r2] */
  214. blo copy_loop
  215. #ifndef CONFIG_PRELOADER
  216. /* fix got entries */
  217. ldr r1, _TEXT_BASE /* Text base */
  218. mov r0, r7 /* reloc addr */
  219. ldr r2, _got_start /* addr in Flash */
  220. ldr r3, _got_end /* addr in Flash */
  221. sub r3, r3, r1
  222. add r3, r3, r0
  223. sub r2, r2, r1
  224. add r2, r2, r0
  225. fixloop:
  226. ldr r4, [r2]
  227. sub r4, r4, r1
  228. add r4, r4, r0
  229. str r4, [r2]
  230. add r2, r2, #4
  231. cmp r2, r3
  232. bne fixloop
  233. #endif
  234. #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */
  235. clear_bss:
  236. #ifndef CONFIG_PRELOADER
  237. ldr r0, _bss_start
  238. ldr r1, _bss_end
  239. ldr r3, _TEXT_BASE /* Text base */
  240. mov r4, r7 /* reloc addr */
  241. sub r0, r0, r3
  242. add r0, r0, r4
  243. sub r1, r1, r3
  244. add r1, r1, r4
  245. mov r2, #0x00000000 /* clear */
  246. clbss_l:str r2, [r0] /* clear loop... */
  247. add r0, r0, #4
  248. cmp r0, r1
  249. bne clbss_l
  250. bl coloured_LED_init
  251. bl red_LED_on
  252. #endif
  253. /*
  254. * We are done. Do not return, instead branch to second part of board
  255. * initialization, now running from RAM.
  256. */
  257. #ifdef CONFIG_NAND_SPL
  258. ldr pc, _nand_boot
  259. _nand_boot: .word nand_boot
  260. #else
  261. ldr r0, _TEXT_BASE
  262. ldr r2, _board_init_r
  263. sub r2, r2, r0
  264. add r2, r2, r7 /* position from board_init_r in RAM */
  265. /* setup parameters for board_init_r */
  266. mov r0, r5 /* gd_t */
  267. mov r1, r7 /* dest_addr */
  268. /* jump to it ... */
  269. mov lr, r2
  270. mov pc, lr
  271. _board_init_r: .word board_init_r
  272. #endif
  273. #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
  274. /*
  275. * the actual start code
  276. */
  277. start_code:
  278. /*
  279. * set the cpu to SVC32 mode
  280. */
  281. mrs r0, cpsr
  282. bic r0, r0, #0x1f
  283. orr r0, r0, #0xd3
  284. msr cpsr, r0
  285. bl coloured_LED_init
  286. bl red_LED_on
  287. #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
  288. /*
  289. * relocate exception table
  290. */
  291. ldr r0, =_start
  292. ldr r1, =0x0
  293. mov r2, #16
  294. copyex:
  295. subs r2, r2, #1
  296. ldr r3, [r0], #4
  297. str r3, [r1], #4
  298. bne copyex
  299. #endif
  300. #ifdef CONFIG_S3C24X0
  301. /* turn off the watchdog */
  302. # if defined(CONFIG_S3C2400)
  303. # define pWTCON 0x15300000
  304. # define INTMSK 0x14400008 /* Interupt-Controller base addresses */
  305. # define CLKDIVN 0x14800014 /* clock divisor register */
  306. #else
  307. # define pWTCON 0x53000000
  308. # define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
  309. # define INTSUBMSK 0x4A00001C
  310. # define CLKDIVN 0x4C000014 /* clock divisor register */
  311. # endif
  312. ldr r0, =pWTCON
  313. mov r1, #0x0
  314. str r1, [r0]
  315. /*
  316. * mask all IRQs by setting all bits in the INTMR - default
  317. */
  318. mov r1, #0xffffffff
  319. ldr r0, =INTMSK
  320. str r1, [r0]
  321. # if defined(CONFIG_S3C2410)
  322. ldr r1, =0x3ff
  323. ldr r0, =INTSUBMSK
  324. str r1, [r0]
  325. # endif
  326. /* FCLK:HCLK:PCLK = 1:2:4 */
  327. /* default FCLK is 120 MHz ! */
  328. ldr r0, =CLKDIVN
  329. mov r1, #3
  330. str r1, [r0]
  331. #endif /* CONFIG_S3C24X0 */
  332. /*
  333. * we do sys-critical inits only at reboot,
  334. * not when booting from ram!
  335. */
  336. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  337. bl cpu_init_crit
  338. #endif
  339. #ifndef CONFIG_SKIP_RELOCATE_UBOOT
  340. relocate: /* relocate U-Boot to RAM */
  341. adr r0, _start /* r0 <- current position of code */
  342. ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
  343. cmp r0, r1 /* don't reloc during debug */
  344. beq stack_setup
  345. ldr r2, _armboot_start
  346. ldr r3, _bss_start
  347. sub r2, r3, r2 /* r2 <- size of armboot */
  348. add r2, r0, r2 /* r2 <- source end address */
  349. copy_loop:
  350. ldmia r0!, {r3-r10} /* copy from source address [r0] */
  351. stmia r1!, {r3-r10} /* copy to target address [r1] */
  352. cmp r0, r2 /* until source end address [r2] */
  353. blo copy_loop
  354. #endif /* CONFIG_SKIP_RELOCATE_UBOOT */
  355. /* Set up the stack */
  356. stack_setup:
  357. ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
  358. sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
  359. sub r0, r0, #GENERATED_GBL_DATA_SIZE /* bdinfo */
  360. #ifdef CONFIG_USE_IRQ
  361. sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
  362. #endif
  363. sub sp, r0, #12 /* leave 3 words for abort-stack */
  364. bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
  365. clear_bss:
  366. ldr r0, _bss_start /* find start of bss segment */
  367. ldr r1, _bss_end /* stop here */
  368. mov r2, #0x00000000 /* clear */
  369. clbss_l:str r2, [r0] /* clear loop... */
  370. add r0, r0, #4
  371. cmp r0, r1
  372. blo clbss_l
  373. ldr pc, _start_armboot
  374. _start_armboot: .word start_armboot
  375. #endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */
  376. /*
  377. *************************************************************************
  378. *
  379. * CPU_init_critical registers
  380. *
  381. * setup important registers
  382. * setup memory timing
  383. *
  384. *************************************************************************
  385. */
  386. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  387. cpu_init_crit:
  388. /*
  389. * flush v4 I/D caches
  390. */
  391. mov r0, #0
  392. mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
  393. mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
  394. /*
  395. * disable MMU stuff and caches
  396. */
  397. mrc p15, 0, r0, c1, c0, 0
  398. bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
  399. bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
  400. orr r0, r0, #0x00000002 @ set bit 2 (A) Align
  401. orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
  402. mcr p15, 0, r0, c1, c0, 0
  403. /*
  404. * before relocating, we have to setup RAM timing
  405. * because memory timing is board-dependend, you will
  406. * find a lowlevel_init.S in your board directory.
  407. */
  408. mov ip, lr
  409. bl lowlevel_init
  410. mov lr, ip
  411. mov pc, lr
  412. #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  413. /*
  414. *************************************************************************
  415. *
  416. * Interrupt handling
  417. *
  418. *************************************************************************
  419. */
  420. @
  421. @ IRQ stack frame.
  422. @
  423. #define S_FRAME_SIZE 72
  424. #define S_OLD_R0 68
  425. #define S_PSR 64
  426. #define S_PC 60
  427. #define S_LR 56
  428. #define S_SP 52
  429. #define S_IP 48
  430. #define S_FP 44
  431. #define S_R10 40
  432. #define S_R9 36
  433. #define S_R8 32
  434. #define S_R7 28
  435. #define S_R6 24
  436. #define S_R5 20
  437. #define S_R4 16
  438. #define S_R3 12
  439. #define S_R2 8
  440. #define S_R1 4
  441. #define S_R0 0
  442. #define MODE_SVC 0x13
  443. #define I_BIT 0x80
  444. /*
  445. * use bad_save_user_regs for abort/prefetch/undef/swi ...
  446. * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
  447. */
  448. .macro bad_save_user_regs
  449. sub sp, sp, #S_FRAME_SIZE
  450. stmia sp, {r0 - r12} @ Calling r0-r12
  451. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  452. ldr r2, _armboot_start
  453. sub r2, r2, #(CONFIG_STACKSIZE)
  454. sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
  455. /* set base 2 words into abort stack */
  456. sub r2, r2, #(GENERATED_GBL_DATA_SIZE+8)
  457. #else
  458. ldr r2, IRQ_STACK_START_IN
  459. #endif
  460. ldmia r2, {r2 - r3} @ get pc, cpsr
  461. add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
  462. add r5, sp, #S_SP
  463. mov r1, lr
  464. stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
  465. mov r0, sp
  466. .endm
  467. .macro irq_save_user_regs
  468. sub sp, sp, #S_FRAME_SIZE
  469. stmia sp, {r0 - r12} @ Calling r0-r12
  470. add r7, sp, #S_PC
  471. stmdb r7, {sp, lr}^ @ Calling SP, LR
  472. str lr, [r7, #0] @ Save calling PC
  473. mrs r6, spsr
  474. str r6, [r7, #4] @ Save CPSR
  475. str r0, [r7, #8] @ Save OLD_R0
  476. mov r0, sp
  477. .endm
  478. .macro irq_restore_user_regs
  479. ldmia sp, {r0 - lr}^ @ Calling r0 - lr
  480. mov r0, r0
  481. ldr lr, [sp, #S_PC] @ Get PC
  482. add sp, sp, #S_FRAME_SIZE
  483. /* return & move spsr_svc into cpsr */
  484. subs pc, lr, #4
  485. .endm
  486. .macro get_bad_stack
  487. #if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
  488. ldr r13, _armboot_start @ setup our mode stack
  489. sub r13, r13, #(CONFIG_STACKSIZE)
  490. sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
  491. /* reserve a couple spots in abort stack */
  492. sub r13, r13, #(GENERATED_GBL_DATA_SIZE+8)
  493. #else
  494. ldr r13, IRQ_STACK_START_IN @ setup our mode stack
  495. #endif
  496. str lr, [r13] @ save caller lr / spsr
  497. mrs lr, spsr
  498. str lr, [r13, #4]
  499. mov r13, #MODE_SVC @ prepare SVC-Mode
  500. @ msr spsr_c, r13
  501. msr spsr, r13
  502. mov lr, pc
  503. movs pc, lr
  504. .endm
  505. .macro get_irq_stack @ setup IRQ stack
  506. ldr sp, IRQ_STACK_START
  507. .endm
  508. .macro get_fiq_stack @ setup FIQ stack
  509. ldr sp, FIQ_STACK_START
  510. .endm
  511. /*
  512. * exception handlers
  513. */
  514. .align 5
  515. undefined_instruction:
  516. get_bad_stack
  517. bad_save_user_regs
  518. bl do_undefined_instruction
  519. .align 5
  520. software_interrupt:
  521. get_bad_stack
  522. bad_save_user_regs
  523. bl do_software_interrupt
  524. .align 5
  525. prefetch_abort:
  526. get_bad_stack
  527. bad_save_user_regs
  528. bl do_prefetch_abort
  529. .align 5
  530. data_abort:
  531. get_bad_stack
  532. bad_save_user_regs
  533. bl do_data_abort
  534. .align 5
  535. not_used:
  536. get_bad_stack
  537. bad_save_user_regs
  538. bl do_not_used
  539. #ifdef CONFIG_USE_IRQ
  540. .align 5
  541. irq:
  542. get_irq_stack
  543. irq_save_user_regs
  544. bl do_irq
  545. irq_restore_user_regs
  546. .align 5
  547. fiq:
  548. get_fiq_stack
  549. /* someone ought to write a more effiction fiq_save_user_regs */
  550. irq_save_user_regs
  551. bl do_fiq
  552. irq_restore_user_regs
  553. #else
  554. .align 5
  555. irq:
  556. get_bad_stack
  557. bad_save_user_regs
  558. bl do_irq
  559. .align 5
  560. fiq:
  561. get_bad_stack
  562. bad_save_user_regs
  563. bl do_fiq
  564. #endif