timer.c 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. #include <common.h>
  7. #include <init.h>
  8. #include <time.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/hardware.h>
  11. #include <asm/arch/spr_gpt.h>
  12. #include <asm/arch/spr_misc.h>
  13. #include <asm/ptrace.h>
  14. #define GPT_RESOLUTION (CONFIG_SPEAR_HZ_CLOCK / CONFIG_SPEAR_HZ)
  15. #define READ_TIMER() (readl(&gpt_regs_p->count) & GPT_FREE_RUNNING)
  16. static struct gpt_regs *const gpt_regs_p =
  17. (struct gpt_regs *)CONFIG_SPEAR_TIMERBASE;
  18. static struct misc_regs *const misc_regs_p =
  19. (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  20. DECLARE_GLOBAL_DATA_PTR;
  21. static ulong get_timer_masked(void);
  22. #define timestamp gd->arch.tbl
  23. #define lastdec gd->arch.lastinc
  24. int timer_init(void)
  25. {
  26. u32 synth;
  27. /* Prescaler setting */
  28. #if defined(CONFIG_SPEAR3XX)
  29. writel(MISC_PRSC_CFG, &misc_regs_p->prsc2_clk_cfg);
  30. synth = MISC_GPT4SYNTH;
  31. #elif defined(CONFIG_SPEAR600)
  32. writel(MISC_PRSC_CFG, &misc_regs_p->prsc1_clk_cfg);
  33. synth = MISC_GPT3SYNTH;
  34. #else
  35. # error Incorrect config. Can only be SPEAR{600|300|310|320}
  36. #endif
  37. writel(readl(&misc_regs_p->periph_clk_cfg) | synth,
  38. &misc_regs_p->periph_clk_cfg);
  39. /* disable timers */
  40. writel(GPT_PRESCALER_1 | GPT_MODE_AUTO_RELOAD, &gpt_regs_p->control);
  41. /* load value for free running */
  42. writel(GPT_FREE_RUNNING, &gpt_regs_p->compare);
  43. /* auto reload, start timer */
  44. writel(readl(&gpt_regs_p->control) | GPT_ENABLE, &gpt_regs_p->control);
  45. /* Reset the timer */
  46. lastdec = READ_TIMER();
  47. timestamp = 0;
  48. return 0;
  49. }
  50. /*
  51. * timer without interrupts
  52. */
  53. ulong get_timer(ulong base)
  54. {
  55. return (get_timer_masked() / GPT_RESOLUTION) - base;
  56. }
  57. void __udelay(unsigned long usec)
  58. {
  59. ulong tmo;
  60. ulong start = get_timer_masked();
  61. ulong tenudelcnt = CONFIG_SPEAR_HZ_CLOCK / (1000 * 100);
  62. ulong rndoff;
  63. rndoff = (usec % 10) ? 1 : 0;
  64. /* tenudelcnt timer tick gives 10 microsecconds delay */
  65. tmo = ((usec / 10) + rndoff) * tenudelcnt;
  66. while ((ulong) (get_timer_masked() - start) < tmo)
  67. ;
  68. }
  69. static ulong get_timer_masked(void)
  70. {
  71. ulong now = READ_TIMER();
  72. if (now >= lastdec) {
  73. /* normal mode */
  74. timestamp += now - lastdec;
  75. } else {
  76. /* we have an overflow ... */
  77. timestamp += now + GPT_FREE_RUNNING - lastdec;
  78. }
  79. lastdec = now;
  80. return timestamp;
  81. }
  82. /*
  83. * This function is derived from PowerPC code (read timebase as long long).
  84. * On ARM it just returns the timer value.
  85. */
  86. unsigned long long get_ticks(void)
  87. {
  88. return get_timer(0);
  89. }
  90. /*
  91. * This function is derived from PowerPC code (timebase clock frequency).
  92. * On ARM it returns the number of timer ticks per second.
  93. */
  94. ulong get_tbclk(void)
  95. {
  96. return CONFIG_SPEAR_HZ;
  97. }