spl.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011
  4. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  5. *
  6. * Copyright (C) 2012 Stefan Roese <sr@denx.de>
  7. */
  8. #include <common.h>
  9. #include <init.h>
  10. #include <spl.h>
  11. #include <version.h>
  12. #include <asm/io.h>
  13. #include <asm/ptrace.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/spr_defs.h>
  16. #include <asm/arch/spr_misc.h>
  17. #include <asm/arch/spr_syscntl.h>
  18. #include <linux/mtd/st_smi.h>
  19. /* Reserve some space to store the BootROM's stack pointer during SPL operation.
  20. * The BSS cannot be used for this purpose because it will be zeroed after
  21. * having stored the pointer, so force the location to the data section.
  22. */
  23. u32 bootrom_stash_sp __attribute__((section(".data")));
  24. static void ddr_clock_init(void)
  25. {
  26. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  27. u32 clkenb, ddrpll;
  28. clkenb = readl(&misc_p->periph1_clken);
  29. clkenb &= ~PERIPH_MPMCMSK;
  30. clkenb |= PERIPH_MPMC_WE;
  31. /* Intentionally done twice */
  32. writel(clkenb, &misc_p->periph1_clken);
  33. writel(clkenb, &misc_p->periph1_clken);
  34. ddrpll = readl(&misc_p->pll_ctr_reg);
  35. ddrpll &= ~MEM_CLK_SEL_MSK;
  36. #if (CONFIG_DDR_HCLK)
  37. ddrpll |= MEM_CLK_HCLK;
  38. #elif (CONFIG_DDR_2HCLK)
  39. ddrpll |= MEM_CLK_2HCLK;
  40. #elif (CONFIG_DDR_PLL2)
  41. ddrpll |= MEM_CLK_PLL2;
  42. #else
  43. #error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
  44. #endif
  45. writel(ddrpll, &misc_p->pll_ctr_reg);
  46. writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
  47. &misc_p->periph1_clken);
  48. }
  49. static void mpmc_init_values(void)
  50. {
  51. u32 i;
  52. u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
  53. u32 *mpmc_val_p = &mpmc_conf_vals[0];
  54. for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
  55. writel(*mpmc_val_p, mpmc_reg_p);
  56. mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
  57. /*
  58. * MPMC controller start
  59. * MPMC waiting for DLLLOCKREG high
  60. */
  61. writel(0x01000100, &mpmc_reg_p[7]);
  62. while (!(readl(&mpmc_reg_p[3]) & 0x10000))
  63. ;
  64. }
  65. static void mpmc_init(void)
  66. {
  67. /* Clock related settings for DDR */
  68. ddr_clock_init();
  69. /*
  70. * DDR pad register bits are different for different SoCs
  71. * Compensation values are also handled separately
  72. */
  73. plat_ddr_init();
  74. /* Initialize mpmc register values */
  75. mpmc_init_values();
  76. }
  77. static void pll_init(void)
  78. {
  79. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  80. /* Initialize PLLs */
  81. writel(FREQ_332, &misc_p->pll1_frq);
  82. writel(0x1C0A, &misc_p->pll1_cntl);
  83. writel(0x1C0E, &misc_p->pll1_cntl);
  84. writel(0x1C06, &misc_p->pll1_cntl);
  85. writel(0x1C0E, &misc_p->pll1_cntl);
  86. writel(FREQ_332, &misc_p->pll2_frq);
  87. writel(0x1C0A, &misc_p->pll2_cntl);
  88. writel(0x1C0E, &misc_p->pll2_cntl);
  89. writel(0x1C06, &misc_p->pll2_cntl);
  90. writel(0x1C0E, &misc_p->pll2_cntl);
  91. /* wait for pll locks */
  92. while (!(readl(&misc_p->pll1_cntl) & 0x1))
  93. ;
  94. while (!(readl(&misc_p->pll2_cntl) & 0x1))
  95. ;
  96. }
  97. static void mac_init(void)
  98. {
  99. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  100. writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
  101. &misc_p->periph1_clken);
  102. writel(SYNTH23, &misc_p->gmac_synth_clk);
  103. switch (get_socrev()) {
  104. case SOC_SPEAR600_AA:
  105. case SOC_SPEAR600_AB:
  106. case SOC_SPEAR600_BA:
  107. case SOC_SPEAR600_BB:
  108. case SOC_SPEAR600_BC:
  109. case SOC_SPEAR600_BD:
  110. writel(0x0, &misc_p->gmac_ctr_reg);
  111. break;
  112. case SOC_SPEAR300:
  113. case SOC_SPEAR310:
  114. case SOC_SPEAR320:
  115. writel(0x4, &misc_p->gmac_ctr_reg);
  116. break;
  117. }
  118. writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
  119. &misc_p->periph1_clken);
  120. writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
  121. &misc_p->periph1_rst);
  122. writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
  123. &misc_p->periph1_rst);
  124. }
  125. static void sys_init(void)
  126. {
  127. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  128. struct syscntl_regs *syscntl_p =
  129. (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
  130. /* Set system state to SLOW */
  131. writel(SLOW, &syscntl_p->scctrl);
  132. writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
  133. /* Initialize PLLs */
  134. pll_init();
  135. /*
  136. * Ethernet configuration
  137. * To be done only if the tftp boot is not selected already
  138. * Boot code ensures the correct configuration in tftp booting
  139. */
  140. if (!tftp_boot_selected())
  141. mac_init();
  142. writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
  143. writel(0x555, &misc_p->amba_clk_cfg);
  144. writel(NORMAL, &syscntl_p->scctrl);
  145. /* Wait for system to switch to normal mode */
  146. while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
  147. != NORMAL)
  148. ;
  149. }
  150. /*
  151. * get_socrev
  152. *
  153. * Get SoC Revision.
  154. * @return SOC_SPEARXXX
  155. */
  156. int get_socrev(void)
  157. {
  158. #if defined(CONFIG_SPEAR600)
  159. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  160. u32 soc_id = readl(&misc_p->soc_core_id);
  161. u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
  162. u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
  163. if ((pri_socid == 'B') && (sec_socid == 'B'))
  164. return SOC_SPEAR600_BB;
  165. else if ((pri_socid == 'B') && (sec_socid == 'C'))
  166. return SOC_SPEAR600_BC;
  167. else if ((pri_socid == 'B') && (sec_socid == 'D'))
  168. return SOC_SPEAR600_BD;
  169. else if (soc_id == 0)
  170. return SOC_SPEAR600_BA;
  171. else
  172. return SOC_SPEAR_NA;
  173. #elif defined(CONFIG_SPEAR300)
  174. return SOC_SPEAR300;
  175. #elif defined(CONFIG_SPEAR310)
  176. return SOC_SPEAR310;
  177. #elif defined(CONFIG_SPEAR320)
  178. return SOC_SPEAR320;
  179. #endif
  180. }
  181. /*
  182. * SNOR (Serial NOR flash) related functions
  183. */
  184. static void snor_init(void)
  185. {
  186. struct smi_regs *const smicntl =
  187. (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
  188. /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
  189. writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
  190. &smicntl->smi_cr1);
  191. }
  192. u32 spl_boot_device(void)
  193. {
  194. u32 mode = 0;
  195. if (usb_boot_selected()) {
  196. mode = BOOT_DEVICE_BOOTROM;
  197. } else if (snor_boot_selected()) {
  198. /* SNOR-SMI initialization */
  199. snor_init();
  200. mode = BOOT_DEVICE_NOR;
  201. }
  202. return mode;
  203. }
  204. void board_boot_order(u32 *spl_boot_list)
  205. {
  206. spl_boot_list[0] = spl_boot_device();
  207. /*
  208. * If the main boot device (eg. NOR) is empty, try to jump back into the
  209. * BootROM for USB boot process.
  210. */
  211. if (USB_BOOT_SUPPORTED)
  212. spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
  213. }
  214. void board_init_f(ulong dummy)
  215. {
  216. struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
  217. /* Initialize PLLs */
  218. sys_init();
  219. preloader_console_init();
  220. arch_cpu_init();
  221. /* Enable IPs (release reset) */
  222. writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
  223. /* Initialize MPMC */
  224. puts("Configure DDR\n");
  225. mpmc_init();
  226. spear_late_init();
  227. }
  228. /*
  229. * In a few cases (Ethernet, UART or USB boot, we might want to go back into the
  230. * BootROM code right after having initialized a few components like the DRAM).
  231. * The following function is called from SPL common code (board_init_r).
  232. */
  233. int board_return_to_bootrom(struct spl_image_info *spl_image,
  234. struct spl_boot_device *bootdev)
  235. {
  236. /*
  237. * Retrieve the BootROM's stack pointer and jump back to the start of
  238. * the SPL, where we can easily branch back into the BootROM. Don't do
  239. * it right here because SPL might be compiled in Thumb mode while the
  240. * BootROM expects ARM mode.
  241. */
  242. asm volatile ("ldr r0, =bootrom_stash_sp;"
  243. "ldr r0, [r0];"
  244. "mov sp, r0;"
  245. #if defined(CONFIG_SPL_SYS_THUMB_BUILD)
  246. "blx back_to_bootrom;"
  247. #else
  248. "bl back_to_bootrom;"
  249. #endif
  250. );
  251. return 0;
  252. }