atcspi200_spi.c 9.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Andestech ATCSPI200 SPI controller driver.
  4. *
  5. * Copyright 2017 Andes Technology, Inc.
  6. * Author: Rick Chen (rick@andestech.com)
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <spi.h>
  13. #include <asm/io.h>
  14. #include <dm.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. #define MAX_TRANSFER_LEN 512
  17. #define CHUNK_SIZE 1
  18. #define SPI_TIMEOUT 0x100000
  19. #define SPI0_BUS 0
  20. #define SPI1_BUS 1
  21. #define SPI0_BASE 0xf0b00000
  22. #define SPI1_BASE 0xf0f00000
  23. #define NSPI_MAX_CS_NUM 1
  24. struct atcspi200_spi_regs {
  25. u32 rev;
  26. u32 reserve1[3];
  27. u32 format; /* 0x10 */
  28. #define DATA_LENGTH(x) ((x-1)<<8)
  29. u32 pio;
  30. u32 reserve2[2];
  31. u32 tctrl; /* 0x20 */
  32. #define TRAMODE_OFFSET 24
  33. #define TRAMODE_MASK (0x0F<<TRAMODE_OFFSET)
  34. #define TRAMODE_WR_SYNC (0<<TRAMODE_OFFSET)
  35. #define TRAMODE_WO (1<<TRAMODE_OFFSET)
  36. #define TRAMODE_RO (2<<TRAMODE_OFFSET)
  37. #define TRAMODE_WR (3<<TRAMODE_OFFSET)
  38. #define TRAMODE_RW (4<<TRAMODE_OFFSET)
  39. #define TRAMODE_WDR (5<<TRAMODE_OFFSET)
  40. #define TRAMODE_RDW (6<<TRAMODE_OFFSET)
  41. #define TRAMODE_NONE (7<<TRAMODE_OFFSET)
  42. #define TRAMODE_DW (8<<TRAMODE_OFFSET)
  43. #define TRAMODE_DR (9<<TRAMODE_OFFSET)
  44. #define WCNT_OFFSET 12
  45. #define WCNT_MASK (0x1FF<<WCNT_OFFSET)
  46. #define RCNT_OFFSET 0
  47. #define RCNT_MASK (0x1FF<<RCNT_OFFSET)
  48. u32 cmd;
  49. u32 addr;
  50. u32 data;
  51. u32 ctrl; /* 0x30 */
  52. #define TXFTH_OFFSET 16
  53. #define RXFTH_OFFSET 8
  54. #define TXDMAEN (1<<4)
  55. #define RXDMAEN (1<<3)
  56. #define TXFRST (1<<2)
  57. #define RXFRST (1<<1)
  58. #define SPIRST (1<<0)
  59. u32 status;
  60. #define TXFFL (1<<23)
  61. #define TXEPTY (1<<22)
  62. #define TXFVE_MASK (0x1F<<16)
  63. #define RXFEM (1<<14)
  64. #define RXFVE_OFFSET (8)
  65. #define RXFVE_MASK (0x1F<<RXFVE_OFFSET)
  66. #define SPIBSY (1<<0)
  67. u32 inten;
  68. u32 intsta;
  69. u32 timing; /* 0x40 */
  70. #define SCLK_DIV_MASK 0xFF
  71. };
  72. struct nds_spi_slave {
  73. volatile struct atcspi200_spi_regs *regs;
  74. int to;
  75. unsigned int freq;
  76. ulong clock;
  77. unsigned int mode;
  78. u8 num_cs;
  79. unsigned int mtiming;
  80. size_t cmd_len;
  81. u8 cmd_buf[16];
  82. size_t data_len;
  83. size_t tran_len;
  84. u8 *din;
  85. u8 *dout;
  86. unsigned int max_transfer_length;
  87. };
  88. static int __atcspi200_spi_set_speed(struct nds_spi_slave *ns)
  89. {
  90. u32 tm;
  91. u8 div;
  92. tm = ns->regs->timing;
  93. tm &= ~SCLK_DIV_MASK;
  94. if(ns->freq >= ns->clock)
  95. div =0xff;
  96. else{
  97. for (div = 0; div < 0xff; div++) {
  98. if (ns->freq >= ns->clock / (2 * (div + 1)))
  99. break;
  100. }
  101. }
  102. tm |= div;
  103. ns->regs->timing = tm;
  104. return 0;
  105. }
  106. static int __atcspi200_spi_claim_bus(struct nds_spi_slave *ns)
  107. {
  108. unsigned int format=0;
  109. ns->regs->ctrl |= (TXFRST|RXFRST|SPIRST);
  110. while((ns->regs->ctrl &(TXFRST|RXFRST|SPIRST))&&(ns->to--))
  111. if(!ns->to)
  112. return -EINVAL;
  113. ns->cmd_len = 0;
  114. format = ns->mode|DATA_LENGTH(8);
  115. ns->regs->format = format;
  116. __atcspi200_spi_set_speed(ns);
  117. return 0;
  118. }
  119. static int __atcspi200_spi_release_bus(struct nds_spi_slave *ns)
  120. {
  121. /* do nothing */
  122. return 0;
  123. }
  124. static int __atcspi200_spi_start(struct nds_spi_slave *ns)
  125. {
  126. int i,olen=0;
  127. int tc = ns->regs->tctrl;
  128. tc &= ~(WCNT_MASK|RCNT_MASK|TRAMODE_MASK);
  129. if ((ns->din)&&(ns->cmd_len))
  130. tc |= TRAMODE_WR;
  131. else if (ns->din)
  132. tc |= TRAMODE_RO;
  133. else
  134. tc |= TRAMODE_WO;
  135. if(ns->dout)
  136. olen = ns->tran_len;
  137. tc |= (ns->cmd_len+olen-1) << WCNT_OFFSET;
  138. if(ns->din)
  139. tc |= (ns->tran_len-1) << RCNT_OFFSET;
  140. ns->regs->tctrl = tc;
  141. ns->regs->cmd = 1;
  142. for (i=0;i<ns->cmd_len;i++)
  143. ns->regs->data = ns->cmd_buf[i];
  144. return 0;
  145. }
  146. static int __atcspi200_spi_stop(struct nds_spi_slave *ns)
  147. {
  148. ns->regs->timing = ns->mtiming;
  149. while ((ns->regs->status & SPIBSY)&&(ns->to--))
  150. if (!ns->to)
  151. return -EINVAL;
  152. return 0;
  153. }
  154. static void __nspi_espi_tx(struct nds_spi_slave *ns, const void *dout)
  155. {
  156. ns->regs->data = *(u8 *)dout;
  157. }
  158. static int __nspi_espi_rx(struct nds_spi_slave *ns, void *din, unsigned int bytes)
  159. {
  160. *(u8 *)din = ns->regs->data;
  161. return bytes;
  162. }
  163. static int __atcspi200_spi_xfer(struct nds_spi_slave *ns,
  164. unsigned int bitlen, const void *data_out, void *data_in,
  165. unsigned long flags)
  166. {
  167. unsigned int event, rx_bytes;
  168. const void *dout = NULL;
  169. void *din = NULL;
  170. int num_blks, num_chunks, max_tran_len, tran_len;
  171. int num_bytes;
  172. u8 *cmd_buf = ns->cmd_buf;
  173. size_t cmd_len = ns->cmd_len;
  174. unsigned long data_len = bitlen / 8;
  175. int rf_cnt;
  176. int ret = 0;
  177. max_tran_len = ns->max_transfer_length;
  178. switch (flags) {
  179. case SPI_XFER_BEGIN:
  180. cmd_len = ns->cmd_len = data_len;
  181. memcpy(cmd_buf, data_out, cmd_len);
  182. return 0;
  183. case 0:
  184. case SPI_XFER_END:
  185. if (bitlen == 0) {
  186. return 0;
  187. }
  188. ns->data_len = data_len;
  189. ns->din = (u8 *)data_in;
  190. ns->dout = (u8 *)data_out;
  191. break;
  192. case SPI_XFER_BEGIN | SPI_XFER_END:
  193. ns->data_len = 0;
  194. ns->din = 0;
  195. ns->dout = 0;
  196. cmd_len = ns->cmd_len = data_len;
  197. memcpy(cmd_buf, data_out, cmd_len);
  198. data_out = 0;
  199. data_len = 0;
  200. __atcspi200_spi_start(ns);
  201. break;
  202. }
  203. if (data_out)
  204. debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) data_len %lu\n",
  205. *(uint *)data_out, data_out, *(uint *)data_in,
  206. data_in, data_len);
  207. num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
  208. din = data_in;
  209. dout = data_out;
  210. while (num_chunks--) {
  211. tran_len = min((size_t)data_len, (size_t)max_tran_len);
  212. ns->tran_len = tran_len;
  213. num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE);
  214. num_bytes = (tran_len) % CHUNK_SIZE;
  215. if(num_bytes == 0)
  216. num_bytes = CHUNK_SIZE;
  217. __atcspi200_spi_start(ns);
  218. while (num_blks) {
  219. event = in_le32(&ns->regs->status);
  220. if ((event & TXEPTY) && (data_out)) {
  221. __nspi_espi_tx(ns, dout);
  222. num_blks -= CHUNK_SIZE;
  223. dout += CHUNK_SIZE;
  224. }
  225. if ((event & RXFVE_MASK) && (data_in)) {
  226. rf_cnt = ((event & RXFVE_MASK)>> RXFVE_OFFSET);
  227. if (rf_cnt >= CHUNK_SIZE)
  228. rx_bytes = CHUNK_SIZE;
  229. else if (num_blks == 1 && rf_cnt == num_bytes)
  230. rx_bytes = num_bytes;
  231. else
  232. continue;
  233. if (__nspi_espi_rx(ns, din, rx_bytes) == rx_bytes) {
  234. num_blks -= CHUNK_SIZE;
  235. din = (unsigned char *)din + rx_bytes;
  236. }
  237. }
  238. }
  239. data_len -= tran_len;
  240. if(data_len)
  241. {
  242. ns->cmd_buf[1] += ((tran_len>>16)&0xff);
  243. ns->cmd_buf[2] += ((tran_len>>8)&0xff);
  244. ns->cmd_buf[3] += ((tran_len)&0xff);
  245. ns->data_len = data_len;
  246. }
  247. ret = __atcspi200_spi_stop(ns);
  248. }
  249. ret = __atcspi200_spi_stop(ns);
  250. return ret;
  251. }
  252. static int atcspi200_spi_set_speed(struct udevice *bus, uint max_hz)
  253. {
  254. struct nds_spi_slave *ns = dev_get_priv(bus);
  255. debug("%s speed %u\n", __func__, max_hz);
  256. ns->freq = max_hz;
  257. __atcspi200_spi_set_speed(ns);
  258. return 0;
  259. }
  260. static int atcspi200_spi_set_mode(struct udevice *bus, uint mode)
  261. {
  262. struct nds_spi_slave *ns = dev_get_priv(bus);
  263. debug("%s mode %u\n", __func__, mode);
  264. ns->mode = mode;
  265. return 0;
  266. }
  267. static int atcspi200_spi_claim_bus(struct udevice *dev)
  268. {
  269. struct dm_spi_slave_platdata *slave_plat =
  270. dev_get_parent_platdata(dev);
  271. struct udevice *bus = dev->parent;
  272. struct nds_spi_slave *ns = dev_get_priv(bus);
  273. if (slave_plat->cs >= ns->num_cs) {
  274. printf("Invalid SPI chipselect\n");
  275. return -EINVAL;
  276. }
  277. return __atcspi200_spi_claim_bus(ns);
  278. }
  279. static int atcspi200_spi_release_bus(struct udevice *dev)
  280. {
  281. struct nds_spi_slave *ns = dev_get_priv(dev->parent);
  282. return __atcspi200_spi_release_bus(ns);
  283. }
  284. static int atcspi200_spi_xfer(struct udevice *dev, unsigned int bitlen,
  285. const void *dout, void *din,
  286. unsigned long flags)
  287. {
  288. struct udevice *bus = dev->parent;
  289. struct nds_spi_slave *ns = dev_get_priv(bus);
  290. return __atcspi200_spi_xfer(ns, bitlen, dout, din, flags);
  291. }
  292. static int atcspi200_spi_get_clk(struct udevice *bus)
  293. {
  294. struct nds_spi_slave *ns = dev_get_priv(bus);
  295. struct clk clk;
  296. ulong clk_rate;
  297. int ret;
  298. ret = clk_get_by_index(bus, 0, &clk);
  299. if (ret)
  300. return -EINVAL;
  301. clk_rate = clk_get_rate(&clk);
  302. if (!clk_rate)
  303. return -EINVAL;
  304. ns->clock = clk_rate;
  305. clk_free(&clk);
  306. return 0;
  307. }
  308. static int atcspi200_spi_probe(struct udevice *bus)
  309. {
  310. struct nds_spi_slave *ns = dev_get_priv(bus);
  311. ns->to = SPI_TIMEOUT;
  312. ns->max_transfer_length = MAX_TRANSFER_LEN;
  313. ns->mtiming = ns->regs->timing;
  314. atcspi200_spi_get_clk(bus);
  315. return 0;
  316. }
  317. static int atcspi200_ofdata_to_platadata(struct udevice *bus)
  318. {
  319. struct nds_spi_slave *ns = dev_get_priv(bus);
  320. const void *blob = gd->fdt_blob;
  321. int node = dev_of_offset(bus);
  322. ns->regs = map_physmem(dev_read_addr(bus),
  323. sizeof(struct atcspi200_spi_regs),
  324. MAP_NOCACHE);
  325. if (!ns->regs) {
  326. printf("%s: could not map device address\n", __func__);
  327. return -EINVAL;
  328. }
  329. ns->num_cs = fdtdec_get_int(blob, node, "num-cs", 4);
  330. return 0;
  331. }
  332. static const struct dm_spi_ops atcspi200_spi_ops = {
  333. .claim_bus = atcspi200_spi_claim_bus,
  334. .release_bus = atcspi200_spi_release_bus,
  335. .xfer = atcspi200_spi_xfer,
  336. .set_speed = atcspi200_spi_set_speed,
  337. .set_mode = atcspi200_spi_set_mode,
  338. };
  339. static const struct udevice_id atcspi200_spi_ids[] = {
  340. { .compatible = "andestech,atcspi200" },
  341. { }
  342. };
  343. U_BOOT_DRIVER(atcspi200_spi) = {
  344. .name = "atcspi200_spi",
  345. .id = UCLASS_SPI,
  346. .of_match = atcspi200_spi_ids,
  347. .ops = &atcspi200_spi_ops,
  348. .ofdata_to_platdata = atcspi200_ofdata_to_platadata,
  349. .priv_auto_alloc_size = sizeof(struct nds_spi_slave),
  350. .probe = atcspi200_spi_probe,
  351. };