serial_sh.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SuperH SCIF device driver.
  4. * Copyright (C) 2013 Renesas Electronics Corporation
  5. * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu
  6. * Copyright (C) 2002 - 2008 Paul Mundt
  7. */
  8. #include <common.h>
  9. #include <errno.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <asm/io.h>
  13. #include <asm/processor.h>
  14. #include <serial.h>
  15. #include <linux/compiler.h>
  16. #include <dm/platform_data/serial_sh.h>
  17. #include <linux/delay.h>
  18. #include "serial_sh.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #if defined(CONFIG_CPU_SH7780)
  21. static int scif_rxfill(struct uart_port *port)
  22. {
  23. return sci_in(port, SCRFDR) & 0xff;
  24. }
  25. #elif defined(CONFIG_CPU_SH7763)
  26. static int scif_rxfill(struct uart_port *port)
  27. {
  28. if ((port->mapbase == 0xffe00000) ||
  29. (port->mapbase == 0xffe08000)) {
  30. /* SCIF0/1*/
  31. return sci_in(port, SCRFDR) & 0xff;
  32. } else {
  33. /* SCIF2 */
  34. return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
  35. }
  36. }
  37. #else
  38. static int scif_rxfill(struct uart_port *port)
  39. {
  40. return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
  41. }
  42. #endif
  43. static void sh_serial_init_generic(struct uart_port *port)
  44. {
  45. sci_out(port, SCSCR , SCSCR_INIT(port));
  46. sci_out(port, SCSCR , SCSCR_INIT(port));
  47. sci_out(port, SCSMR, 0);
  48. sci_out(port, SCSMR, 0);
  49. sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST);
  50. sci_in(port, SCFCR);
  51. sci_out(port, SCFCR, 0);
  52. #if defined(CONFIG_RZA1)
  53. sci_out(port, SCSPTR, 0x0003);
  54. #endif
  55. }
  56. static void
  57. sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate)
  58. {
  59. if (port->clk_mode == EXT_CLK) {
  60. unsigned short dl = DL_VALUE(baudrate, clk);
  61. sci_out(port, DL, dl);
  62. /* Need wait: Clock * 1/dl * 1/16 */
  63. udelay((1000000 * dl * 16 / clk) * 1000 + 1);
  64. } else {
  65. sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk));
  66. }
  67. }
  68. static void handle_error(struct uart_port *port)
  69. {
  70. sci_in(port, SCxSR);
  71. sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
  72. sci_in(port, SCLSR);
  73. sci_out(port, SCLSR, 0x00);
  74. }
  75. static int serial_raw_putc(struct uart_port *port, const char c)
  76. {
  77. /* Tx fifo is empty */
  78. if (!(sci_in(port, SCxSR) & SCxSR_TEND(port)))
  79. return -EAGAIN;
  80. sci_out(port, SCxTDR, c);
  81. sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port));
  82. return 0;
  83. }
  84. static int serial_rx_fifo_level(struct uart_port *port)
  85. {
  86. return scif_rxfill(port);
  87. }
  88. static int sh_serial_tstc_generic(struct uart_port *port)
  89. {
  90. if (sci_in(port, SCxSR) & SCIF_ERRORS) {
  91. handle_error(port);
  92. return 0;
  93. }
  94. return serial_rx_fifo_level(port) ? 1 : 0;
  95. }
  96. static int serial_getc_check(struct uart_port *port)
  97. {
  98. unsigned short status;
  99. status = sci_in(port, SCxSR);
  100. if (status & SCIF_ERRORS)
  101. handle_error(port);
  102. if (sci_in(port, SCLSR) & SCxSR_ORER(port))
  103. handle_error(port);
  104. return status & (SCIF_DR | SCxSR_RDxF(port));
  105. }
  106. static int sh_serial_getc_generic(struct uart_port *port)
  107. {
  108. unsigned short status;
  109. char ch;
  110. if (!serial_getc_check(port))
  111. return -EAGAIN;
  112. ch = sci_in(port, SCxRDR);
  113. status = sci_in(port, SCxSR);
  114. sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
  115. if (status & SCIF_ERRORS)
  116. handle_error(port);
  117. if (sci_in(port, SCLSR) & SCxSR_ORER(port))
  118. handle_error(port);
  119. return ch;
  120. }
  121. #if CONFIG_IS_ENABLED(DM_SERIAL)
  122. static int sh_serial_pending(struct udevice *dev, bool input)
  123. {
  124. struct uart_port *priv = dev_get_priv(dev);
  125. return sh_serial_tstc_generic(priv);
  126. }
  127. static int sh_serial_putc(struct udevice *dev, const char ch)
  128. {
  129. struct uart_port *priv = dev_get_priv(dev);
  130. return serial_raw_putc(priv, ch);
  131. }
  132. static int sh_serial_getc(struct udevice *dev)
  133. {
  134. struct uart_port *priv = dev_get_priv(dev);
  135. return sh_serial_getc_generic(priv);
  136. }
  137. static int sh_serial_setbrg(struct udevice *dev, int baudrate)
  138. {
  139. struct sh_serial_platdata *plat = dev_get_platdata(dev);
  140. struct uart_port *priv = dev_get_priv(dev);
  141. sh_serial_setbrg_generic(priv, plat->clk, baudrate);
  142. return 0;
  143. }
  144. static int sh_serial_probe(struct udevice *dev)
  145. {
  146. struct sh_serial_platdata *plat = dev_get_platdata(dev);
  147. struct uart_port *priv = dev_get_priv(dev);
  148. priv->membase = (unsigned char *)plat->base;
  149. priv->mapbase = plat->base;
  150. priv->type = plat->type;
  151. priv->clk_mode = plat->clk_mode;
  152. sh_serial_init_generic(priv);
  153. return 0;
  154. }
  155. static const struct dm_serial_ops sh_serial_ops = {
  156. .putc = sh_serial_putc,
  157. .pending = sh_serial_pending,
  158. .getc = sh_serial_getc,
  159. .setbrg = sh_serial_setbrg,
  160. };
  161. #if CONFIG_IS_ENABLED(OF_CONTROL)
  162. static const struct udevice_id sh_serial_id[] ={
  163. {.compatible = "renesas,sci", .data = PORT_SCI},
  164. {.compatible = "renesas,scif", .data = PORT_SCIF},
  165. {.compatible = "renesas,scifa", .data = PORT_SCIFA},
  166. {}
  167. };
  168. static int sh_serial_ofdata_to_platdata(struct udevice *dev)
  169. {
  170. struct sh_serial_platdata *plat = dev_get_platdata(dev);
  171. struct clk sh_serial_clk;
  172. fdt_addr_t addr;
  173. int ret;
  174. addr = dev_read_addr(dev);
  175. if (!addr)
  176. return -EINVAL;
  177. plat->base = addr;
  178. ret = clk_get_by_name(dev, "fck", &sh_serial_clk);
  179. if (!ret) {
  180. ret = clk_enable(&sh_serial_clk);
  181. if (!ret)
  182. plat->clk = clk_get_rate(&sh_serial_clk);
  183. } else {
  184. plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  185. "clock", 1);
  186. }
  187. plat->type = dev_get_driver_data(dev);
  188. return 0;
  189. }
  190. #endif
  191. U_BOOT_DRIVER(serial_sh) = {
  192. .name = "serial_sh",
  193. .id = UCLASS_SERIAL,
  194. .of_match = of_match_ptr(sh_serial_id),
  195. .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata),
  196. .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata),
  197. .probe = sh_serial_probe,
  198. .ops = &sh_serial_ops,
  199. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  200. .flags = DM_FLAG_PRE_RELOC,
  201. #endif
  202. .priv_auto_alloc_size = sizeof(struct uart_port),
  203. };
  204. #else /* CONFIG_DM_SERIAL */
  205. #if defined(CONFIG_CONS_SCIF0)
  206. # define SCIF_BASE SCIF0_BASE
  207. #elif defined(CONFIG_CONS_SCIF1)
  208. # define SCIF_BASE SCIF1_BASE
  209. #elif defined(CONFIG_CONS_SCIF2)
  210. # define SCIF_BASE SCIF2_BASE
  211. #elif defined(CONFIG_CONS_SCIF3)
  212. # define SCIF_BASE SCIF3_BASE
  213. #elif defined(CONFIG_CONS_SCIF4)
  214. # define SCIF_BASE SCIF4_BASE
  215. #elif defined(CONFIG_CONS_SCIF5)
  216. # define SCIF_BASE SCIF5_BASE
  217. #elif defined(CONFIG_CONS_SCIF6)
  218. # define SCIF_BASE SCIF6_BASE
  219. #elif defined(CONFIG_CONS_SCIF7)
  220. # define SCIF_BASE SCIF7_BASE
  221. #elif defined(CONFIG_CONS_SCIFA0)
  222. # define SCIF_BASE SCIFA0_BASE
  223. #else
  224. # error "Default SCIF doesn't set....."
  225. #endif
  226. #if defined(CONFIG_SCIF_A)
  227. #define SCIF_BASE_PORT PORT_SCIFA
  228. #elif defined(CONFIG_SCI)
  229. #define SCIF_BASE_PORT PORT_SCI
  230. #else
  231. #define SCIF_BASE_PORT PORT_SCIF
  232. #endif
  233. static struct uart_port sh_sci = {
  234. .membase = (unsigned char *)SCIF_BASE,
  235. .mapbase = SCIF_BASE,
  236. .type = SCIF_BASE_PORT,
  237. #ifdef CONFIG_SCIF_USE_EXT_CLK
  238. .clk_mode = EXT_CLK,
  239. #endif
  240. };
  241. static void sh_serial_setbrg(void)
  242. {
  243. DECLARE_GLOBAL_DATA_PTR;
  244. struct uart_port *port = &sh_sci;
  245. sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate);
  246. }
  247. static int sh_serial_init(void)
  248. {
  249. struct uart_port *port = &sh_sci;
  250. sh_serial_init_generic(port);
  251. serial_setbrg();
  252. return 0;
  253. }
  254. static void sh_serial_putc(const char c)
  255. {
  256. struct uart_port *port = &sh_sci;
  257. if (c == '\n') {
  258. while (1) {
  259. if (serial_raw_putc(port, '\r') != -EAGAIN)
  260. break;
  261. }
  262. }
  263. while (1) {
  264. if (serial_raw_putc(port, c) != -EAGAIN)
  265. break;
  266. }
  267. }
  268. static int sh_serial_tstc(void)
  269. {
  270. struct uart_port *port = &sh_sci;
  271. return sh_serial_tstc_generic(port);
  272. }
  273. static int sh_serial_getc(void)
  274. {
  275. struct uart_port *port = &sh_sci;
  276. int ch;
  277. while (1) {
  278. ch = sh_serial_getc_generic(port);
  279. if (ch != -EAGAIN)
  280. break;
  281. }
  282. return ch;
  283. }
  284. static struct serial_device sh_serial_drv = {
  285. .name = "sh_serial",
  286. .start = sh_serial_init,
  287. .stop = NULL,
  288. .setbrg = sh_serial_setbrg,
  289. .putc = sh_serial_putc,
  290. .puts = default_serial_puts,
  291. .getc = sh_serial_getc,
  292. .tstc = sh_serial_tstc,
  293. };
  294. void sh_serial_initialize(void)
  295. {
  296. serial_register(&sh_serial_drv);
  297. }
  298. __weak struct serial_device *default_serial_console(void)
  299. {
  300. return &sh_serial_drv;
  301. }
  302. #endif /* CONFIG_DM_SERIAL */