serial_pl01x.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000
  4. * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
  5. *
  6. * (C) Copyright 2004
  7. * ARM Ltd.
  8. * Philippe Robin, <philippe.robin@arm.com>
  9. */
  10. /* Simple U-Boot driver for the PrimeCell PL010/PL011 UARTs */
  11. #include <common.h>
  12. /* For get_bus_freq() */
  13. #include <clock_legacy.h>
  14. #include <dm.h>
  15. #include <clk.h>
  16. #include <errno.h>
  17. #include <watchdog.h>
  18. #include <asm/io.h>
  19. #include <serial.h>
  20. #include <dm/platform_data/serial_pl01x.h>
  21. #include <linux/compiler.h>
  22. #include "serial_pl01x_internal.h"
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #ifndef CONFIG_DM_SERIAL
  25. static volatile unsigned char *const port[] = CONFIG_PL01x_PORTS;
  26. static enum pl01x_type pl01x_type __attribute__ ((section(".data")));
  27. static struct pl01x_regs *base_regs __attribute__ ((section(".data")));
  28. #define NUM_PORTS (sizeof(port)/sizeof(port[0]))
  29. #endif
  30. static int pl01x_putc(struct pl01x_regs *regs, char c)
  31. {
  32. /* Wait until there is space in the FIFO */
  33. if (readl(&regs->fr) & UART_PL01x_FR_TXFF)
  34. return -EAGAIN;
  35. /* Send the character */
  36. writel(c, &regs->dr);
  37. return 0;
  38. }
  39. static int pl01x_getc(struct pl01x_regs *regs)
  40. {
  41. unsigned int data;
  42. /* Wait until there is data in the FIFO */
  43. if (readl(&regs->fr) & UART_PL01x_FR_RXFE)
  44. return -EAGAIN;
  45. data = readl(&regs->dr);
  46. /* Check for an error flag */
  47. if (data & 0xFFFFFF00) {
  48. /* Clear the error */
  49. writel(0xFFFFFFFF, &regs->ecr);
  50. return -1;
  51. }
  52. return (int) data;
  53. }
  54. static int pl01x_tstc(struct pl01x_regs *regs)
  55. {
  56. WATCHDOG_RESET();
  57. return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
  58. }
  59. static int pl01x_generic_serial_init(struct pl01x_regs *regs,
  60. enum pl01x_type type)
  61. {
  62. switch (type) {
  63. case TYPE_PL010:
  64. /* disable everything */
  65. writel(0, &regs->pl010_cr);
  66. break;
  67. case TYPE_PL011:
  68. /* disable everything */
  69. writel(0, &regs->pl011_cr);
  70. break;
  71. default:
  72. return -EINVAL;
  73. }
  74. return 0;
  75. }
  76. static int pl011_set_line_control(struct pl01x_regs *regs)
  77. {
  78. unsigned int lcr;
  79. /*
  80. * Internal update of baud rate register require line
  81. * control register write
  82. */
  83. lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN;
  84. writel(lcr, &regs->pl011_lcrh);
  85. return 0;
  86. }
  87. static int pl01x_generic_setbrg(struct pl01x_regs *regs, enum pl01x_type type,
  88. int clock, int baudrate)
  89. {
  90. switch (type) {
  91. case TYPE_PL010: {
  92. unsigned int divisor;
  93. /* disable everything */
  94. writel(0, &regs->pl010_cr);
  95. switch (baudrate) {
  96. case 9600:
  97. divisor = UART_PL010_BAUD_9600;
  98. break;
  99. case 19200:
  100. divisor = UART_PL010_BAUD_19200;
  101. break;
  102. case 38400:
  103. divisor = UART_PL010_BAUD_38400;
  104. break;
  105. case 57600:
  106. divisor = UART_PL010_BAUD_57600;
  107. break;
  108. case 115200:
  109. divisor = UART_PL010_BAUD_115200;
  110. break;
  111. default:
  112. divisor = UART_PL010_BAUD_38400;
  113. }
  114. writel((divisor & 0xf00) >> 8, &regs->pl010_lcrm);
  115. writel(divisor & 0xff, &regs->pl010_lcrl);
  116. /*
  117. * Set line control for the PL010 to be 8 bits, 1 stop bit,
  118. * no parity, fifo enabled
  119. */
  120. writel(UART_PL010_LCRH_WLEN_8 | UART_PL010_LCRH_FEN,
  121. &regs->pl010_lcrh);
  122. /* Finally, enable the UART */
  123. writel(UART_PL010_CR_UARTEN, &regs->pl010_cr);
  124. break;
  125. }
  126. case TYPE_PL011: {
  127. unsigned int temp;
  128. unsigned int divider;
  129. unsigned int remainder;
  130. unsigned int fraction;
  131. /* Without a valid clock rate we cannot set up the baudrate. */
  132. if (clock) {
  133. /*
  134. * Set baud rate
  135. *
  136. * IBRD = UART_CLK / (16 * BAUD_RATE)
  137. * FBRD = RND((64 * MOD(UART_CLK,(16 * BAUD_RATE)))
  138. * / (16 * BAUD_RATE))
  139. */
  140. temp = 16 * baudrate;
  141. divider = clock / temp;
  142. remainder = clock % temp;
  143. temp = (8 * remainder) / baudrate;
  144. fraction = (temp >> 1) + (temp & 1);
  145. writel(divider, &regs->pl011_ibrd);
  146. writel(fraction, &regs->pl011_fbrd);
  147. }
  148. pl011_set_line_control(regs);
  149. /* Finally, enable the UART */
  150. writel(UART_PL011_CR_UARTEN | UART_PL011_CR_TXE |
  151. UART_PL011_CR_RXE | UART_PL011_CR_RTS, &regs->pl011_cr);
  152. break;
  153. }
  154. default:
  155. return -EINVAL;
  156. }
  157. return 0;
  158. }
  159. #ifndef CONFIG_DM_SERIAL
  160. static void pl01x_serial_init_baud(int baudrate)
  161. {
  162. int clock = 0;
  163. #if defined(CONFIG_PL010_SERIAL)
  164. pl01x_type = TYPE_PL010;
  165. #elif defined(CONFIG_PL011_SERIAL)
  166. pl01x_type = TYPE_PL011;
  167. clock = CONFIG_PL011_CLOCK;
  168. #endif
  169. base_regs = (struct pl01x_regs *)port[CONFIG_CONS_INDEX];
  170. pl01x_generic_serial_init(base_regs, pl01x_type);
  171. pl01x_generic_setbrg(base_regs, pl01x_type, clock, baudrate);
  172. }
  173. /*
  174. * Integrator AP has two UARTs, we use the first one, at 38400-8-N-1
  175. * Integrator CP has two UARTs, use the first one, at 38400-8-N-1
  176. * Versatile PB has four UARTs.
  177. */
  178. int pl01x_serial_init(void)
  179. {
  180. pl01x_serial_init_baud(CONFIG_BAUDRATE);
  181. return 0;
  182. }
  183. static void pl01x_serial_putc(const char c)
  184. {
  185. if (c == '\n')
  186. while (pl01x_putc(base_regs, '\r') == -EAGAIN);
  187. while (pl01x_putc(base_regs, c) == -EAGAIN);
  188. }
  189. static int pl01x_serial_getc(void)
  190. {
  191. while (1) {
  192. int ch = pl01x_getc(base_regs);
  193. if (ch == -EAGAIN) {
  194. WATCHDOG_RESET();
  195. continue;
  196. }
  197. return ch;
  198. }
  199. }
  200. static int pl01x_serial_tstc(void)
  201. {
  202. return pl01x_tstc(base_regs);
  203. }
  204. static void pl01x_serial_setbrg(void)
  205. {
  206. /*
  207. * Flush FIFO and wait for non-busy before changing baudrate to avoid
  208. * crap in console
  209. */
  210. while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
  211. WATCHDOG_RESET();
  212. while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
  213. WATCHDOG_RESET();
  214. pl01x_serial_init_baud(gd->baudrate);
  215. }
  216. static struct serial_device pl01x_serial_drv = {
  217. .name = "pl01x_serial",
  218. .start = pl01x_serial_init,
  219. .stop = NULL,
  220. .setbrg = pl01x_serial_setbrg,
  221. .putc = pl01x_serial_putc,
  222. .puts = default_serial_puts,
  223. .getc = pl01x_serial_getc,
  224. .tstc = pl01x_serial_tstc,
  225. };
  226. void pl01x_serial_initialize(void)
  227. {
  228. serial_register(&pl01x_serial_drv);
  229. }
  230. __weak struct serial_device *default_serial_console(void)
  231. {
  232. return &pl01x_serial_drv;
  233. }
  234. #endif /* nCONFIG_DM_SERIAL */
  235. #ifdef CONFIG_DM_SERIAL
  236. int pl01x_serial_setbrg(struct udevice *dev, int baudrate)
  237. {
  238. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  239. struct pl01x_priv *priv = dev_get_priv(dev);
  240. if (!plat->skip_init) {
  241. pl01x_generic_setbrg(priv->regs, priv->type, plat->clock,
  242. baudrate);
  243. }
  244. return 0;
  245. }
  246. int pl01x_serial_probe(struct udevice *dev)
  247. {
  248. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  249. struct pl01x_priv *priv = dev_get_priv(dev);
  250. priv->regs = (struct pl01x_regs *)plat->base;
  251. priv->type = plat->type;
  252. if (!plat->skip_init)
  253. return pl01x_generic_serial_init(priv->regs, priv->type);
  254. else
  255. return 0;
  256. }
  257. int pl01x_serial_getc(struct udevice *dev)
  258. {
  259. struct pl01x_priv *priv = dev_get_priv(dev);
  260. return pl01x_getc(priv->regs);
  261. }
  262. int pl01x_serial_putc(struct udevice *dev, const char ch)
  263. {
  264. struct pl01x_priv *priv = dev_get_priv(dev);
  265. return pl01x_putc(priv->regs, ch);
  266. }
  267. int pl01x_serial_pending(struct udevice *dev, bool input)
  268. {
  269. struct pl01x_priv *priv = dev_get_priv(dev);
  270. unsigned int fr = readl(&priv->regs->fr);
  271. if (input)
  272. return pl01x_tstc(priv->regs);
  273. else
  274. return fr & UART_PL01x_FR_TXFF ? 0 : 1;
  275. }
  276. static const struct dm_serial_ops pl01x_serial_ops = {
  277. .putc = pl01x_serial_putc,
  278. .pending = pl01x_serial_pending,
  279. .getc = pl01x_serial_getc,
  280. .setbrg = pl01x_serial_setbrg,
  281. };
  282. #if CONFIG_IS_ENABLED(OF_CONTROL)
  283. static const struct udevice_id pl01x_serial_id[] ={
  284. {.compatible = "arm,pl011", .data = TYPE_PL011},
  285. {.compatible = "arm,pl010", .data = TYPE_PL010},
  286. {}
  287. };
  288. #ifndef CONFIG_PL011_CLOCK
  289. #define CONFIG_PL011_CLOCK 0
  290. #endif
  291. int pl01x_serial_ofdata_to_platdata(struct udevice *dev)
  292. {
  293. struct pl01x_serial_platdata *plat = dev_get_platdata(dev);
  294. struct clk clk;
  295. fdt_addr_t addr;
  296. int ret;
  297. addr = dev_read_addr(dev);
  298. if (addr == FDT_ADDR_T_NONE)
  299. return -EINVAL;
  300. plat->base = addr;
  301. plat->clock = dev_read_u32_default(dev, "clock", CONFIG_PL011_CLOCK);
  302. ret = clk_get_by_index(dev, 0, &clk);
  303. if (!ret) {
  304. clk_enable(&clk);
  305. plat->clock = clk_get_rate(&clk);
  306. }
  307. plat->type = dev_get_driver_data(dev);
  308. plat->skip_init = dev_read_bool(dev, "skip-init");
  309. return 0;
  310. }
  311. #endif
  312. U_BOOT_DRIVER(serial_pl01x) = {
  313. .name = "serial_pl01x",
  314. .id = UCLASS_SERIAL,
  315. .of_match = of_match_ptr(pl01x_serial_id),
  316. .ofdata_to_platdata = of_match_ptr(pl01x_serial_ofdata_to_platdata),
  317. .platdata_auto_alloc_size = sizeof(struct pl01x_serial_platdata),
  318. .probe = pl01x_serial_probe,
  319. .ops = &pl01x_serial_ops,
  320. .flags = DM_FLAG_PRE_RELOC,
  321. .priv_auto_alloc_size = sizeof(struct pl01x_priv),
  322. };
  323. #endif
  324. #if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011)
  325. #include <debug_uart.h>
  326. static void _debug_uart_init(void)
  327. {
  328. #ifndef CONFIG_DEBUG_UART_SKIP_INIT
  329. struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
  330. enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ?
  331. TYPE_PL011 : TYPE_PL010;
  332. pl01x_generic_serial_init(regs, type);
  333. pl01x_generic_setbrg(regs, type,
  334. CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
  335. #endif
  336. }
  337. static inline void _debug_uart_putc(int ch)
  338. {
  339. struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE;
  340. pl01x_putc(regs, ch);
  341. }
  342. DEBUG_UART_FUNCS
  343. #endif