atmel_usart.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2004-2006 Atmel Corporation
  4. *
  5. * Modified to support C structur SoC access by
  6. * Andreas Bießmann <biessmann@corscience.de>
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <malloc.h>
  13. #include <watchdog.h>
  14. #include <serial.h>
  15. #include <debug_uart.h>
  16. #include <linux/compiler.h>
  17. #include <linux/delay.h>
  18. #include <asm/io.h>
  19. #ifdef CONFIG_DM_SERIAL
  20. #include <asm/arch/atmel_serial.h>
  21. #endif
  22. #include <asm/arch/clk.h>
  23. #include <asm/arch/hardware.h>
  24. #include "atmel_usart.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #ifndef CONFIG_DM_SERIAL
  27. static void atmel_serial_setbrg_internal(atmel_usart3_t *usart, int id,
  28. int baudrate)
  29. {
  30. unsigned long divisor;
  31. unsigned long usart_hz;
  32. /*
  33. * Master Clock
  34. * Baud Rate = --------------
  35. * 16 * CD
  36. */
  37. usart_hz = get_usart_clk_rate(id);
  38. divisor = (usart_hz / 16 + baudrate / 2) / baudrate;
  39. writel(USART3_BF(CD, divisor), &usart->brgr);
  40. }
  41. static void atmel_serial_init_internal(atmel_usart3_t *usart)
  42. {
  43. /*
  44. * Just in case: drain transmitter register
  45. * 1000us is enough for baudrate >= 9600
  46. */
  47. if (!(readl(&usart->csr) & USART3_BIT(TXEMPTY)))
  48. __udelay(1000);
  49. writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
  50. }
  51. static void atmel_serial_activate(atmel_usart3_t *usart)
  52. {
  53. writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL)
  54. | USART3_BF(USCLKS, USART3_USCLKS_MCK)
  55. | USART3_BF(CHRL, USART3_CHRL_8)
  56. | USART3_BF(PAR, USART3_PAR_NONE)
  57. | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
  58. &usart->mr);
  59. writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
  60. /* 100us is enough for the new settings to be settled */
  61. __udelay(100);
  62. }
  63. static void atmel_serial_setbrg(void)
  64. {
  65. atmel_serial_setbrg_internal((atmel_usart3_t *)CONFIG_USART_BASE,
  66. CONFIG_USART_ID, gd->baudrate);
  67. }
  68. static int atmel_serial_init(void)
  69. {
  70. atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
  71. atmel_serial_init_internal(usart);
  72. serial_setbrg();
  73. atmel_serial_activate(usart);
  74. return 0;
  75. }
  76. static void atmel_serial_putc(char c)
  77. {
  78. atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
  79. if (c == '\n')
  80. serial_putc('\r');
  81. while (!(readl(&usart->csr) & USART3_BIT(TXRDY)));
  82. writel(c, &usart->thr);
  83. }
  84. static int atmel_serial_getc(void)
  85. {
  86. atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
  87. while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
  88. WATCHDOG_RESET();
  89. return readl(&usart->rhr);
  90. }
  91. static int atmel_serial_tstc(void)
  92. {
  93. atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
  94. return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
  95. }
  96. static struct serial_device atmel_serial_drv = {
  97. .name = "atmel_serial",
  98. .start = atmel_serial_init,
  99. .stop = NULL,
  100. .setbrg = atmel_serial_setbrg,
  101. .putc = atmel_serial_putc,
  102. .puts = default_serial_puts,
  103. .getc = atmel_serial_getc,
  104. .tstc = atmel_serial_tstc,
  105. };
  106. void atmel_serial_initialize(void)
  107. {
  108. serial_register(&atmel_serial_drv);
  109. }
  110. __weak struct serial_device *default_serial_console(void)
  111. {
  112. return &atmel_serial_drv;
  113. }
  114. #endif
  115. #ifdef CONFIG_DM_SERIAL
  116. enum serial_clk_type {
  117. CLK_TYPE_NORMAL = 0,
  118. CLK_TYPE_DBGU,
  119. };
  120. struct atmel_serial_priv {
  121. atmel_usart3_t *usart;
  122. ulong usart_clk_rate;
  123. };
  124. static void _atmel_serial_set_brg(atmel_usart3_t *usart,
  125. ulong usart_clk_rate, int baudrate)
  126. {
  127. unsigned long divisor;
  128. divisor = (usart_clk_rate / 16 + baudrate / 2) / baudrate;
  129. writel(USART3_BF(CD, divisor), &usart->brgr);
  130. }
  131. void _atmel_serial_init(atmel_usart3_t *usart,
  132. ulong usart_clk_rate, int baudrate)
  133. {
  134. writel(USART3_BIT(RXDIS) | USART3_BIT(TXDIS), &usart->cr);
  135. writel((USART3_BF(USART_MODE, USART3_USART_MODE_NORMAL) |
  136. USART3_BF(USCLKS, USART3_USCLKS_MCK) |
  137. USART3_BF(CHRL, USART3_CHRL_8) |
  138. USART3_BF(PAR, USART3_PAR_NONE) |
  139. USART3_BF(NBSTOP, USART3_NBSTOP_1)), &usart->mr);
  140. _atmel_serial_set_brg(usart, usart_clk_rate, baudrate);
  141. writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
  142. writel(USART3_BIT(RXEN) | USART3_BIT(TXEN), &usart->cr);
  143. }
  144. int atmel_serial_setbrg(struct udevice *dev, int baudrate)
  145. {
  146. struct atmel_serial_priv *priv = dev_get_priv(dev);
  147. _atmel_serial_set_brg(priv->usart, priv->usart_clk_rate, baudrate);
  148. return 0;
  149. }
  150. static int atmel_serial_getc(struct udevice *dev)
  151. {
  152. struct atmel_serial_priv *priv = dev_get_priv(dev);
  153. if (!(readl(&priv->usart->csr) & USART3_BIT(RXRDY)))
  154. return -EAGAIN;
  155. return readl(&priv->usart->rhr);
  156. }
  157. static int atmel_serial_putc(struct udevice *dev, const char ch)
  158. {
  159. struct atmel_serial_priv *priv = dev_get_priv(dev);
  160. if (!(readl(&priv->usart->csr) & USART3_BIT(TXRDY)))
  161. return -EAGAIN;
  162. writel(ch, &priv->usart->thr);
  163. return 0;
  164. }
  165. static int atmel_serial_pending(struct udevice *dev, bool input)
  166. {
  167. struct atmel_serial_priv *priv = dev_get_priv(dev);
  168. uint32_t csr = readl(&priv->usart->csr);
  169. if (input)
  170. return csr & USART3_BIT(RXRDY) ? 1 : 0;
  171. else
  172. return csr & USART3_BIT(TXEMPTY) ? 0 : 1;
  173. }
  174. static const struct dm_serial_ops atmel_serial_ops = {
  175. .putc = atmel_serial_putc,
  176. .pending = atmel_serial_pending,
  177. .getc = atmel_serial_getc,
  178. .setbrg = atmel_serial_setbrg,
  179. };
  180. #if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_CLK)
  181. static int atmel_serial_enable_clk(struct udevice *dev)
  182. {
  183. struct atmel_serial_priv *priv = dev_get_priv(dev);
  184. /* Use fixed clock value in SPL */
  185. priv->usart_clk_rate = CONFIG_SPL_UART_CLOCK;
  186. return 0;
  187. }
  188. #else
  189. static int atmel_serial_enable_clk(struct udevice *dev)
  190. {
  191. struct atmel_serial_priv *priv = dev_get_priv(dev);
  192. struct clk clk;
  193. ulong clk_rate;
  194. int ret;
  195. ret = clk_get_by_index(dev, 0, &clk);
  196. if (ret)
  197. return -EINVAL;
  198. if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) {
  199. ret = clk_enable(&clk);
  200. if (ret)
  201. return ret;
  202. }
  203. clk_rate = clk_get_rate(&clk);
  204. if (!clk_rate)
  205. return -EINVAL;
  206. priv->usart_clk_rate = clk_rate;
  207. clk_free(&clk);
  208. return 0;
  209. }
  210. #endif
  211. static int atmel_serial_probe(struct udevice *dev)
  212. {
  213. struct atmel_serial_platdata *plat = dev->platdata;
  214. struct atmel_serial_priv *priv = dev_get_priv(dev);
  215. int ret;
  216. #if CONFIG_IS_ENABLED(OF_CONTROL)
  217. fdt_addr_t addr_base;
  218. addr_base = dev_read_addr(dev);
  219. if (addr_base == FDT_ADDR_T_NONE)
  220. return -ENODEV;
  221. plat->base_addr = (uint32_t)addr_base;
  222. #endif
  223. priv->usart = (atmel_usart3_t *)plat->base_addr;
  224. ret = atmel_serial_enable_clk(dev);
  225. if (ret)
  226. return ret;
  227. _atmel_serial_init(priv->usart, priv->usart_clk_rate, gd->baudrate);
  228. return 0;
  229. }
  230. #if CONFIG_IS_ENABLED(OF_CONTROL)
  231. static const struct udevice_id atmel_serial_ids[] = {
  232. {
  233. .compatible = "atmel,at91sam9260-dbgu",
  234. .data = CLK_TYPE_DBGU,
  235. },
  236. {
  237. .compatible = "atmel,at91sam9260-usart",
  238. .data = CLK_TYPE_NORMAL,
  239. },
  240. { }
  241. };
  242. #endif
  243. U_BOOT_DRIVER(serial_atmel) = {
  244. .name = "serial_atmel",
  245. .id = UCLASS_SERIAL,
  246. #if CONFIG_IS_ENABLED(OF_CONTROL)
  247. .of_match = atmel_serial_ids,
  248. .platdata_auto_alloc_size = sizeof(struct atmel_serial_platdata),
  249. #endif
  250. .probe = atmel_serial_probe,
  251. .ops = &atmel_serial_ops,
  252. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  253. .flags = DM_FLAG_PRE_RELOC,
  254. #endif
  255. .priv_auto_alloc_size = sizeof(struct atmel_serial_priv),
  256. };
  257. #endif
  258. #ifdef CONFIG_DEBUG_UART_ATMEL
  259. static inline void _debug_uart_init(void)
  260. {
  261. atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
  262. _atmel_serial_init(usart, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
  263. }
  264. static inline void _debug_uart_putc(int ch)
  265. {
  266. atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_DEBUG_UART_BASE;
  267. while (!(readl(&usart->csr) & USART3_BIT(TXRDY)))
  268. ;
  269. writel(ch, &usart->thr);
  270. }
  271. DEBUG_UART_FUNCS
  272. #endif