pinctrl_ar933x.c 2.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <log.h>
  9. #include <asm/io.h>
  10. #include <dm/pinctrl.h>
  11. #include <mach/ar71xx_regs.h>
  12. DECLARE_GLOBAL_DATA_PTR;
  13. enum periph_id {
  14. PERIPH_ID_UART0,
  15. PERIPH_ID_SPI0,
  16. PERIPH_ID_NONE = -1,
  17. };
  18. struct ar933x_pinctrl_priv {
  19. void __iomem *regs;
  20. };
  21. static void pinctrl_ar933x_spi_config(struct ar933x_pinctrl_priv *priv, int cs)
  22. {
  23. switch (cs) {
  24. case 0:
  25. clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
  26. AR933X_GPIO(4), AR933X_GPIO(3) |
  27. AR933X_GPIO(5) | AR933X_GPIO(2));
  28. setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
  29. AR933X_GPIO_FUNC_SPI_EN |
  30. AR933X_GPIO_FUNC_RES_TRUE);
  31. break;
  32. }
  33. }
  34. static void pinctrl_ar933x_uart_config(struct ar933x_pinctrl_priv *priv, int uart_id)
  35. {
  36. switch (uart_id) {
  37. case PERIPH_ID_UART0:
  38. clrsetbits_be32(priv->regs + AR71XX_GPIO_REG_OE,
  39. AR933X_GPIO(9), AR933X_GPIO(10));
  40. setbits_be32(priv->regs + AR71XX_GPIO_REG_FUNC,
  41. AR933X_GPIO_FUNC_UART_EN |
  42. AR933X_GPIO_FUNC_RES_TRUE);
  43. break;
  44. }
  45. }
  46. static int ar933x_pinctrl_request(struct udevice *dev, int func, int flags)
  47. {
  48. struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
  49. debug("%s: func=%x, flags=%x\n", __func__, func, flags);
  50. switch (func) {
  51. case PERIPH_ID_SPI0:
  52. pinctrl_ar933x_spi_config(priv, flags);
  53. break;
  54. case PERIPH_ID_UART0:
  55. pinctrl_ar933x_uart_config(priv, func);
  56. break;
  57. default:
  58. return -EINVAL;
  59. }
  60. return 0;
  61. }
  62. static int ar933x_pinctrl_get_periph_id(struct udevice *dev,
  63. struct udevice *periph)
  64. {
  65. u32 cell[2];
  66. int ret;
  67. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(periph),
  68. "interrupts", cell, ARRAY_SIZE(cell));
  69. if (ret < 0)
  70. return -EINVAL;
  71. switch (cell[0]) {
  72. case 128:
  73. return PERIPH_ID_UART0;
  74. case 129:
  75. return PERIPH_ID_SPI0;
  76. }
  77. return -ENOENT;
  78. }
  79. static int ar933x_pinctrl_set_state_simple(struct udevice *dev,
  80. struct udevice *periph)
  81. {
  82. int func;
  83. func = ar933x_pinctrl_get_periph_id(dev, periph);
  84. if (func < 0)
  85. return func;
  86. return ar933x_pinctrl_request(dev, func, 0);
  87. }
  88. static struct pinctrl_ops ar933x_pinctrl_ops = {
  89. .set_state_simple = ar933x_pinctrl_set_state_simple,
  90. .request = ar933x_pinctrl_request,
  91. .get_periph_id = ar933x_pinctrl_get_periph_id,
  92. };
  93. static int ar933x_pinctrl_probe(struct udevice *dev)
  94. {
  95. struct ar933x_pinctrl_priv *priv = dev_get_priv(dev);
  96. fdt_addr_t addr;
  97. addr = dev_read_addr(dev);
  98. if (addr == FDT_ADDR_T_NONE)
  99. return -EINVAL;
  100. priv->regs = map_physmem(addr,
  101. AR71XX_GPIO_SIZE,
  102. MAP_NOCACHE);
  103. return 0;
  104. }
  105. static const struct udevice_id ar933x_pinctrl_ids[] = {
  106. { .compatible = "qca,ar933x-pinctrl" },
  107. { }
  108. };
  109. U_BOOT_DRIVER(pinctrl_ar933x) = {
  110. .name = "pinctrl_ar933x",
  111. .id = UCLASS_PINCTRL,
  112. .of_match = ar933x_pinctrl_ids,
  113. .priv_auto_alloc_size = sizeof(struct ar933x_pinctrl_priv),
  114. .ops = &ar933x_pinctrl_ops,
  115. .probe = ar933x_pinctrl_probe,
  116. };