keystone_net.c 19 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Ethernet driver for TI K2HK EVM.
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <console.h>
  11. #include <linux/delay.h>
  12. #include <dm.h>
  13. #include <dm/lists.h>
  14. #include <net.h>
  15. #include <phy.h>
  16. #include <errno.h>
  17. #include <miiphy.h>
  18. #include <malloc.h>
  19. #include <asm/ti-common/keystone_nav.h>
  20. #include <asm/ti-common/keystone_net.h>
  21. #include <asm/ti-common/keystone_serdes.h>
  22. #include <asm/arch/psc_defs.h>
  23. #include <linux/libfdt.h>
  24. #include "cpsw_mdio.h"
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #ifdef KEYSTONE2_EMAC_GIG_ENABLE
  27. #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x)
  28. #else
  29. #define emac_gigabit_enable(x) /* no gigabit to enable */
  30. #endif
  31. #define RX_BUFF_NUMS 24
  32. #define RX_BUFF_LEN 1520
  33. #define MAX_SIZE_STREAM_BUFFER RX_BUFF_LEN
  34. #define SGMII_ANEG_TIMEOUT 4000
  35. static u8 rx_buffs[RX_BUFF_NUMS * RX_BUFF_LEN] __aligned(16);
  36. enum link_type {
  37. LINK_TYPE_SGMII_MAC_TO_MAC_AUTO = 0,
  38. LINK_TYPE_SGMII_MAC_TO_PHY_MODE = 1,
  39. LINK_TYPE_SGMII_MAC_TO_MAC_FORCED_MODE = 2,
  40. LINK_TYPE_SGMII_MAC_TO_FIBRE_MODE = 3,
  41. LINK_TYPE_SGMII_MAC_TO_PHY_NO_MDIO_MODE = 4,
  42. LINK_TYPE_RGMII_LINK_MAC_PHY = 5,
  43. LINK_TYPE_RGMII_LINK_MAC_MAC_FORCED = 6,
  44. LINK_TYPE_RGMII_LINK_MAC_PHY_NO_MDIO = 7,
  45. LINK_TYPE_10G_MAC_TO_PHY_MODE = 10,
  46. LINK_TYPE_10G_MAC_TO_MAC_FORCED_MODE = 11,
  47. };
  48. #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \
  49. ((mac)[2] << 16) | ((mac)[3] << 24))
  50. #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8))
  51. #ifdef CONFIG_KSNET_NETCP_V1_0
  52. #define EMAC_EMACSW_BASE_OFS 0x90800
  53. #define EMAC_EMACSW_PORT_BASE_OFS (EMAC_EMACSW_BASE_OFS + 0x60)
  54. /* CPSW Switch slave registers */
  55. #define CPGMACSL_REG_SA_LO 0x10
  56. #define CPGMACSL_REG_SA_HI 0x14
  57. #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
  58. (x) * 0x30)
  59. #elif defined(CONFIG_KSNET_NETCP_V1_5)
  60. #define EMAC_EMACSW_PORT_BASE_OFS 0x222000
  61. /* CPSW Switch slave registers */
  62. #define CPGMACSL_REG_SA_LO 0x308
  63. #define CPGMACSL_REG_SA_HI 0x30c
  64. #define DEVICE_EMACSW_BASE(base, x) ((base) + EMAC_EMACSW_PORT_BASE_OFS + \
  65. (x) * 0x1000)
  66. #endif
  67. struct ks2_eth_priv {
  68. struct udevice *dev;
  69. struct phy_device *phydev;
  70. struct mii_dev *mdio_bus;
  71. int phy_addr;
  72. phy_interface_t phy_if;
  73. int phy_of_handle;
  74. int sgmii_link_type;
  75. void *mdio_base;
  76. struct rx_buff_desc net_rx_buffs;
  77. struct pktdma_cfg *netcp_pktdma;
  78. void *hd;
  79. int slave_port;
  80. enum link_type link_type;
  81. bool emac_open;
  82. bool has_mdio;
  83. };
  84. static void __attribute__((unused))
  85. keystone2_eth_gigabit_enable(struct udevice *dev)
  86. {
  87. struct ks2_eth_priv *priv = dev_get_priv(dev);
  88. /*
  89. * Check if link detected is giga-bit
  90. * If Gigabit mode detected, enable gigbit in MAC
  91. */
  92. if (priv->has_mdio) {
  93. if (priv->phydev->speed != 1000)
  94. return;
  95. }
  96. writel(readl(DEVICE_EMACSL_BASE(priv->slave_port - 1) +
  97. CPGMACSL_REG_CTL) |
  98. EMAC_MACCONTROL_GIGFORCE | EMAC_MACCONTROL_GIGABIT_ENABLE,
  99. DEVICE_EMACSL_BASE(priv->slave_port - 1) + CPGMACSL_REG_CTL);
  100. }
  101. #ifdef CONFIG_SOC_K2G
  102. int keystone_rgmii_config(struct phy_device *phy_dev)
  103. {
  104. unsigned int i, status;
  105. i = 0;
  106. do {
  107. if (i > SGMII_ANEG_TIMEOUT) {
  108. puts(" TIMEOUT !\n");
  109. phy_dev->link = 0;
  110. return 0;
  111. }
  112. if (ctrlc()) {
  113. puts("user interrupt!\n");
  114. phy_dev->link = 0;
  115. return -EINTR;
  116. }
  117. if ((i++ % 500) == 0)
  118. printf(".");
  119. udelay(1000); /* 1 ms */
  120. status = readl(RGMII_STATUS_REG);
  121. } while (!(status & RGMII_REG_STATUS_LINK));
  122. puts(" done\n");
  123. return 0;
  124. }
  125. #else
  126. int keystone_sgmii_config(struct phy_device *phy_dev, int port, int interface)
  127. {
  128. unsigned int i, status, mask;
  129. unsigned int mr_adv_ability, control;
  130. switch (interface) {
  131. case SGMII_LINK_MAC_MAC_AUTONEG:
  132. mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
  133. SGMII_REG_MR_ADV_LINK |
  134. SGMII_REG_MR_ADV_FULL_DUPLEX |
  135. SGMII_REG_MR_ADV_GIG_MODE);
  136. control = (SGMII_REG_CONTROL_MASTER |
  137. SGMII_REG_CONTROL_AUTONEG);
  138. break;
  139. case SGMII_LINK_MAC_PHY:
  140. case SGMII_LINK_MAC_PHY_FORCED:
  141. mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
  142. control = SGMII_REG_CONTROL_AUTONEG;
  143. break;
  144. case SGMII_LINK_MAC_MAC_FORCED:
  145. mr_adv_ability = (SGMII_REG_MR_ADV_ENABLE |
  146. SGMII_REG_MR_ADV_LINK |
  147. SGMII_REG_MR_ADV_FULL_DUPLEX |
  148. SGMII_REG_MR_ADV_GIG_MODE);
  149. control = SGMII_REG_CONTROL_MASTER;
  150. break;
  151. case SGMII_LINK_MAC_FIBER:
  152. mr_adv_ability = 0x20;
  153. control = SGMII_REG_CONTROL_AUTONEG;
  154. break;
  155. default:
  156. mr_adv_ability = SGMII_REG_MR_ADV_ENABLE;
  157. control = SGMII_REG_CONTROL_AUTONEG;
  158. }
  159. __raw_writel(0, SGMII_CTL_REG(port));
  160. /*
  161. * Wait for the SerDes pll to lock,
  162. * but don't trap if lock is never read
  163. */
  164. for (i = 0; i < 1000; i++) {
  165. udelay(2000);
  166. status = __raw_readl(SGMII_STATUS_REG(port));
  167. if ((status & SGMII_REG_STATUS_LOCK) != 0)
  168. break;
  169. }
  170. __raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
  171. __raw_writel(control, SGMII_CTL_REG(port));
  172. mask = SGMII_REG_STATUS_LINK;
  173. if (control & SGMII_REG_CONTROL_AUTONEG)
  174. mask |= SGMII_REG_STATUS_AUTONEG;
  175. status = __raw_readl(SGMII_STATUS_REG(port));
  176. if ((status & mask) == mask)
  177. return 0;
  178. printf("\n%s Waiting for SGMII auto negotiation to complete",
  179. phy_dev->dev->name);
  180. while ((status & mask) != mask) {
  181. /*
  182. * Timeout reached ?
  183. */
  184. if (i > SGMII_ANEG_TIMEOUT) {
  185. puts(" TIMEOUT !\n");
  186. phy_dev->link = 0;
  187. return 0;
  188. }
  189. if (ctrlc()) {
  190. puts("user interrupt!\n");
  191. phy_dev->link = 0;
  192. return -EINTR;
  193. }
  194. if ((i++ % 500) == 0)
  195. printf(".");
  196. udelay(1000); /* 1 ms */
  197. status = __raw_readl(SGMII_STATUS_REG(port));
  198. }
  199. puts(" done\n");
  200. return 0;
  201. }
  202. #endif
  203. int mac_sl_reset(u32 port)
  204. {
  205. u32 i, v;
  206. if (port >= DEVICE_N_GMACSL_PORTS)
  207. return GMACSL_RET_INVALID_PORT;
  208. /* Set the soft reset bit */
  209. writel(CPGMAC_REG_RESET_VAL_RESET,
  210. DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
  211. /* Wait for the bit to clear */
  212. for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
  213. v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
  214. if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
  215. CPGMAC_REG_RESET_VAL_RESET)
  216. return GMACSL_RET_OK;
  217. }
  218. /* Timeout on the reset */
  219. return GMACSL_RET_WARN_RESET_INCOMPLETE;
  220. }
  221. int mac_sl_config(u_int16_t port, struct mac_sl_cfg *cfg)
  222. {
  223. u32 v, i;
  224. int ret = GMACSL_RET_OK;
  225. if (port >= DEVICE_N_GMACSL_PORTS)
  226. return GMACSL_RET_INVALID_PORT;
  227. if (cfg->max_rx_len > CPGMAC_REG_MAXLEN_LEN) {
  228. cfg->max_rx_len = CPGMAC_REG_MAXLEN_LEN;
  229. ret = GMACSL_RET_WARN_MAXLEN_TOO_BIG;
  230. }
  231. /* Must wait if the device is undergoing reset */
  232. for (i = 0; i < DEVICE_EMACSL_RESET_POLL_COUNT; i++) {
  233. v = readl(DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RESET);
  234. if ((v & CPGMAC_REG_RESET_VAL_RESET_MASK) !=
  235. CPGMAC_REG_RESET_VAL_RESET)
  236. break;
  237. }
  238. if (i == DEVICE_EMACSL_RESET_POLL_COUNT)
  239. return GMACSL_RET_CONFIG_FAIL_RESET_ACTIVE;
  240. writel(cfg->max_rx_len, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_MAXLEN);
  241. writel(cfg->ctl, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_CTL);
  242. #ifndef CONFIG_SOC_K2HK
  243. /* Map RX packet flow priority to 0 */
  244. writel(0, DEVICE_EMACSL_BASE(port) + CPGMACSL_REG_RX_PRI_MAP);
  245. #endif
  246. return ret;
  247. }
  248. int ethss_config(u32 ctl, u32 max_pkt_size)
  249. {
  250. u32 i;
  251. /* Max length register */
  252. writel(max_pkt_size, DEVICE_CPSW_BASE + CPSW_REG_MAXLEN);
  253. /* Control register */
  254. writel(ctl, DEVICE_CPSW_BASE + CPSW_REG_CTL);
  255. /* All statistics enabled by default */
  256. writel(CPSW_REG_VAL_STAT_ENABLE_ALL,
  257. DEVICE_CPSW_BASE + CPSW_REG_STAT_PORT_EN);
  258. /* Reset and enable the ALE */
  259. writel(CPSW_REG_VAL_ALE_CTL_RESET_AND_ENABLE |
  260. CPSW_REG_VAL_ALE_CTL_BYPASS,
  261. DEVICE_CPSW_BASE + CPSW_REG_ALE_CONTROL);
  262. /* All ports put into forward mode */
  263. for (i = 0; i < DEVICE_CPSW_NUM_PORTS; i++)
  264. writel(CPSW_REG_VAL_PORTCTL_FORWARD_MODE,
  265. DEVICE_CPSW_BASE + CPSW_REG_ALE_PORTCTL(i));
  266. return 0;
  267. }
  268. int ethss_start(void)
  269. {
  270. int i;
  271. struct mac_sl_cfg cfg;
  272. cfg.max_rx_len = MAX_SIZE_STREAM_BUFFER;
  273. cfg.ctl = GMACSL_ENABLE | GMACSL_RX_ENABLE_EXT_CTL;
  274. for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++) {
  275. mac_sl_reset(i);
  276. mac_sl_config(i, &cfg);
  277. }
  278. return 0;
  279. }
  280. int ethss_stop(void)
  281. {
  282. int i;
  283. for (i = 0; i < DEVICE_N_GMACSL_PORTS; i++)
  284. mac_sl_reset(i);
  285. return 0;
  286. }
  287. struct ks2_serdes ks2_serdes_sgmii_156p25mhz = {
  288. .clk = SERDES_CLOCK_156P25M,
  289. .rate = SERDES_RATE_5G,
  290. .rate_mode = SERDES_QUARTER_RATE,
  291. .intf = SERDES_PHY_SGMII,
  292. .loopback = 0,
  293. };
  294. #ifndef CONFIG_SOC_K2G
  295. static void keystone2_net_serdes_setup(void)
  296. {
  297. ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII_BASE,
  298. &ks2_serdes_sgmii_156p25mhz,
  299. CONFIG_KSNET_SERDES_LANES_PER_SGMII);
  300. #if defined(CONFIG_SOC_K2E) || defined(CONFIG_SOC_K2L)
  301. ks2_serdes_init(CONFIG_KSNET_SERDES_SGMII2_BASE,
  302. &ks2_serdes_sgmii_156p25mhz,
  303. CONFIG_KSNET_SERDES_LANES_PER_SGMII);
  304. #endif
  305. /* wait till setup */
  306. udelay(5000);
  307. }
  308. #endif
  309. static int ks2_eth_start(struct udevice *dev)
  310. {
  311. struct ks2_eth_priv *priv = dev_get_priv(dev);
  312. #ifdef CONFIG_SOC_K2G
  313. keystone_rgmii_config(priv->phydev);
  314. #else
  315. keystone_sgmii_config(priv->phydev, priv->slave_port - 1,
  316. priv->sgmii_link_type);
  317. #endif
  318. udelay(10000);
  319. /* On chip switch configuration */
  320. ethss_config(target_get_switch_ctl(), SWITCH_MAX_PKT_SIZE);
  321. qm_init();
  322. if (ksnav_init(priv->netcp_pktdma, &priv->net_rx_buffs)) {
  323. pr_err("ksnav_init failed\n");
  324. goto err_knav_init;
  325. }
  326. /*
  327. * Streaming switch configuration. If not present this
  328. * statement is defined to void in target.h.
  329. * If present this is usually defined to a series of register writes
  330. */
  331. hw_config_streaming_switch();
  332. if (priv->has_mdio) {
  333. phy_startup(priv->phydev);
  334. if (priv->phydev->link == 0) {
  335. pr_err("phy startup failed\n");
  336. goto err_phy_start;
  337. }
  338. }
  339. emac_gigabit_enable(dev);
  340. ethss_start();
  341. priv->emac_open = true;
  342. return 0;
  343. err_phy_start:
  344. ksnav_close(priv->netcp_pktdma);
  345. err_knav_init:
  346. qm_close();
  347. return -EFAULT;
  348. }
  349. static int ks2_eth_send(struct udevice *dev, void *packet, int length)
  350. {
  351. struct ks2_eth_priv *priv = dev_get_priv(dev);
  352. genphy_update_link(priv->phydev);
  353. if (priv->phydev->link == 0)
  354. return -1;
  355. if (length < EMAC_MIN_ETHERNET_PKT_SIZE)
  356. length = EMAC_MIN_ETHERNET_PKT_SIZE;
  357. return ksnav_send(priv->netcp_pktdma, (u32 *)packet,
  358. length, (priv->slave_port) << 16);
  359. }
  360. static int ks2_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  361. {
  362. struct ks2_eth_priv *priv = dev_get_priv(dev);
  363. int pkt_size;
  364. u32 *pkt = NULL;
  365. priv->hd = ksnav_recv(priv->netcp_pktdma, &pkt, &pkt_size);
  366. if (priv->hd == NULL)
  367. return -EAGAIN;
  368. *packetp = (uchar *)pkt;
  369. return pkt_size;
  370. }
  371. static int ks2_eth_free_pkt(struct udevice *dev, uchar *packet,
  372. int length)
  373. {
  374. struct ks2_eth_priv *priv = dev_get_priv(dev);
  375. ksnav_release_rxhd(priv->netcp_pktdma, priv->hd);
  376. return 0;
  377. }
  378. static void ks2_eth_stop(struct udevice *dev)
  379. {
  380. struct ks2_eth_priv *priv = dev_get_priv(dev);
  381. if (!priv->emac_open)
  382. return;
  383. ethss_stop();
  384. ksnav_close(priv->netcp_pktdma);
  385. qm_close();
  386. phy_shutdown(priv->phydev);
  387. priv->emac_open = false;
  388. }
  389. int ks2_eth_read_rom_hwaddr(struct udevice *dev)
  390. {
  391. struct ks2_eth_priv *priv = dev_get_priv(dev);
  392. struct eth_pdata *pdata = dev_get_platdata(dev);
  393. u32 maca = 0;
  394. u32 macb = 0;
  395. /* Read the e-fuse mac address */
  396. if (priv->slave_port == 1) {
  397. maca = __raw_readl(MAC_ID_BASE_ADDR);
  398. macb = __raw_readl(MAC_ID_BASE_ADDR + 4);
  399. }
  400. pdata->enetaddr[0] = (macb >> 8) & 0xff;
  401. pdata->enetaddr[1] = (macb >> 0) & 0xff;
  402. pdata->enetaddr[2] = (maca >> 24) & 0xff;
  403. pdata->enetaddr[3] = (maca >> 16) & 0xff;
  404. pdata->enetaddr[4] = (maca >> 8) & 0xff;
  405. pdata->enetaddr[5] = (maca >> 0) & 0xff;
  406. return 0;
  407. }
  408. int ks2_eth_write_hwaddr(struct udevice *dev)
  409. {
  410. struct ks2_eth_priv *priv = dev_get_priv(dev);
  411. struct eth_pdata *pdata = dev_get_platdata(dev);
  412. writel(mac_hi(pdata->enetaddr),
  413. DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
  414. CPGMACSL_REG_SA_HI);
  415. writel(mac_lo(pdata->enetaddr),
  416. DEVICE_EMACSW_BASE(pdata->iobase, priv->slave_port - 1) +
  417. CPGMACSL_REG_SA_LO);
  418. return 0;
  419. }
  420. static int ks2_eth_probe(struct udevice *dev)
  421. {
  422. struct ks2_eth_priv *priv = dev_get_priv(dev);
  423. struct mii_dev *mdio_bus;
  424. priv->dev = dev;
  425. priv->emac_open = false;
  426. /* These clock enables has to be moved to common location */
  427. if (cpu_is_k2g())
  428. writel(KS2_ETHERNET_RGMII, KS2_ETHERNET_CFG);
  429. /* By default, select PA PLL clock as PA clock source */
  430. #ifndef CONFIG_SOC_K2G
  431. if (psc_enable_module(KS2_LPSC_PA))
  432. return -EACCES;
  433. #endif
  434. if (psc_enable_module(KS2_LPSC_CPGMAC))
  435. return -EACCES;
  436. if (psc_enable_module(KS2_LPSC_CRYPTO))
  437. return -EACCES;
  438. if (cpu_is_k2e() || cpu_is_k2l())
  439. pll_pa_clk_sel();
  440. priv->net_rx_buffs.buff_ptr = rx_buffs;
  441. priv->net_rx_buffs.num_buffs = RX_BUFF_NUMS;
  442. priv->net_rx_buffs.buff_len = RX_BUFF_LEN;
  443. if (priv->slave_port == 1) {
  444. #ifndef CONFIG_SOC_K2G
  445. keystone2_net_serdes_setup();
  446. #endif
  447. /*
  448. * Register MDIO bus for slave 0 only, other slave have
  449. * to re-use the same
  450. */
  451. mdio_bus = cpsw_mdio_init("ethernet-mdio",
  452. (u32)priv->mdio_base,
  453. EMAC_MDIO_CLOCK_FREQ,
  454. EMAC_MDIO_BUS_FREQ);
  455. if (!mdio_bus) {
  456. pr_err("MDIO alloc failed\n");
  457. return -ENOMEM;
  458. }
  459. priv->mdio_bus = mdio_bus;
  460. } else {
  461. /* Get the MDIO bus from slave 0 device */
  462. struct ks2_eth_priv *parent_priv;
  463. parent_priv = dev_get_priv(dev->parent);
  464. priv->mdio_bus = parent_priv->mdio_bus;
  465. priv->mdio_base = parent_priv->mdio_base;
  466. }
  467. priv->netcp_pktdma = &netcp_pktdma;
  468. if (priv->has_mdio) {
  469. priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
  470. dev, priv->phy_if);
  471. #ifdef CONFIG_DM_ETH
  472. if (priv->phy_of_handle)
  473. priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
  474. #endif
  475. phy_config(priv->phydev);
  476. }
  477. return 0;
  478. }
  479. int ks2_eth_remove(struct udevice *dev)
  480. {
  481. struct ks2_eth_priv *priv = dev_get_priv(dev);
  482. cpsw_mdio_free(priv->mdio_bus);
  483. return 0;
  484. }
  485. static const struct eth_ops ks2_eth_ops = {
  486. .start = ks2_eth_start,
  487. .send = ks2_eth_send,
  488. .recv = ks2_eth_recv,
  489. .free_pkt = ks2_eth_free_pkt,
  490. .stop = ks2_eth_stop,
  491. .read_rom_hwaddr = ks2_eth_read_rom_hwaddr,
  492. .write_hwaddr = ks2_eth_write_hwaddr,
  493. };
  494. static int ks2_eth_bind_slaves(struct udevice *dev, int gbe, int *gbe_0)
  495. {
  496. const void *fdt = gd->fdt_blob;
  497. struct udevice *sl_dev;
  498. int interfaces;
  499. int sec_slave;
  500. int slave;
  501. int ret;
  502. char *slave_name;
  503. interfaces = fdt_subnode_offset(fdt, gbe, "interfaces");
  504. fdt_for_each_subnode(slave, fdt, interfaces) {
  505. int slave_no;
  506. slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
  507. if (slave_no == -ENOENT)
  508. continue;
  509. if (slave_no == 0) {
  510. /* This is the current eth device */
  511. *gbe_0 = slave;
  512. } else {
  513. /* Slave devices to be registered */
  514. slave_name = malloc(20);
  515. snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
  516. ret = device_bind_driver_to_node(dev, "eth_ks2_sl",
  517. slave_name, offset_to_ofnode(slave),
  518. &sl_dev);
  519. if (ret) {
  520. pr_err("ks2_net - not able to bind slave interfaces\n");
  521. return ret;
  522. }
  523. }
  524. }
  525. sec_slave = fdt_subnode_offset(fdt, gbe, "secondary-slave-ports");
  526. fdt_for_each_subnode(slave, fdt, sec_slave) {
  527. int slave_no;
  528. slave_no = fdtdec_get_int(fdt, slave, "slave-port", -ENOENT);
  529. if (slave_no == -ENOENT)
  530. continue;
  531. /* Slave devices to be registered */
  532. slave_name = malloc(20);
  533. snprintf(slave_name, 20, "netcp@slave-%d", slave_no);
  534. ret = device_bind_driver_to_node(dev, "eth_ks2_sl", slave_name,
  535. offset_to_ofnode(slave), &sl_dev);
  536. if (ret) {
  537. pr_err("ks2_net - not able to bind slave interfaces\n");
  538. return ret;
  539. }
  540. }
  541. return 0;
  542. }
  543. static int ks2_eth_parse_slave_interface(int netcp, int slave,
  544. struct ks2_eth_priv *priv,
  545. struct eth_pdata *pdata)
  546. {
  547. const void *fdt = gd->fdt_blob;
  548. int mdio;
  549. int phy;
  550. int dma_count;
  551. u32 dma_channel[8];
  552. const char *phy_mode;
  553. priv->slave_port = fdtdec_get_int(fdt, slave, "slave-port", -1);
  554. priv->net_rx_buffs.rx_flow = priv->slave_port * 8;
  555. /* U-Boot slave port number starts with 1 instead of 0 */
  556. priv->slave_port += 1;
  557. dma_count = fdtdec_get_int_array_count(fdt, netcp,
  558. "ti,navigator-dmas",
  559. dma_channel, 8);
  560. if (dma_count > (2 * priv->slave_port)) {
  561. int dma_idx;
  562. dma_idx = priv->slave_port * 2 - 1;
  563. priv->net_rx_buffs.rx_flow = dma_channel[dma_idx];
  564. }
  565. priv->link_type = fdtdec_get_int(fdt, slave, "link-interface", -1);
  566. phy = fdtdec_lookup_phandle(fdt, slave, "phy-handle");
  567. if (phy >= 0) {
  568. priv->phy_of_handle = phy;
  569. priv->phy_addr = fdtdec_get_int(fdt, phy, "reg", -1);
  570. mdio = fdt_parent_offset(fdt, phy);
  571. if (mdio < 0) {
  572. pr_err("mdio dt not found\n");
  573. return -ENODEV;
  574. }
  575. priv->mdio_base = (void *)fdtdec_get_addr(fdt, mdio, "reg");
  576. }
  577. if (priv->link_type == LINK_TYPE_SGMII_MAC_TO_PHY_MODE) {
  578. priv->phy_if = PHY_INTERFACE_MODE_SGMII;
  579. pdata->phy_interface = priv->phy_if;
  580. priv->sgmii_link_type = SGMII_LINK_MAC_PHY;
  581. priv->has_mdio = true;
  582. } else if (priv->link_type == LINK_TYPE_RGMII_LINK_MAC_PHY) {
  583. phy_mode = fdt_getprop(fdt, slave, "phy-mode", NULL);
  584. if (phy_mode) {
  585. priv->phy_if = phy_get_interface_by_name(phy_mode);
  586. if (priv->phy_if != PHY_INTERFACE_MODE_RGMII &&
  587. priv->phy_if != PHY_INTERFACE_MODE_RGMII_ID &&
  588. priv->phy_if != PHY_INTERFACE_MODE_RGMII_RXID &&
  589. priv->phy_if != PHY_INTERFACE_MODE_RGMII_TXID) {
  590. pr_err("invalid phy-mode\n");
  591. return -EINVAL;
  592. }
  593. } else {
  594. priv->phy_if = PHY_INTERFACE_MODE_RGMII;
  595. }
  596. pdata->phy_interface = priv->phy_if;
  597. priv->has_mdio = true;
  598. }
  599. return 0;
  600. }
  601. static int ks2_sl_eth_ofdata_to_platdata(struct udevice *dev)
  602. {
  603. struct ks2_eth_priv *priv = dev_get_priv(dev);
  604. struct eth_pdata *pdata = dev_get_platdata(dev);
  605. const void *fdt = gd->fdt_blob;
  606. int slave = dev_of_offset(dev);
  607. int interfaces;
  608. int gbe;
  609. int netcp_devices;
  610. int netcp;
  611. interfaces = fdt_parent_offset(fdt, slave);
  612. gbe = fdt_parent_offset(fdt, interfaces);
  613. netcp_devices = fdt_parent_offset(fdt, gbe);
  614. netcp = fdt_parent_offset(fdt, netcp_devices);
  615. ks2_eth_parse_slave_interface(netcp, slave, priv, pdata);
  616. pdata->iobase = fdtdec_get_addr(fdt, netcp, "reg");
  617. return 0;
  618. }
  619. static int ks2_eth_ofdata_to_platdata(struct udevice *dev)
  620. {
  621. struct ks2_eth_priv *priv = dev_get_priv(dev);
  622. struct eth_pdata *pdata = dev_get_platdata(dev);
  623. const void *fdt = gd->fdt_blob;
  624. int gbe_0 = -ENODEV;
  625. int netcp_devices;
  626. int gbe;
  627. netcp_devices = fdt_subnode_offset(fdt, dev_of_offset(dev),
  628. "netcp-devices");
  629. gbe = fdt_subnode_offset(fdt, netcp_devices, "gbe");
  630. ks2_eth_bind_slaves(dev, gbe, &gbe_0);
  631. ks2_eth_parse_slave_interface(dev_of_offset(dev), gbe_0, priv, pdata);
  632. pdata->iobase = dev_read_addr(dev);
  633. return 0;
  634. }
  635. static const struct udevice_id ks2_eth_ids[] = {
  636. { .compatible = "ti,netcp-1.0" },
  637. { }
  638. };
  639. U_BOOT_DRIVER(eth_ks2_slave) = {
  640. .name = "eth_ks2_sl",
  641. .id = UCLASS_ETH,
  642. .ofdata_to_platdata = ks2_sl_eth_ofdata_to_platdata,
  643. .probe = ks2_eth_probe,
  644. .remove = ks2_eth_remove,
  645. .ops = &ks2_eth_ops,
  646. .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
  647. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  648. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  649. };
  650. U_BOOT_DRIVER(eth_ks2) = {
  651. .name = "eth_ks2",
  652. .id = UCLASS_ETH,
  653. .of_match = ks2_eth_ids,
  654. .ofdata_to_platdata = ks2_eth_ofdata_to_platdata,
  655. .probe = ks2_eth_probe,
  656. .remove = ks2_eth_remove,
  657. .ops = &ks2_eth_ops,
  658. .priv_auto_alloc_size = sizeof(struct ks2_eth_priv),
  659. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  660. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  661. };