sun8i_emac.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. * Author: Amit Singh Tomar, amittomer25@gmail.com
  5. *
  6. * Ethernet driver for H3/A64/A83T based SoC's
  7. *
  8. * It is derived from the work done by
  9. * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
  10. *
  11. */
  12. #include <cpu_func.h>
  13. #include <log.h>
  14. #include <asm/cache.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/gpio.h>
  18. #include <common.h>
  19. #include <clk.h>
  20. #include <dm.h>
  21. #include <fdt_support.h>
  22. #include <dm/device_compat.h>
  23. #include <linux/bitops.h>
  24. #include <linux/delay.h>
  25. #include <linux/err.h>
  26. #include <malloc.h>
  27. #include <miiphy.h>
  28. #include <net.h>
  29. #include <reset.h>
  30. #include <dt-bindings/pinctrl/sun4i-a10.h>
  31. #if CONFIG_IS_ENABLED(DM_GPIO)
  32. #include <asm-generic/gpio.h>
  33. #endif
  34. #define MDIO_CMD_MII_BUSY BIT(0)
  35. #define MDIO_CMD_MII_WRITE BIT(1)
  36. #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
  37. #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
  38. #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
  39. #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
  40. #define CONFIG_TX_DESCR_NUM 32
  41. #define CONFIG_RX_DESCR_NUM 32
  42. #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
  43. /*
  44. * The datasheet says that each descriptor can transfers up to 4096 bytes
  45. * But later, the register documentation reduces that value to 2048,
  46. * using 2048 cause strange behaviours and even BSP driver use 2047
  47. */
  48. #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
  49. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  50. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  51. #define H3_EPHY_DEFAULT_VALUE 0x58000
  52. #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
  53. #define H3_EPHY_ADDR_SHIFT 20
  54. #define REG_PHY_ADDR_MASK GENMASK(4, 0)
  55. #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
  56. #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
  57. #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
  58. #define SC_RMII_EN BIT(13)
  59. #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
  60. #define SC_ETCS_MASK GENMASK(1, 0)
  61. #define SC_ETCS_EXT_GMII 0x1
  62. #define SC_ETCS_INT_GMII 0x2
  63. #define SC_ETXDC_MASK GENMASK(12, 10)
  64. #define SC_ETXDC_OFFSET 10
  65. #define SC_ERXDC_MASK GENMASK(9, 5)
  66. #define SC_ERXDC_OFFSET 5
  67. #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
  68. #define AHB_GATE_OFFSET_EPHY 0
  69. /* IO mux settings */
  70. #define SUN8I_IOMUX_H3 2
  71. #define SUN8I_IOMUX_R40 5
  72. #define SUN8I_IOMUX 4
  73. /* H3/A64 EMAC Register's offset */
  74. #define EMAC_CTL0 0x00
  75. #define EMAC_CTL1 0x04
  76. #define EMAC_INT_STA 0x08
  77. #define EMAC_INT_EN 0x0c
  78. #define EMAC_TX_CTL0 0x10
  79. #define EMAC_TX_CTL1 0x14
  80. #define EMAC_TX_FLOW_CTL 0x1c
  81. #define EMAC_TX_DMA_DESC 0x20
  82. #define EMAC_RX_CTL0 0x24
  83. #define EMAC_RX_CTL1 0x28
  84. #define EMAC_RX_DMA_DESC 0x34
  85. #define EMAC_MII_CMD 0x48
  86. #define EMAC_MII_DATA 0x4c
  87. #define EMAC_ADDR0_HIGH 0x50
  88. #define EMAC_ADDR0_LOW 0x54
  89. #define EMAC_TX_DMA_STA 0xb0
  90. #define EMAC_TX_CUR_DESC 0xb4
  91. #define EMAC_TX_CUR_BUF 0xb8
  92. #define EMAC_RX_DMA_STA 0xc0
  93. #define EMAC_RX_CUR_DESC 0xc4
  94. DECLARE_GLOBAL_DATA_PTR;
  95. enum emac_variant {
  96. A83T_EMAC = 1,
  97. H3_EMAC,
  98. A64_EMAC,
  99. R40_GMAC,
  100. H6_EMAC,
  101. };
  102. struct emac_dma_desc {
  103. u32 status;
  104. u32 st;
  105. u32 buf_addr;
  106. u32 next;
  107. } __aligned(ARCH_DMA_MINALIGN);
  108. struct emac_eth_dev {
  109. struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
  110. struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
  111. char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  112. char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  113. u32 interface;
  114. u32 phyaddr;
  115. u32 link;
  116. u32 speed;
  117. u32 duplex;
  118. u32 phy_configured;
  119. u32 tx_currdescnum;
  120. u32 rx_currdescnum;
  121. u32 addr;
  122. u32 tx_slot;
  123. bool use_internal_phy;
  124. enum emac_variant variant;
  125. void *mac_reg;
  126. phys_addr_t sysctl_reg;
  127. struct phy_device *phydev;
  128. struct mii_dev *bus;
  129. struct clk tx_clk;
  130. struct clk ephy_clk;
  131. struct reset_ctl tx_rst;
  132. struct reset_ctl ephy_rst;
  133. #if CONFIG_IS_ENABLED(DM_GPIO)
  134. struct gpio_desc reset_gpio;
  135. #endif
  136. };
  137. struct sun8i_eth_pdata {
  138. struct eth_pdata eth_pdata;
  139. u32 reset_delays[3];
  140. int tx_delay_ps;
  141. int rx_delay_ps;
  142. };
  143. static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  144. {
  145. struct udevice *dev = bus->priv;
  146. struct emac_eth_dev *priv = dev_get_priv(dev);
  147. ulong start;
  148. u32 miiaddr = 0;
  149. int timeout = CONFIG_MDIO_TIMEOUT;
  150. miiaddr &= ~MDIO_CMD_MII_WRITE;
  151. miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  152. miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  153. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  154. miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
  155. miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  156. MDIO_CMD_MII_PHY_ADDR_MASK;
  157. miiaddr |= MDIO_CMD_MII_BUSY;
  158. writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
  159. start = get_timer(0);
  160. while (get_timer(start) < timeout) {
  161. if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
  162. return readl(priv->mac_reg + EMAC_MII_DATA);
  163. udelay(10);
  164. };
  165. return -1;
  166. }
  167. static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  168. u16 val)
  169. {
  170. struct udevice *dev = bus->priv;
  171. struct emac_eth_dev *priv = dev_get_priv(dev);
  172. ulong start;
  173. u32 miiaddr = 0;
  174. int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
  175. miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  176. miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
  177. MDIO_CMD_MII_PHY_REG_ADDR_MASK;
  178. miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
  179. miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
  180. MDIO_CMD_MII_PHY_ADDR_MASK;
  181. miiaddr |= MDIO_CMD_MII_WRITE;
  182. miiaddr |= MDIO_CMD_MII_BUSY;
  183. writel(val, priv->mac_reg + EMAC_MII_DATA);
  184. writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
  185. start = get_timer(0);
  186. while (get_timer(start) < timeout) {
  187. if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
  188. MDIO_CMD_MII_BUSY)) {
  189. ret = 0;
  190. break;
  191. }
  192. udelay(10);
  193. };
  194. return ret;
  195. }
  196. static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
  197. {
  198. u32 macid_lo, macid_hi;
  199. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  200. (mac_id[3] << 24);
  201. macid_hi = mac_id[4] + (mac_id[5] << 8);
  202. writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
  203. writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
  204. return 0;
  205. }
  206. static void sun8i_adjust_link(struct emac_eth_dev *priv,
  207. struct phy_device *phydev)
  208. {
  209. u32 v;
  210. v = readl(priv->mac_reg + EMAC_CTL0);
  211. if (phydev->duplex)
  212. v |= BIT(0);
  213. else
  214. v &= ~BIT(0);
  215. v &= ~0x0C;
  216. switch (phydev->speed) {
  217. case 1000:
  218. break;
  219. case 100:
  220. v |= BIT(2);
  221. v |= BIT(3);
  222. break;
  223. case 10:
  224. v |= BIT(3);
  225. break;
  226. }
  227. writel(v, priv->mac_reg + EMAC_CTL0);
  228. }
  229. static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
  230. {
  231. if (priv->use_internal_phy) {
  232. /* H3 based SoC's that has an Internal 100MBit PHY
  233. * needs to be configured and powered up before use
  234. */
  235. *reg &= ~H3_EPHY_DEFAULT_MASK;
  236. *reg |= H3_EPHY_DEFAULT_VALUE;
  237. *reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
  238. *reg &= ~H3_EPHY_SHUTDOWN;
  239. *reg |= H3_EPHY_SELECT;
  240. } else
  241. /* This is to select External Gigabit PHY on
  242. * the boards with H3 SoC.
  243. */
  244. *reg &= ~H3_EPHY_SELECT;
  245. return 0;
  246. }
  247. static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
  248. struct emac_eth_dev *priv)
  249. {
  250. int ret;
  251. u32 reg;
  252. if (priv->variant == R40_GMAC) {
  253. /* Select RGMII for R40 */
  254. reg = readl(priv->sysctl_reg + 0x164);
  255. reg |= SC_ETCS_INT_GMII |
  256. SC_EPIT |
  257. (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
  258. writel(reg, priv->sysctl_reg + 0x164);
  259. return 0;
  260. }
  261. reg = readl(priv->sysctl_reg + 0x30);
  262. if (priv->variant == H3_EMAC || priv->variant == H6_EMAC) {
  263. ret = sun8i_emac_set_syscon_ephy(priv, &reg);
  264. if (ret)
  265. return ret;
  266. }
  267. reg &= ~(SC_ETCS_MASK | SC_EPIT);
  268. if (priv->variant == H3_EMAC ||
  269. priv->variant == A64_EMAC ||
  270. priv->variant == H6_EMAC)
  271. reg &= ~SC_RMII_EN;
  272. switch (priv->interface) {
  273. case PHY_INTERFACE_MODE_MII:
  274. /* default */
  275. break;
  276. case PHY_INTERFACE_MODE_RGMII:
  277. reg |= SC_EPIT | SC_ETCS_INT_GMII;
  278. break;
  279. case PHY_INTERFACE_MODE_RMII:
  280. if (priv->variant == H3_EMAC ||
  281. priv->variant == A64_EMAC ||
  282. priv->variant == H6_EMAC) {
  283. reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
  284. break;
  285. }
  286. /* RMII not supported on A83T */
  287. default:
  288. debug("%s: Invalid PHY interface\n", __func__);
  289. return -EINVAL;
  290. }
  291. if (pdata->tx_delay_ps)
  292. reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
  293. & SC_ETXDC_MASK;
  294. if (pdata->rx_delay_ps)
  295. reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
  296. & SC_ERXDC_MASK;
  297. writel(reg, priv->sysctl_reg + 0x30);
  298. return 0;
  299. }
  300. static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
  301. {
  302. struct phy_device *phydev;
  303. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  304. if (!phydev)
  305. return -ENODEV;
  306. phy_connect_dev(phydev, dev);
  307. priv->phydev = phydev;
  308. phy_config(priv->phydev);
  309. return 0;
  310. }
  311. static void rx_descs_init(struct emac_eth_dev *priv)
  312. {
  313. struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
  314. char *rxbuffs = &priv->rxbuffer[0];
  315. struct emac_dma_desc *desc_p;
  316. u32 idx;
  317. /* flush Rx buffers */
  318. flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
  319. RX_TOTAL_BUFSIZE);
  320. for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  321. desc_p = &desc_table_p[idx];
  322. desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
  323. ;
  324. desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
  325. desc_p->st |= CONFIG_ETH_RXSIZE;
  326. desc_p->status = BIT(31);
  327. }
  328. /* Correcting the last pointer of the chain */
  329. desc_p->next = (uintptr_t)&desc_table_p[0];
  330. flush_dcache_range((uintptr_t)priv->rx_chain,
  331. (uintptr_t)priv->rx_chain +
  332. sizeof(priv->rx_chain));
  333. writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
  334. priv->rx_currdescnum = 0;
  335. }
  336. static void tx_descs_init(struct emac_eth_dev *priv)
  337. {
  338. struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
  339. char *txbuffs = &priv->txbuffer[0];
  340. struct emac_dma_desc *desc_p;
  341. u32 idx;
  342. for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  343. desc_p = &desc_table_p[idx];
  344. desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
  345. ;
  346. desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
  347. desc_p->status = (1 << 31);
  348. desc_p->st = 0;
  349. }
  350. /* Correcting the last pointer of the chain */
  351. desc_p->next = (uintptr_t)&desc_table_p[0];
  352. /* Flush all Tx buffer descriptors */
  353. flush_dcache_range((uintptr_t)priv->tx_chain,
  354. (uintptr_t)priv->tx_chain +
  355. sizeof(priv->tx_chain));
  356. writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
  357. priv->tx_currdescnum = 0;
  358. }
  359. static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
  360. {
  361. u32 reg, v;
  362. int timeout = 100;
  363. reg = readl((priv->mac_reg + EMAC_CTL1));
  364. if (!(reg & 0x1)) {
  365. /* Soft reset MAC */
  366. setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
  367. do {
  368. reg = readl(priv->mac_reg + EMAC_CTL1);
  369. } while ((reg & 0x01) != 0 && (--timeout));
  370. if (!timeout) {
  371. printf("%s: Timeout\n", __func__);
  372. return -1;
  373. }
  374. }
  375. /* Rewrite mac address after reset */
  376. _sun8i_write_hwaddr(priv, enetaddr);
  377. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  378. /* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
  379. v |= BIT(1);
  380. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  381. v = readl(priv->mac_reg + EMAC_RX_CTL1);
  382. /* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
  383. * complete frame has been written to RX DMA FIFO
  384. */
  385. v |= BIT(1);
  386. writel(v, priv->mac_reg + EMAC_RX_CTL1);
  387. /* DMA */
  388. writel(8 << 24, priv->mac_reg + EMAC_CTL1);
  389. /* Initialize rx/tx descriptors */
  390. rx_descs_init(priv);
  391. tx_descs_init(priv);
  392. /* PHY Start Up */
  393. phy_startup(priv->phydev);
  394. sun8i_adjust_link(priv, priv->phydev);
  395. /* Start RX DMA */
  396. v = readl(priv->mac_reg + EMAC_RX_CTL1);
  397. v |= BIT(30);
  398. writel(v, priv->mac_reg + EMAC_RX_CTL1);
  399. /* Start TX DMA */
  400. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  401. v |= BIT(30);
  402. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  403. /* Enable RX/TX */
  404. setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
  405. setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
  406. return 0;
  407. }
  408. static int parse_phy_pins(struct udevice *dev)
  409. {
  410. struct emac_eth_dev *priv = dev_get_priv(dev);
  411. int offset;
  412. const char *pin_name;
  413. int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
  414. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
  415. "pinctrl-0");
  416. if (offset < 0) {
  417. printf("WARNING: emac: cannot find pinctrl-0 node\n");
  418. return offset;
  419. }
  420. drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
  421. "drive-strength", ~0);
  422. if (drive != ~0) {
  423. if (drive <= 10)
  424. drive = SUN4I_PINCTRL_10_MA;
  425. else if (drive <= 20)
  426. drive = SUN4I_PINCTRL_20_MA;
  427. else if (drive <= 30)
  428. drive = SUN4I_PINCTRL_30_MA;
  429. else
  430. drive = SUN4I_PINCTRL_40_MA;
  431. }
  432. if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
  433. pull = SUN4I_PINCTRL_PULL_UP;
  434. else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
  435. pull = SUN4I_PINCTRL_PULL_DOWN;
  436. for (i = 0; ; i++) {
  437. int pin;
  438. pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
  439. "pins", i, NULL);
  440. if (!pin_name)
  441. break;
  442. pin = sunxi_name_to_gpio(pin_name);
  443. if (pin < 0)
  444. continue;
  445. if (priv->variant == H3_EMAC)
  446. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3);
  447. else if (priv->variant == R40_GMAC || priv->variant == H6_EMAC)
  448. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40);
  449. else
  450. sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX);
  451. if (drive != ~0)
  452. sunxi_gpio_set_drv(pin, drive);
  453. if (pull != ~0)
  454. sunxi_gpio_set_pull(pin, pull);
  455. }
  456. if (!i) {
  457. printf("WARNING: emac: cannot find pins property\n");
  458. return -2;
  459. }
  460. return 0;
  461. }
  462. static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
  463. {
  464. u32 status, desc_num = priv->rx_currdescnum;
  465. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  466. int length = -EAGAIN;
  467. int good_packet = 1;
  468. uintptr_t desc_start = (uintptr_t)desc_p;
  469. uintptr_t desc_end = desc_start +
  470. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  471. ulong data_start = (uintptr_t)desc_p->buf_addr;
  472. ulong data_end;
  473. /* Invalidate entire buffer descriptor */
  474. invalidate_dcache_range(desc_start, desc_end);
  475. status = desc_p->status;
  476. /* Check for DMA own bit */
  477. if (!(status & BIT(31))) {
  478. length = (desc_p->status >> 16) & 0x3FFF;
  479. if (length < 0x40) {
  480. good_packet = 0;
  481. debug("RX: Bad Packet (runt)\n");
  482. }
  483. data_end = data_start + length;
  484. /* Invalidate received data */
  485. invalidate_dcache_range(rounddown(data_start,
  486. ARCH_DMA_MINALIGN),
  487. roundup(data_end,
  488. ARCH_DMA_MINALIGN));
  489. if (good_packet) {
  490. if (length > CONFIG_ETH_RXSIZE) {
  491. printf("Received packet is too big (len=%d)\n",
  492. length);
  493. return -EMSGSIZE;
  494. }
  495. *packetp = (uchar *)(ulong)desc_p->buf_addr;
  496. return length;
  497. }
  498. }
  499. return length;
  500. }
  501. static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
  502. int len)
  503. {
  504. u32 v, desc_num = priv->tx_currdescnum;
  505. struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
  506. uintptr_t desc_start = (uintptr_t)desc_p;
  507. uintptr_t desc_end = desc_start +
  508. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  509. uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
  510. uintptr_t data_end = data_start +
  511. roundup(len, ARCH_DMA_MINALIGN);
  512. /* Invalidate entire buffer descriptor */
  513. invalidate_dcache_range(desc_start, desc_end);
  514. desc_p->st = len;
  515. /* Mandatory undocumented bit */
  516. desc_p->st |= BIT(24);
  517. memcpy((void *)data_start, packet, len);
  518. /* Flush data to be sent */
  519. flush_dcache_range(data_start, data_end);
  520. /* frame end */
  521. desc_p->st |= BIT(30);
  522. desc_p->st |= BIT(31);
  523. /*frame begin */
  524. desc_p->st |= BIT(29);
  525. desc_p->status = BIT(31);
  526. /*Descriptors st and status field has changed, so FLUSH it */
  527. flush_dcache_range(desc_start, desc_end);
  528. /* Move to next Descriptor and wrap around */
  529. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  530. desc_num = 0;
  531. priv->tx_currdescnum = desc_num;
  532. /* Start the DMA */
  533. v = readl(priv->mac_reg + EMAC_TX_CTL1);
  534. v |= BIT(31);/* mandatory */
  535. v |= BIT(30);/* mandatory */
  536. writel(v, priv->mac_reg + EMAC_TX_CTL1);
  537. return 0;
  538. }
  539. static int sun8i_eth_write_hwaddr(struct udevice *dev)
  540. {
  541. struct eth_pdata *pdata = dev_get_platdata(dev);
  542. struct emac_eth_dev *priv = dev_get_priv(dev);
  543. return _sun8i_write_hwaddr(priv, pdata->enetaddr);
  544. }
  545. static int sun8i_emac_board_setup(struct emac_eth_dev *priv)
  546. {
  547. int ret;
  548. ret = clk_enable(&priv->tx_clk);
  549. if (ret) {
  550. dev_err(dev, "failed to enable TX clock\n");
  551. return ret;
  552. }
  553. if (reset_valid(&priv->tx_rst)) {
  554. ret = reset_deassert(&priv->tx_rst);
  555. if (ret) {
  556. dev_err(dev, "failed to deassert TX reset\n");
  557. goto err_tx_clk;
  558. }
  559. }
  560. /* Only H3/H5 have clock controls for internal EPHY */
  561. if (clk_valid(&priv->ephy_clk)) {
  562. ret = clk_enable(&priv->ephy_clk);
  563. if (ret) {
  564. dev_err(dev, "failed to enable EPHY TX clock\n");
  565. return ret;
  566. }
  567. }
  568. if (reset_valid(&priv->ephy_rst)) {
  569. ret = reset_deassert(&priv->ephy_rst);
  570. if (ret) {
  571. dev_err(dev, "failed to deassert EPHY TX clock\n");
  572. return ret;
  573. }
  574. }
  575. return 0;
  576. err_tx_clk:
  577. clk_disable(&priv->tx_clk);
  578. return ret;
  579. }
  580. #if CONFIG_IS_ENABLED(DM_GPIO)
  581. static int sun8i_mdio_reset(struct mii_dev *bus)
  582. {
  583. struct udevice *dev = bus->priv;
  584. struct emac_eth_dev *priv = dev_get_priv(dev);
  585. struct sun8i_eth_pdata *pdata = dev_get_platdata(dev);
  586. int ret;
  587. if (!dm_gpio_is_valid(&priv->reset_gpio))
  588. return 0;
  589. /* reset the phy */
  590. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  591. if (ret)
  592. return ret;
  593. udelay(pdata->reset_delays[0]);
  594. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  595. if (ret)
  596. return ret;
  597. udelay(pdata->reset_delays[1]);
  598. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  599. if (ret)
  600. return ret;
  601. udelay(pdata->reset_delays[2]);
  602. return 0;
  603. }
  604. #endif
  605. static int sun8i_mdio_init(const char *name, struct udevice *priv)
  606. {
  607. struct mii_dev *bus = mdio_alloc();
  608. if (!bus) {
  609. debug("Failed to allocate MDIO bus\n");
  610. return -ENOMEM;
  611. }
  612. bus->read = sun8i_mdio_read;
  613. bus->write = sun8i_mdio_write;
  614. snprintf(bus->name, sizeof(bus->name), name);
  615. bus->priv = (void *)priv;
  616. #if CONFIG_IS_ENABLED(DM_GPIO)
  617. bus->reset = sun8i_mdio_reset;
  618. #endif
  619. return mdio_register(bus);
  620. }
  621. static int sun8i_emac_eth_start(struct udevice *dev)
  622. {
  623. struct eth_pdata *pdata = dev_get_platdata(dev);
  624. return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
  625. }
  626. static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
  627. {
  628. struct emac_eth_dev *priv = dev_get_priv(dev);
  629. return _sun8i_emac_eth_send(priv, packet, length);
  630. }
  631. static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  632. {
  633. struct emac_eth_dev *priv = dev_get_priv(dev);
  634. return _sun8i_eth_recv(priv, packetp);
  635. }
  636. static int _sun8i_free_pkt(struct emac_eth_dev *priv)
  637. {
  638. u32 desc_num = priv->rx_currdescnum;
  639. struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
  640. uintptr_t desc_start = (uintptr_t)desc_p;
  641. uintptr_t desc_end = desc_start +
  642. roundup(sizeof(u32), ARCH_DMA_MINALIGN);
  643. /* Make the current descriptor valid again */
  644. desc_p->status |= BIT(31);
  645. /* Flush Status field of descriptor */
  646. flush_dcache_range(desc_start, desc_end);
  647. /* Move to next desc and wrap-around condition. */
  648. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  649. desc_num = 0;
  650. priv->rx_currdescnum = desc_num;
  651. return 0;
  652. }
  653. static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
  654. int length)
  655. {
  656. struct emac_eth_dev *priv = dev_get_priv(dev);
  657. return _sun8i_free_pkt(priv);
  658. }
  659. static void sun8i_emac_eth_stop(struct udevice *dev)
  660. {
  661. struct emac_eth_dev *priv = dev_get_priv(dev);
  662. /* Stop Rx/Tx transmitter */
  663. clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
  664. clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
  665. /* Stop TX DMA */
  666. clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
  667. phy_shutdown(priv->phydev);
  668. }
  669. static int sun8i_emac_eth_probe(struct udevice *dev)
  670. {
  671. struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
  672. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  673. struct emac_eth_dev *priv = dev_get_priv(dev);
  674. int ret;
  675. priv->mac_reg = (void *)pdata->iobase;
  676. ret = sun8i_emac_board_setup(priv);
  677. if (ret)
  678. return ret;
  679. sun8i_emac_set_syscon(sun8i_pdata, priv);
  680. sun8i_mdio_init(dev->name, dev);
  681. priv->bus = miiphy_get_dev_by_name(dev->name);
  682. return sun8i_phy_init(priv, dev);
  683. }
  684. static const struct eth_ops sun8i_emac_eth_ops = {
  685. .start = sun8i_emac_eth_start,
  686. .write_hwaddr = sun8i_eth_write_hwaddr,
  687. .send = sun8i_emac_eth_send,
  688. .recv = sun8i_emac_eth_recv,
  689. .free_pkt = sun8i_eth_free_pkt,
  690. .stop = sun8i_emac_eth_stop,
  691. };
  692. static int sun8i_get_ephy_nodes(struct emac_eth_dev *priv)
  693. {
  694. int emac_node, ephy_node, ret, ephy_handle;
  695. emac_node = fdt_path_offset(gd->fdt_blob,
  696. "/soc/ethernet@1c30000");
  697. if (emac_node < 0) {
  698. debug("failed to get emac node\n");
  699. return emac_node;
  700. }
  701. ephy_handle = fdtdec_lookup_phandle(gd->fdt_blob,
  702. emac_node, "phy-handle");
  703. /* look for mdio-mux node for internal PHY node */
  704. ephy_node = fdt_path_offset(gd->fdt_blob,
  705. "/soc/ethernet@1c30000/mdio-mux/mdio@1/ethernet-phy@1");
  706. if (ephy_node < 0) {
  707. debug("failed to get mdio-mux with internal PHY\n");
  708. return ephy_node;
  709. }
  710. /* This is not the phy we are looking for */
  711. if (ephy_node != ephy_handle)
  712. return 0;
  713. ret = fdt_node_check_compatible(gd->fdt_blob, ephy_node,
  714. "allwinner,sun8i-h3-mdio-internal");
  715. if (ret < 0) {
  716. debug("failed to find mdio-internal node\n");
  717. return ret;
  718. }
  719. ret = clk_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
  720. &priv->ephy_clk);
  721. if (ret) {
  722. dev_err(dev, "failed to get EPHY TX clock\n");
  723. return ret;
  724. }
  725. ret = reset_get_by_index_nodev(offset_to_ofnode(ephy_node), 0,
  726. &priv->ephy_rst);
  727. if (ret) {
  728. dev_err(dev, "failed to get EPHY TX reset\n");
  729. return ret;
  730. }
  731. priv->use_internal_phy = true;
  732. return 0;
  733. }
  734. static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
  735. {
  736. struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev);
  737. struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
  738. struct emac_eth_dev *priv = dev_get_priv(dev);
  739. const char *phy_mode;
  740. const fdt32_t *reg;
  741. int node = dev_of_offset(dev);
  742. int offset = 0;
  743. #if CONFIG_IS_ENABLED(DM_GPIO)
  744. int reset_flags = GPIOD_IS_OUT;
  745. #endif
  746. int ret;
  747. pdata->iobase = dev_read_addr(dev);
  748. if (pdata->iobase == FDT_ADDR_T_NONE) {
  749. debug("%s: Cannot find MAC base address\n", __func__);
  750. return -EINVAL;
  751. }
  752. priv->variant = dev_get_driver_data(dev);
  753. if (!priv->variant) {
  754. printf("%s: Missing variant\n", __func__);
  755. return -EINVAL;
  756. }
  757. ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
  758. if (ret) {
  759. dev_err(dev, "failed to get TX clock\n");
  760. return ret;
  761. }
  762. ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
  763. if (ret && ret != -ENOENT) {
  764. dev_err(dev, "failed to get TX reset\n");
  765. return ret;
  766. }
  767. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
  768. if (offset < 0) {
  769. debug("%s: cannot find syscon node\n", __func__);
  770. return -EINVAL;
  771. }
  772. reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
  773. if (!reg) {
  774. debug("%s: cannot find reg property in syscon node\n",
  775. __func__);
  776. return -EINVAL;
  777. }
  778. priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
  779. offset, reg);
  780. if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
  781. debug("%s: Cannot find syscon base address\n", __func__);
  782. return -EINVAL;
  783. }
  784. pdata->phy_interface = -1;
  785. priv->phyaddr = -1;
  786. priv->use_internal_phy = false;
  787. offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
  788. if (offset < 0) {
  789. debug("%s: Cannot find PHY address\n", __func__);
  790. return -EINVAL;
  791. }
  792. priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
  793. phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
  794. if (phy_mode)
  795. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  796. printf("phy interface%d\n", pdata->phy_interface);
  797. if (pdata->phy_interface == -1) {
  798. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  799. return -EINVAL;
  800. }
  801. if (priv->variant == H3_EMAC) {
  802. ret = sun8i_get_ephy_nodes(priv);
  803. if (ret)
  804. return ret;
  805. }
  806. priv->interface = pdata->phy_interface;
  807. if (!priv->use_internal_phy)
  808. parse_phy_pins(dev);
  809. sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
  810. "allwinner,tx-delay-ps", 0);
  811. if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
  812. printf("%s: Invalid TX delay value %d\n", __func__,
  813. sun8i_pdata->tx_delay_ps);
  814. sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
  815. "allwinner,rx-delay-ps", 0);
  816. if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
  817. printf("%s: Invalid RX delay value %d\n", __func__,
  818. sun8i_pdata->rx_delay_ps);
  819. #if CONFIG_IS_ENABLED(DM_GPIO)
  820. if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
  821. "snps,reset-active-low"))
  822. reset_flags |= GPIOD_ACTIVE_LOW;
  823. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  824. &priv->reset_gpio, reset_flags);
  825. if (ret == 0) {
  826. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  827. "snps,reset-delays-us",
  828. sun8i_pdata->reset_delays, 3);
  829. } else if (ret == -ENOENT) {
  830. ret = 0;
  831. }
  832. #endif
  833. return 0;
  834. }
  835. static const struct udevice_id sun8i_emac_eth_ids[] = {
  836. {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
  837. {.compatible = "allwinner,sun50i-a64-emac",
  838. .data = (uintptr_t)A64_EMAC },
  839. {.compatible = "allwinner,sun8i-a83t-emac",
  840. .data = (uintptr_t)A83T_EMAC },
  841. {.compatible = "allwinner,sun8i-r40-gmac",
  842. .data = (uintptr_t)R40_GMAC },
  843. {.compatible = "allwinner,sun50i-h6-emac",
  844. .data = (uintptr_t)H6_EMAC },
  845. { }
  846. };
  847. U_BOOT_DRIVER(eth_sun8i_emac) = {
  848. .name = "eth_sun8i_emac",
  849. .id = UCLASS_ETH,
  850. .of_match = sun8i_emac_eth_ids,
  851. .ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
  852. .probe = sun8i_emac_eth_probe,
  853. .ops = &sun8i_emac_eth_ops,
  854. .priv_auto_alloc_size = sizeof(struct emac_eth_dev),
  855. .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata),
  856. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  857. };