sh_eth.c 25 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * sh_eth.c - Driver for Renesas ethernet controller.
  4. *
  5. * Copyright (C) 2008, 2011 Renesas Solutions Corp.
  6. * Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
  7. * Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
  8. * Copyright (C) 2013, 2014 Renesas Electronics Corporation
  9. */
  10. #include <config.h>
  11. #include <common.h>
  12. #include <cpu_func.h>
  13. #include <env.h>
  14. #include <log.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <netdev.h>
  18. #include <miiphy.h>
  19. #include <asm/cache.h>
  20. #include <linux/delay.h>
  21. #include <linux/errno.h>
  22. #include <asm/io.h>
  23. #ifdef CONFIG_DM_ETH
  24. #include <clk.h>
  25. #include <dm.h>
  26. #include <linux/mii.h>
  27. #include <asm/gpio.h>
  28. #endif
  29. #include "sh_eth.h"
  30. #ifndef CONFIG_SH_ETHER_USE_PORT
  31. # error "Please define CONFIG_SH_ETHER_USE_PORT"
  32. #endif
  33. #ifndef CONFIG_SH_ETHER_PHY_ADDR
  34. # error "Please define CONFIG_SH_ETHER_PHY_ADDR"
  35. #endif
  36. #if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && \
  37. !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  38. #define flush_cache_wback(addr, len) \
  39. flush_dcache_range((unsigned long)addr, \
  40. (unsigned long)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
  41. #else
  42. #define flush_cache_wback(...)
  43. #endif
  44. #if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
  45. #define invalidate_cache(addr, len) \
  46. { \
  47. unsigned long line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
  48. unsigned long start, end; \
  49. \
  50. start = (unsigned long)addr; \
  51. end = start + len; \
  52. start &= ~(line_size - 1); \
  53. end = ((end + line_size - 1) & ~(line_size - 1)); \
  54. \
  55. invalidate_dcache_range(start, end); \
  56. }
  57. #else
  58. #define invalidate_cache(...)
  59. #endif
  60. #define TIMEOUT_CNT 1000
  61. static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
  62. {
  63. int ret = 0, timeout;
  64. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  65. if (!packet || len > 0xffff) {
  66. printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
  67. ret = -EINVAL;
  68. goto err;
  69. }
  70. /* packet must be a 4 byte boundary */
  71. if ((uintptr_t)packet & 3) {
  72. printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
  73. , __func__);
  74. ret = -EFAULT;
  75. goto err;
  76. }
  77. /* Update tx descriptor */
  78. flush_cache_wback(packet, len);
  79. port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
  80. port_info->tx_desc_cur->td1 = len << 16;
  81. /* Must preserve the end of descriptor list indication */
  82. if (port_info->tx_desc_cur->td0 & TD_TDLE)
  83. port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
  84. else
  85. port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
  86. flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
  87. /* Restart the transmitter if disabled */
  88. if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
  89. sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
  90. /* Wait until packet is transmitted */
  91. timeout = TIMEOUT_CNT;
  92. do {
  93. invalidate_cache(port_info->tx_desc_cur,
  94. sizeof(struct tx_desc_s));
  95. udelay(100);
  96. } while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
  97. if (timeout < 0) {
  98. printf(SHETHER_NAME ": transmit timeout\n");
  99. ret = -ETIMEDOUT;
  100. goto err;
  101. }
  102. port_info->tx_desc_cur++;
  103. if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
  104. port_info->tx_desc_cur = port_info->tx_desc_base;
  105. err:
  106. return ret;
  107. }
  108. static int sh_eth_recv_start(struct sh_eth_dev *eth)
  109. {
  110. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  111. /* Check if the rx descriptor is ready */
  112. invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
  113. if (port_info->rx_desc_cur->rd0 & RD_RACT)
  114. return -EINVAL;
  115. /* Check for errors */
  116. if (port_info->rx_desc_cur->rd0 & RD_RFE)
  117. return -EINVAL;
  118. return port_info->rx_desc_cur->rd1 & 0xffff;
  119. }
  120. static void sh_eth_recv_finish(struct sh_eth_dev *eth)
  121. {
  122. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  123. /* Make current descriptor available again */
  124. if (port_info->rx_desc_cur->rd0 & RD_RDLE)
  125. port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
  126. else
  127. port_info->rx_desc_cur->rd0 = RD_RACT;
  128. flush_cache_wback(port_info->rx_desc_cur,
  129. sizeof(struct rx_desc_s));
  130. /* Point to the next descriptor */
  131. port_info->rx_desc_cur++;
  132. if (port_info->rx_desc_cur >=
  133. port_info->rx_desc_base + NUM_RX_DESC)
  134. port_info->rx_desc_cur = port_info->rx_desc_base;
  135. }
  136. static int sh_eth_reset(struct sh_eth_dev *eth)
  137. {
  138. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  139. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  140. int ret = 0, i;
  141. /* Start e-dmac transmitter and receiver */
  142. sh_eth_write(port_info, EDSR_ENALL, EDSR);
  143. /* Perform a software reset and wait for it to complete */
  144. sh_eth_write(port_info, EDMR_SRST, EDMR);
  145. for (i = 0; i < TIMEOUT_CNT; i++) {
  146. if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
  147. break;
  148. udelay(1000);
  149. }
  150. if (i == TIMEOUT_CNT) {
  151. printf(SHETHER_NAME ": Software reset timeout\n");
  152. ret = -EIO;
  153. }
  154. return ret;
  155. #else
  156. sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
  157. mdelay(3);
  158. sh_eth_write(port_info,
  159. sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
  160. return 0;
  161. #endif
  162. }
  163. static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
  164. {
  165. int i, ret = 0;
  166. u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
  167. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  168. struct tx_desc_s *cur_tx_desc;
  169. /*
  170. * Allocate rx descriptors. They must be aligned to size of struct
  171. * tx_desc_s.
  172. */
  173. port_info->tx_desc_alloc =
  174. memalign(sizeof(struct tx_desc_s), alloc_desc_size);
  175. if (!port_info->tx_desc_alloc) {
  176. printf(SHETHER_NAME ": memalign failed\n");
  177. ret = -ENOMEM;
  178. goto err;
  179. }
  180. flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
  181. /* Make sure we use a P2 address (non-cacheable) */
  182. port_info->tx_desc_base =
  183. (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
  184. port_info->tx_desc_cur = port_info->tx_desc_base;
  185. /* Initialize all descriptors */
  186. for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
  187. cur_tx_desc++, i++) {
  188. cur_tx_desc->td0 = 0x00;
  189. cur_tx_desc->td1 = 0x00;
  190. cur_tx_desc->td2 = 0x00;
  191. }
  192. /* Mark the end of the descriptors */
  193. cur_tx_desc--;
  194. cur_tx_desc->td0 |= TD_TDLE;
  195. /*
  196. * Point the controller to the tx descriptor list. Must use physical
  197. * addresses
  198. */
  199. sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
  200. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  201. sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
  202. sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
  203. sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
  204. #endif
  205. err:
  206. return ret;
  207. }
  208. static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
  209. {
  210. int i, ret = 0;
  211. u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
  212. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  213. struct rx_desc_s *cur_rx_desc;
  214. u8 *rx_buf;
  215. /*
  216. * Allocate rx descriptors. They must be aligned to size of struct
  217. * rx_desc_s.
  218. */
  219. port_info->rx_desc_alloc =
  220. memalign(sizeof(struct rx_desc_s), alloc_desc_size);
  221. if (!port_info->rx_desc_alloc) {
  222. printf(SHETHER_NAME ": memalign failed\n");
  223. ret = -ENOMEM;
  224. goto err;
  225. }
  226. flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
  227. /* Make sure we use a P2 address (non-cacheable) */
  228. port_info->rx_desc_base =
  229. (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
  230. port_info->rx_desc_cur = port_info->rx_desc_base;
  231. /*
  232. * Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
  233. * aligned and in P2 area.
  234. */
  235. port_info->rx_buf_alloc =
  236. memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
  237. if (!port_info->rx_buf_alloc) {
  238. printf(SHETHER_NAME ": alloc failed\n");
  239. ret = -ENOMEM;
  240. goto err_buf_alloc;
  241. }
  242. port_info->rx_buf_base = (u8 *)ADDR_TO_P2((uintptr_t)port_info->rx_buf_alloc);
  243. /* Initialize all descriptors */
  244. for (cur_rx_desc = port_info->rx_desc_base,
  245. rx_buf = port_info->rx_buf_base, i = 0;
  246. i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
  247. cur_rx_desc->rd0 = RD_RACT;
  248. cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
  249. cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
  250. }
  251. /* Mark the end of the descriptors */
  252. cur_rx_desc--;
  253. cur_rx_desc->rd0 |= RD_RDLE;
  254. /* Point the controller to the rx descriptor list */
  255. sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
  256. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  257. sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
  258. sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
  259. sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
  260. #endif
  261. return ret;
  262. err_buf_alloc:
  263. free(port_info->rx_desc_alloc);
  264. port_info->rx_desc_alloc = NULL;
  265. err:
  266. return ret;
  267. }
  268. static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
  269. {
  270. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  271. if (port_info->tx_desc_alloc) {
  272. free(port_info->tx_desc_alloc);
  273. port_info->tx_desc_alloc = NULL;
  274. }
  275. }
  276. static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
  277. {
  278. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  279. if (port_info->rx_desc_alloc) {
  280. free(port_info->rx_desc_alloc);
  281. port_info->rx_desc_alloc = NULL;
  282. }
  283. if (port_info->rx_buf_alloc) {
  284. free(port_info->rx_buf_alloc);
  285. port_info->rx_buf_alloc = NULL;
  286. }
  287. }
  288. static int sh_eth_desc_init(struct sh_eth_dev *eth)
  289. {
  290. int ret = 0;
  291. ret = sh_eth_tx_desc_init(eth);
  292. if (ret)
  293. goto err_tx_init;
  294. ret = sh_eth_rx_desc_init(eth);
  295. if (ret)
  296. goto err_rx_init;
  297. return ret;
  298. err_rx_init:
  299. sh_eth_tx_desc_free(eth);
  300. err_tx_init:
  301. return ret;
  302. }
  303. static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
  304. unsigned char *mac)
  305. {
  306. u32 val;
  307. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  308. sh_eth_write(port_info, val, MAHR);
  309. val = (mac[4] << 8) | mac[5];
  310. sh_eth_write(port_info, val, MALR);
  311. }
  312. static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
  313. {
  314. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  315. unsigned long edmr;
  316. /* Configure e-dmac registers */
  317. edmr = sh_eth_read(port_info, EDMR);
  318. edmr &= ~EMDR_DESC_R;
  319. edmr |= EMDR_DESC | EDMR_EL;
  320. #if defined(CONFIG_R8A77980)
  321. edmr |= EDMR_NBST;
  322. #endif
  323. sh_eth_write(port_info, edmr, EDMR);
  324. sh_eth_write(port_info, 0, EESIPR);
  325. sh_eth_write(port_info, 0, TRSCER);
  326. sh_eth_write(port_info, 0, TFTR);
  327. sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
  328. sh_eth_write(port_info, RMCR_RST, RMCR);
  329. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  330. sh_eth_write(port_info, 0, RPADIR);
  331. #endif
  332. sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
  333. /* Configure e-mac registers */
  334. sh_eth_write(port_info, 0, ECSIPR);
  335. /* Set Mac address */
  336. sh_eth_write_hwaddr(port_info, mac);
  337. sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
  338. #if defined(SH_ETH_TYPE_GETHER)
  339. sh_eth_write(port_info, 0, PIPR);
  340. #endif
  341. #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
  342. sh_eth_write(port_info, APR_AP, APR);
  343. sh_eth_write(port_info, MPR_MP, MPR);
  344. sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
  345. #endif
  346. #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
  347. sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
  348. #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
  349. sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
  350. #endif
  351. }
  352. static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
  353. {
  354. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  355. struct phy_device *phy = port_info->phydev;
  356. int ret = 0;
  357. u32 val = 0;
  358. /* Set the transfer speed */
  359. if (phy->speed == 100) {
  360. printf(SHETHER_NAME ": 100Base/");
  361. #if defined(SH_ETH_TYPE_GETHER)
  362. sh_eth_write(port_info, GECMR_100B, GECMR);
  363. #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
  364. sh_eth_write(port_info, 1, RTRATE);
  365. #elif defined(CONFIG_RCAR_GEN2) || defined(CONFIG_R8A77980)
  366. val = ECMR_RTM;
  367. #endif
  368. } else if (phy->speed == 10) {
  369. printf(SHETHER_NAME ": 10Base/");
  370. #if defined(SH_ETH_TYPE_GETHER)
  371. sh_eth_write(port_info, GECMR_10B, GECMR);
  372. #elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
  373. sh_eth_write(port_info, 0, RTRATE);
  374. #endif
  375. }
  376. #if defined(SH_ETH_TYPE_GETHER)
  377. else if (phy->speed == 1000) {
  378. printf(SHETHER_NAME ": 1000Base/");
  379. sh_eth_write(port_info, GECMR_1000B, GECMR);
  380. }
  381. #endif
  382. /* Check if full duplex mode is supported by the phy */
  383. if (phy->duplex) {
  384. printf("Full\n");
  385. sh_eth_write(port_info,
  386. val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
  387. ECMR);
  388. } else {
  389. printf("Half\n");
  390. sh_eth_write(port_info,
  391. val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
  392. ECMR);
  393. }
  394. return ret;
  395. }
  396. static void sh_eth_start(struct sh_eth_dev *eth)
  397. {
  398. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  399. /*
  400. * Enable the e-dmac receiver only. The transmitter will be enabled when
  401. * we have something to transmit
  402. */
  403. sh_eth_write(port_info, EDRRR_R, EDRRR);
  404. }
  405. static void sh_eth_stop(struct sh_eth_dev *eth)
  406. {
  407. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  408. sh_eth_write(port_info, ~EDRRR_R, EDRRR);
  409. }
  410. static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
  411. {
  412. int ret = 0;
  413. ret = sh_eth_reset(eth);
  414. if (ret)
  415. return ret;
  416. ret = sh_eth_desc_init(eth);
  417. if (ret)
  418. return ret;
  419. sh_eth_mac_regs_config(eth, mac);
  420. return 0;
  421. }
  422. static int sh_eth_start_common(struct sh_eth_dev *eth)
  423. {
  424. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  425. int ret;
  426. ret = phy_startup(port_info->phydev);
  427. if (ret) {
  428. printf(SHETHER_NAME ": phy startup failure\n");
  429. return ret;
  430. }
  431. ret = sh_eth_phy_regs_config(eth);
  432. if (ret)
  433. return ret;
  434. sh_eth_start(eth);
  435. return 0;
  436. }
  437. #ifndef CONFIG_DM_ETH
  438. static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
  439. {
  440. int ret = 0;
  441. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  442. struct eth_device *dev = port_info->dev;
  443. struct phy_device *phydev;
  444. phydev = phy_connect(
  445. miiphy_get_dev_by_name(dev->name),
  446. port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
  447. port_info->phydev = phydev;
  448. phy_config(phydev);
  449. return ret;
  450. }
  451. static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
  452. {
  453. struct sh_eth_dev *eth = dev->priv;
  454. return sh_eth_send_common(eth, packet, len);
  455. }
  456. static int sh_eth_recv_common(struct sh_eth_dev *eth)
  457. {
  458. int len = 0;
  459. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  460. uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
  461. len = sh_eth_recv_start(eth);
  462. if (len > 0) {
  463. invalidate_cache(packet, len);
  464. net_process_received_packet(packet, len);
  465. sh_eth_recv_finish(eth);
  466. } else
  467. len = 0;
  468. /* Restart the receiver if disabled */
  469. if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
  470. sh_eth_write(port_info, EDRRR_R, EDRRR);
  471. return len;
  472. }
  473. static int sh_eth_recv_legacy(struct eth_device *dev)
  474. {
  475. struct sh_eth_dev *eth = dev->priv;
  476. return sh_eth_recv_common(eth);
  477. }
  478. static int sh_eth_init_legacy(struct eth_device *dev, struct bd_info *bd)
  479. {
  480. struct sh_eth_dev *eth = dev->priv;
  481. int ret;
  482. ret = sh_eth_init_common(eth, dev->enetaddr);
  483. if (ret)
  484. return ret;
  485. ret = sh_eth_phy_config_legacy(eth);
  486. if (ret) {
  487. printf(SHETHER_NAME ": phy config timeout\n");
  488. goto err_start;
  489. }
  490. ret = sh_eth_start_common(eth);
  491. if (ret)
  492. goto err_start;
  493. return 0;
  494. err_start:
  495. sh_eth_tx_desc_free(eth);
  496. sh_eth_rx_desc_free(eth);
  497. return ret;
  498. }
  499. void sh_eth_halt_legacy(struct eth_device *dev)
  500. {
  501. struct sh_eth_dev *eth = dev->priv;
  502. sh_eth_stop(eth);
  503. }
  504. int sh_eth_initialize(struct bd_info *bd)
  505. {
  506. int ret = 0;
  507. struct sh_eth_dev *eth = NULL;
  508. struct eth_device *dev = NULL;
  509. struct mii_dev *mdiodev;
  510. eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
  511. if (!eth) {
  512. printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
  513. ret = -ENOMEM;
  514. goto err;
  515. }
  516. dev = (struct eth_device *)malloc(sizeof(struct eth_device));
  517. if (!dev) {
  518. printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
  519. ret = -ENOMEM;
  520. goto err;
  521. }
  522. memset(dev, 0, sizeof(struct eth_device));
  523. memset(eth, 0, sizeof(struct sh_eth_dev));
  524. eth->port = CONFIG_SH_ETHER_USE_PORT;
  525. eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
  526. eth->port_info[eth->port].iobase =
  527. (void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
  528. dev->priv = (void *)eth;
  529. dev->iobase = 0;
  530. dev->init = sh_eth_init_legacy;
  531. dev->halt = sh_eth_halt_legacy;
  532. dev->send = sh_eth_send_legacy;
  533. dev->recv = sh_eth_recv_legacy;
  534. eth->port_info[eth->port].dev = dev;
  535. strcpy(dev->name, SHETHER_NAME);
  536. /* Register Device to EtherNet subsystem */
  537. eth_register(dev);
  538. bb_miiphy_buses[0].priv = eth;
  539. mdiodev = mdio_alloc();
  540. if (!mdiodev)
  541. return -ENOMEM;
  542. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  543. mdiodev->read = bb_miiphy_read;
  544. mdiodev->write = bb_miiphy_write;
  545. ret = mdio_register(mdiodev);
  546. if (ret < 0)
  547. return ret;
  548. if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
  549. puts("Please set MAC address\n");
  550. return ret;
  551. err:
  552. if (dev)
  553. free(dev);
  554. if (eth)
  555. free(eth);
  556. printf(SHETHER_NAME ": Failed\n");
  557. return ret;
  558. }
  559. #else /* CONFIG_DM_ETH */
  560. struct sh_ether_priv {
  561. struct sh_eth_dev shdev;
  562. struct mii_dev *bus;
  563. phys_addr_t iobase;
  564. struct clk clk;
  565. struct gpio_desc reset_gpio;
  566. };
  567. static int sh_ether_send(struct udevice *dev, void *packet, int len)
  568. {
  569. struct sh_ether_priv *priv = dev_get_priv(dev);
  570. struct sh_eth_dev *eth = &priv->shdev;
  571. return sh_eth_send_common(eth, packet, len);
  572. }
  573. static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
  574. {
  575. struct sh_ether_priv *priv = dev_get_priv(dev);
  576. struct sh_eth_dev *eth = &priv->shdev;
  577. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  578. uchar *packet = (uchar *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_cur->rd2);
  579. int len;
  580. len = sh_eth_recv_start(eth);
  581. if (len > 0) {
  582. invalidate_cache(packet, len);
  583. *packetp = packet;
  584. return len;
  585. } else {
  586. len = 0;
  587. /* Restart the receiver if disabled */
  588. if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
  589. sh_eth_write(port_info, EDRRR_R, EDRRR);
  590. return -EAGAIN;
  591. }
  592. }
  593. static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
  594. {
  595. struct sh_ether_priv *priv = dev_get_priv(dev);
  596. struct sh_eth_dev *eth = &priv->shdev;
  597. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  598. sh_eth_recv_finish(eth);
  599. /* Restart the receiver if disabled */
  600. if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
  601. sh_eth_write(port_info, EDRRR_R, EDRRR);
  602. return 0;
  603. }
  604. static int sh_ether_write_hwaddr(struct udevice *dev)
  605. {
  606. struct sh_ether_priv *priv = dev_get_priv(dev);
  607. struct sh_eth_dev *eth = &priv->shdev;
  608. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  609. struct eth_pdata *pdata = dev_get_platdata(dev);
  610. sh_eth_write_hwaddr(port_info, pdata->enetaddr);
  611. return 0;
  612. }
  613. static int sh_eth_phy_config(struct udevice *dev)
  614. {
  615. struct sh_ether_priv *priv = dev_get_priv(dev);
  616. struct eth_pdata *pdata = dev_get_platdata(dev);
  617. struct sh_eth_dev *eth = &priv->shdev;
  618. int ret = 0;
  619. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  620. struct phy_device *phydev;
  621. int mask = 0xffffffff;
  622. phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
  623. if (!phydev)
  624. return -ENODEV;
  625. phy_connect_dev(phydev, dev);
  626. port_info->phydev = phydev;
  627. phy_config(phydev);
  628. return ret;
  629. }
  630. static int sh_ether_start(struct udevice *dev)
  631. {
  632. struct sh_ether_priv *priv = dev_get_priv(dev);
  633. struct eth_pdata *pdata = dev_get_platdata(dev);
  634. struct sh_eth_dev *eth = &priv->shdev;
  635. int ret;
  636. ret = sh_eth_init_common(eth, pdata->enetaddr);
  637. if (ret)
  638. return ret;
  639. ret = sh_eth_start_common(eth);
  640. if (ret)
  641. goto err_start;
  642. return 0;
  643. err_start:
  644. sh_eth_tx_desc_free(eth);
  645. sh_eth_rx_desc_free(eth);
  646. return ret;
  647. }
  648. static void sh_ether_stop(struct udevice *dev)
  649. {
  650. struct sh_ether_priv *priv = dev_get_priv(dev);
  651. struct sh_eth_dev *eth = &priv->shdev;
  652. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  653. phy_shutdown(port_info->phydev);
  654. sh_eth_stop(&priv->shdev);
  655. }
  656. static int sh_ether_probe(struct udevice *udev)
  657. {
  658. struct eth_pdata *pdata = dev_get_platdata(udev);
  659. struct sh_ether_priv *priv = dev_get_priv(udev);
  660. struct sh_eth_dev *eth = &priv->shdev;
  661. struct ofnode_phandle_args phandle_args;
  662. struct mii_dev *mdiodev;
  663. int ret;
  664. priv->iobase = pdata->iobase;
  665. #if CONFIG_IS_ENABLED(CLK)
  666. ret = clk_get_by_index(udev, 0, &priv->clk);
  667. if (ret < 0)
  668. return ret;
  669. #endif
  670. ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args);
  671. if (!ret) {
  672. gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
  673. &priv->reset_gpio, GPIOD_IS_OUT);
  674. }
  675. if (!dm_gpio_is_valid(&priv->reset_gpio)) {
  676. gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
  677. GPIOD_IS_OUT);
  678. }
  679. mdiodev = mdio_alloc();
  680. if (!mdiodev) {
  681. ret = -ENOMEM;
  682. return ret;
  683. }
  684. mdiodev->read = bb_miiphy_read;
  685. mdiodev->write = bb_miiphy_write;
  686. bb_miiphy_buses[0].priv = eth;
  687. snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
  688. ret = mdio_register(mdiodev);
  689. if (ret < 0)
  690. goto err_mdio_register;
  691. priv->bus = miiphy_get_dev_by_name(udev->name);
  692. eth->port = CONFIG_SH_ETHER_USE_PORT;
  693. eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
  694. eth->port_info[eth->port].iobase =
  695. (void __iomem *)(uintptr_t)(BASE_IO_ADDR + 0x800 * eth->port);
  696. #if CONFIG_IS_ENABLED(CLK)
  697. ret = clk_enable(&priv->clk);
  698. if (ret)
  699. goto err_mdio_register;
  700. #endif
  701. ret = sh_eth_init_common(eth, pdata->enetaddr);
  702. if (ret)
  703. goto err_phy_config;
  704. ret = sh_eth_phy_config(udev);
  705. if (ret) {
  706. printf(SHETHER_NAME ": phy config timeout\n");
  707. goto err_phy_config;
  708. }
  709. return 0;
  710. err_phy_config:
  711. #if CONFIG_IS_ENABLED(CLK)
  712. clk_disable(&priv->clk);
  713. #endif
  714. err_mdio_register:
  715. mdio_free(mdiodev);
  716. return ret;
  717. }
  718. static int sh_ether_remove(struct udevice *udev)
  719. {
  720. struct sh_ether_priv *priv = dev_get_priv(udev);
  721. struct sh_eth_dev *eth = &priv->shdev;
  722. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  723. #if CONFIG_IS_ENABLED(CLK)
  724. clk_disable(&priv->clk);
  725. #endif
  726. free(port_info->phydev);
  727. mdio_unregister(priv->bus);
  728. mdio_free(priv->bus);
  729. if (dm_gpio_is_valid(&priv->reset_gpio))
  730. dm_gpio_free(udev, &priv->reset_gpio);
  731. return 0;
  732. }
  733. static const struct eth_ops sh_ether_ops = {
  734. .start = sh_ether_start,
  735. .send = sh_ether_send,
  736. .recv = sh_ether_recv,
  737. .free_pkt = sh_ether_free_pkt,
  738. .stop = sh_ether_stop,
  739. .write_hwaddr = sh_ether_write_hwaddr,
  740. };
  741. int sh_ether_ofdata_to_platdata(struct udevice *dev)
  742. {
  743. struct eth_pdata *pdata = dev_get_platdata(dev);
  744. const char *phy_mode;
  745. const fdt32_t *cell;
  746. int ret = 0;
  747. pdata->iobase = dev_read_addr(dev);
  748. pdata->phy_interface = -1;
  749. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  750. NULL);
  751. if (phy_mode)
  752. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  753. if (pdata->phy_interface == -1) {
  754. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  755. return -EINVAL;
  756. }
  757. pdata->max_speed = 1000;
  758. cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
  759. if (cell)
  760. pdata->max_speed = fdt32_to_cpu(*cell);
  761. sprintf(bb_miiphy_buses[0].name, dev->name);
  762. return ret;
  763. }
  764. static const struct udevice_id sh_ether_ids[] = {
  765. { .compatible = "renesas,ether-r7s72100" },
  766. { .compatible = "renesas,ether-r8a7790" },
  767. { .compatible = "renesas,ether-r8a7791" },
  768. { .compatible = "renesas,ether-r8a7793" },
  769. { .compatible = "renesas,ether-r8a7794" },
  770. { .compatible = "renesas,gether-r8a77980" },
  771. { }
  772. };
  773. U_BOOT_DRIVER(eth_sh_ether) = {
  774. .name = "sh_ether",
  775. .id = UCLASS_ETH,
  776. .of_match = sh_ether_ids,
  777. .ofdata_to_platdata = sh_ether_ofdata_to_platdata,
  778. .probe = sh_ether_probe,
  779. .remove = sh_ether_remove,
  780. .ops = &sh_ether_ops,
  781. .priv_auto_alloc_size = sizeof(struct sh_ether_priv),
  782. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  783. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  784. };
  785. #endif
  786. /******* for bb_miiphy *******/
  787. static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
  788. {
  789. return 0;
  790. }
  791. static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
  792. {
  793. struct sh_eth_dev *eth = bus->priv;
  794. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  795. sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
  796. return 0;
  797. }
  798. static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
  799. {
  800. struct sh_eth_dev *eth = bus->priv;
  801. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  802. sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
  803. return 0;
  804. }
  805. static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
  806. {
  807. struct sh_eth_dev *eth = bus->priv;
  808. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  809. if (v)
  810. sh_eth_write(port_info,
  811. sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
  812. else
  813. sh_eth_write(port_info,
  814. sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
  815. return 0;
  816. }
  817. static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
  818. {
  819. struct sh_eth_dev *eth = bus->priv;
  820. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  821. *v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
  822. return 0;
  823. }
  824. static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
  825. {
  826. struct sh_eth_dev *eth = bus->priv;
  827. struct sh_eth_info *port_info = &eth->port_info[eth->port];
  828. if (v)
  829. sh_eth_write(port_info,
  830. sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
  831. else
  832. sh_eth_write(port_info,
  833. sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
  834. return 0;
  835. }
  836. static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
  837. {
  838. udelay(10);
  839. return 0;
  840. }
  841. struct bb_miiphy_bus bb_miiphy_buses[] = {
  842. {
  843. .name = "sh_eth",
  844. .init = sh_eth_bb_init,
  845. .mdio_active = sh_eth_bb_mdio_active,
  846. .mdio_tristate = sh_eth_bb_mdio_tristate,
  847. .set_mdio = sh_eth_bb_set_mdio,
  848. .get_mdio = sh_eth_bb_get_mdio,
  849. .set_mdc = sh_eth_bb_set_mdc,
  850. .delay = sh_eth_bb_delay,
  851. }
  852. };
  853. int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);