ag7xxx.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atheros AR71xx / AR9xxx GMAC driver
  4. *
  5. * Copyright (C) 2016 Marek Vasut <marex@denx.de>
  6. * Copyright (C) 2019 Rosy Song <rosysong@rosinson.com>
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <log.h>
  14. #include <miiphy.h>
  15. #include <malloc.h>
  16. #include <net.h>
  17. #include <asm/cache.h>
  18. #include <linux/bitops.h>
  19. #include <linux/compiler.h>
  20. #include <linux/delay.h>
  21. #include <linux/err.h>
  22. #include <linux/mii.h>
  23. #include <wait_bit.h>
  24. #include <asm/io.h>
  25. #include <mach/ath79.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. enum ag7xxx_model {
  28. AG7XXX_MODEL_AG933X,
  29. AG7XXX_MODEL_AG934X,
  30. AG7XXX_MODEL_AG953X,
  31. AG7XXX_MODEL_AG956X
  32. };
  33. /* MAC Configuration 1 */
  34. #define AG7XXX_ETH_CFG1 0x00
  35. #define AG7XXX_ETH_CFG1_SOFT_RST BIT(31)
  36. #define AG7XXX_ETH_CFG1_RX_RST BIT(19)
  37. #define AG7XXX_ETH_CFG1_TX_RST BIT(18)
  38. #define AG7XXX_ETH_CFG1_LOOPBACK BIT(8)
  39. #define AG7XXX_ETH_CFG1_RX_EN BIT(2)
  40. #define AG7XXX_ETH_CFG1_TX_EN BIT(0)
  41. /* MAC Configuration 2 */
  42. #define AG7XXX_ETH_CFG2 0x04
  43. #define AG7XXX_ETH_CFG2_IF_1000 BIT(9)
  44. #define AG7XXX_ETH_CFG2_IF_10_100 BIT(8)
  45. #define AG7XXX_ETH_CFG2_IF_SPEED_MASK (3 << 8)
  46. #define AG7XXX_ETH_CFG2_HUGE_FRAME_EN BIT(5)
  47. #define AG7XXX_ETH_CFG2_LEN_CHECK BIT(4)
  48. #define AG7XXX_ETH_CFG2_PAD_CRC_EN BIT(2)
  49. #define AG7XXX_ETH_CFG2_FDX BIT(0)
  50. /* MII Configuration */
  51. #define AG7XXX_ETH_MII_MGMT_CFG 0x20
  52. #define AG7XXX_ETH_MII_MGMT_CFG_RESET BIT(31)
  53. /* MII Command */
  54. #define AG7XXX_ETH_MII_MGMT_CMD 0x24
  55. #define AG7XXX_ETH_MII_MGMT_CMD_READ 0x1
  56. /* MII Address */
  57. #define AG7XXX_ETH_MII_MGMT_ADDRESS 0x28
  58. #define AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT 8
  59. /* MII Control */
  60. #define AG7XXX_ETH_MII_MGMT_CTRL 0x2c
  61. /* MII Status */
  62. #define AG7XXX_ETH_MII_MGMT_STATUS 0x30
  63. /* MII Indicators */
  64. #define AG7XXX_ETH_MII_MGMT_IND 0x34
  65. #define AG7XXX_ETH_MII_MGMT_IND_INVALID BIT(2)
  66. #define AG7XXX_ETH_MII_MGMT_IND_BUSY BIT(0)
  67. /* STA Address 1 & 2 */
  68. #define AG7XXX_ETH_ADDR1 0x40
  69. #define AG7XXX_ETH_ADDR2 0x44
  70. /* ETH Configuration 0 - 5 */
  71. #define AG7XXX_ETH_FIFO_CFG_0 0x48
  72. #define AG7XXX_ETH_FIFO_CFG_1 0x4c
  73. #define AG7XXX_ETH_FIFO_CFG_2 0x50
  74. #define AG7XXX_ETH_FIFO_CFG_3 0x54
  75. #define AG7XXX_ETH_FIFO_CFG_4 0x58
  76. #define AG7XXX_ETH_FIFO_CFG_5 0x5c
  77. /* DMA Transfer Control for Queue 0 */
  78. #define AG7XXX_ETH_DMA_TX_CTRL 0x180
  79. #define AG7XXX_ETH_DMA_TX_CTRL_TXE BIT(0)
  80. /* Descriptor Address for Queue 0 Tx */
  81. #define AG7XXX_ETH_DMA_TX_DESC 0x184
  82. /* DMA Tx Status */
  83. #define AG7XXX_ETH_DMA_TX_STATUS 0x188
  84. /* Rx Control */
  85. #define AG7XXX_ETH_DMA_RX_CTRL 0x18c
  86. #define AG7XXX_ETH_DMA_RX_CTRL_RXE BIT(0)
  87. /* Pointer to Rx Descriptor */
  88. #define AG7XXX_ETH_DMA_RX_DESC 0x190
  89. /* Rx Status */
  90. #define AG7XXX_ETH_DMA_RX_STATUS 0x194
  91. /* Custom register at 0x1805002C */
  92. #define AG7XXX_ETH_XMII 0x2C
  93. #define AG7XXX_ETH_XMII_TX_INVERT BIT(31)
  94. #define AG7XXX_ETH_XMII_RX_DELAY_LSB 28
  95. #define AG7XXX_ETH_XMII_RX_DELAY_MASK 0x30000000
  96. #define AG7XXX_ETH_XMII_RX_DELAY_SET(x) \
  97. (((x) << AG7XXX_ETH_XMII_RX_DELAY_LSB) & AG7XXX_ETH_XMII_RX_DELAY_MASK)
  98. #define AG7XXX_ETH_XMII_TX_DELAY_LSB 26
  99. #define AG7XXX_ETH_XMII_TX_DELAY_MASK 0x0c000000
  100. #define AG7XXX_ETH_XMII_TX_DELAY_SET(x) \
  101. (((x) << AG7XXX_ETH_XMII_TX_DELAY_LSB) & AG7XXX_ETH_XMII_TX_DELAY_MASK)
  102. #define AG7XXX_ETH_XMII_GIGE BIT(25)
  103. /* Custom register at 0x18070000 */
  104. #define AG7XXX_GMAC_ETH_CFG 0x00
  105. #define AG7XXX_ETH_CFG_RXDV_DELAY_LSB 16
  106. #define AG7XXX_ETH_CFG_RXDV_DELAY_MASK 0x00030000
  107. #define AG7XXX_ETH_CFG_RXDV_DELAY_SET(x) \
  108. (((x) << AG7XXX_ETH_CFG_RXDV_DELAY_LSB) & AG7XXX_ETH_CFG_RXDV_DELAY_MASK)
  109. #define AG7XXX_ETH_CFG_RXD_DELAY_LSB 14
  110. #define AG7XXX_ETH_CFG_RXD_DELAY_MASK 0x0000c000
  111. #define AG7XXX_ETH_CFG_RXD_DELAY_SET(x) \
  112. (((x) << AG7XXX_ETH_CFG_RXD_DELAY_LSB) & AG7XXX_ETH_CFG_RXD_DELAY_MASK)
  113. #define AG7XXX_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
  114. #define AG7XXX_ETH_CFG_SW_PHY_SWAP BIT(7)
  115. #define AG7XXX_ETH_CFG_SW_ONLY_MODE BIT(6)
  116. #define AG7XXX_ETH_CFG_GE0_ERR_EN BIT(5)
  117. #define AG7XXX_ETH_CFG_MII_GE0_SLAVE BIT(4)
  118. #define AG7XXX_ETH_CFG_MII_GE0_MASTER BIT(3)
  119. #define AG7XXX_ETH_CFG_GMII_GE0 BIT(2)
  120. #define AG7XXX_ETH_CFG_MII_GE0 BIT(1)
  121. #define AG7XXX_ETH_CFG_RGMII_GE0 BIT(0)
  122. #define CONFIG_TX_DESCR_NUM 8
  123. #define CONFIG_RX_DESCR_NUM 8
  124. #define CONFIG_ETH_BUFSIZE 2048
  125. #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
  126. #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
  127. /* DMA descriptor. */
  128. struct ag7xxx_dma_desc {
  129. u32 data_addr;
  130. #define AG7XXX_DMADESC_IS_EMPTY BIT(31)
  131. #define AG7XXX_DMADESC_FTPP_OVERRIDE_OFFSET 16
  132. #define AG7XXX_DMADESC_PKT_SIZE_OFFSET 0
  133. #define AG7XXX_DMADESC_PKT_SIZE_MASK 0xfff
  134. u32 config;
  135. u32 next_desc;
  136. u32 _pad[5];
  137. };
  138. struct ar7xxx_eth_priv {
  139. struct ag7xxx_dma_desc tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
  140. struct ag7xxx_dma_desc rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
  141. char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  142. char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  143. void __iomem *regs;
  144. void __iomem *phyregs;
  145. struct eth_device *dev;
  146. struct phy_device *phydev;
  147. struct mii_dev *bus;
  148. u32 interface;
  149. u32 tx_currdescnum;
  150. u32 rx_currdescnum;
  151. enum ag7xxx_model model;
  152. };
  153. /*
  154. * Switch and MDIO access
  155. */
  156. static int ag7xxx_switch_read(struct mii_dev *bus, int addr, int reg, u16 *val)
  157. {
  158. struct ar7xxx_eth_priv *priv = bus->priv;
  159. void __iomem *regs = priv->phyregs;
  160. int ret;
  161. writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
  162. writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
  163. regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
  164. writel(AG7XXX_ETH_MII_MGMT_CMD_READ,
  165. regs + AG7XXX_ETH_MII_MGMT_CMD);
  166. ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
  167. AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
  168. if (ret)
  169. return ret;
  170. *val = readl(regs + AG7XXX_ETH_MII_MGMT_STATUS) & 0xffff;
  171. writel(0x0, regs + AG7XXX_ETH_MII_MGMT_CMD);
  172. return 0;
  173. }
  174. static int ag7xxx_switch_write(struct mii_dev *bus, int addr, int reg, u16 val)
  175. {
  176. struct ar7xxx_eth_priv *priv = bus->priv;
  177. void __iomem *regs = priv->phyregs;
  178. int ret;
  179. writel((addr << AG7XXX_ETH_MII_MGMT_ADDRESS_SHIFT) | reg,
  180. regs + AG7XXX_ETH_MII_MGMT_ADDRESS);
  181. writel(val, regs + AG7XXX_ETH_MII_MGMT_CTRL);
  182. ret = wait_for_bit_le32(regs + AG7XXX_ETH_MII_MGMT_IND,
  183. AG7XXX_ETH_MII_MGMT_IND_BUSY, 0, 1000, 0);
  184. return ret;
  185. }
  186. static int ag7xxx_switch_reg_read(struct mii_dev *bus, int reg, u32 *val)
  187. {
  188. struct ar7xxx_eth_priv *priv = bus->priv;
  189. u32 phy_addr;
  190. u32 reg_addr;
  191. u32 phy_temp;
  192. u32 reg_temp;
  193. u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
  194. u16 rv = 0;
  195. int ret;
  196. if (priv->model == AG7XXX_MODEL_AG933X ||
  197. priv->model == AG7XXX_MODEL_AG953X) {
  198. phy_addr = 0x1f;
  199. reg_addr = 0x10;
  200. } else if (priv->model == AG7XXX_MODEL_AG934X ||
  201. priv->model == AG7XXX_MODEL_AG956X) {
  202. phy_addr = 0x18;
  203. reg_addr = 0x00;
  204. } else
  205. return -EINVAL;
  206. if (priv->model == AG7XXX_MODEL_AG956X)
  207. ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
  208. else
  209. ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
  210. if (ret)
  211. return ret;
  212. phy_temp = ((reg >> 6) & 0x7) | 0x10;
  213. if (priv->model == AG7XXX_MODEL_AG956X)
  214. reg_temp = reg_temp_w & 0x1f;
  215. else
  216. reg_temp = (reg >> 1) & 0x1e;
  217. *val = 0;
  218. ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 0, &rv);
  219. if (ret < 0)
  220. return ret;
  221. *val |= rv;
  222. if (priv->model == AG7XXX_MODEL_AG956X) {
  223. phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
  224. reg_temp = (reg_temp_w + 1) & 0x1f;
  225. ret = ag7xxx_switch_read(bus, phy_temp, reg_temp, &rv);
  226. } else {
  227. ret = ag7xxx_switch_read(bus, phy_temp, reg_temp | 1, &rv);
  228. }
  229. if (ret < 0)
  230. return ret;
  231. *val |= (rv << 16);
  232. return 0;
  233. }
  234. static int ag7xxx_switch_reg_write(struct mii_dev *bus, int reg, u32 val)
  235. {
  236. struct ar7xxx_eth_priv *priv = bus->priv;
  237. u32 phy_addr;
  238. u32 reg_addr;
  239. u32 phy_temp;
  240. u32 reg_temp;
  241. u32 reg_temp_w = (reg & 0xfffffffc) >> 1;
  242. int ret;
  243. if (priv->model == AG7XXX_MODEL_AG933X ||
  244. priv->model == AG7XXX_MODEL_AG953X) {
  245. phy_addr = 0x1f;
  246. reg_addr = 0x10;
  247. } else if (priv->model == AG7XXX_MODEL_AG934X ||
  248. priv->model == AG7XXX_MODEL_AG956X) {
  249. phy_addr = 0x18;
  250. reg_addr = 0x00;
  251. } else
  252. return -EINVAL;
  253. if (priv->model == AG7XXX_MODEL_AG956X)
  254. ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, (reg >> 9) & 0x1ff);
  255. else
  256. ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9);
  257. if (ret)
  258. return ret;
  259. if (priv->model == AG7XXX_MODEL_AG956X) {
  260. reg_temp = (reg_temp_w + 1) & 0x1f;
  261. phy_temp = (((reg_temp_w + 1) >> 5) & 0x7) | 0x10;
  262. } else {
  263. phy_temp = ((reg >> 6) & 0x7) | 0x10;
  264. reg_temp = (reg >> 1) & 0x1e;
  265. }
  266. /*
  267. * The switch on AR933x has some special register behavior, which
  268. * expects particular write order of their nibbles:
  269. * 0x40 ..... MSB first, LSB second
  270. * 0x50 ..... MSB first, LSB second
  271. * 0x98 ..... LSB first, MSB second
  272. * others ... don't care
  273. */
  274. if ((priv->model == AG7XXX_MODEL_AG933X) && (reg == 0x98)) {
  275. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
  276. if (ret < 0)
  277. return ret;
  278. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
  279. if (ret < 0)
  280. return ret;
  281. } else {
  282. if (priv->model == AG7XXX_MODEL_AG956X)
  283. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp, val >> 16);
  284. else
  285. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 1, val >> 16);
  286. if (ret < 0)
  287. return ret;
  288. if (priv->model == AG7XXX_MODEL_AG956X) {
  289. phy_temp = ((reg_temp_w >> 5) & 0x7) | 0x10;
  290. reg_temp = reg_temp_w & 0x1f;
  291. }
  292. ret = ag7xxx_switch_write(bus, phy_temp, reg_temp | 0, val & 0xffff);
  293. if (ret < 0)
  294. return ret;
  295. }
  296. return 0;
  297. }
  298. static int ag7xxx_mdio_rw(struct mii_dev *bus, int addr, int reg, u32 val)
  299. {
  300. u32 data;
  301. unsigned long start;
  302. int ret;
  303. /* No idea if this is long enough or too long */
  304. int timeout_ms = 1000;
  305. /* Dummy read followed by PHY read/write command. */
  306. ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
  307. if (ret < 0)
  308. return ret;
  309. data = val | (reg << 16) | (addr << 21) | BIT(30) | BIT(31);
  310. ret = ag7xxx_switch_reg_write(bus, 0x98, data);
  311. if (ret < 0)
  312. return ret;
  313. start = get_timer(0);
  314. /* Wait for operation to finish */
  315. do {
  316. ret = ag7xxx_switch_reg_read(bus, 0x98, &data);
  317. if (ret < 0)
  318. return ret;
  319. if (get_timer(start) > timeout_ms)
  320. return -ETIMEDOUT;
  321. } while (data & BIT(31));
  322. return data & 0xffff;
  323. }
  324. static int ag7xxx_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  325. {
  326. return ag7xxx_mdio_rw(bus, addr, reg, BIT(27));
  327. }
  328. static int ag7xxx_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  329. u16 val)
  330. {
  331. int ret;
  332. ret = ag7xxx_mdio_rw(bus, addr, reg, val);
  333. if (ret < 0)
  334. return ret;
  335. return 0;
  336. }
  337. /*
  338. * DMA ring handlers
  339. */
  340. static void ag7xxx_dma_clean_tx(struct udevice *dev)
  341. {
  342. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  343. struct ag7xxx_dma_desc *curr, *next;
  344. u32 start, end;
  345. int i;
  346. for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
  347. curr = &priv->tx_mac_descrtable[i];
  348. next = &priv->tx_mac_descrtable[(i + 1) % CONFIG_TX_DESCR_NUM];
  349. curr->data_addr = virt_to_phys(&priv->txbuffs[i * CONFIG_ETH_BUFSIZE]);
  350. curr->config = AG7XXX_DMADESC_IS_EMPTY;
  351. curr->next_desc = virt_to_phys(next);
  352. }
  353. priv->tx_currdescnum = 0;
  354. /* Cache: Flush descriptors, don't care about buffers. */
  355. start = (u32)(&priv->tx_mac_descrtable[0]);
  356. end = start + sizeof(priv->tx_mac_descrtable);
  357. flush_dcache_range(start, end);
  358. }
  359. static void ag7xxx_dma_clean_rx(struct udevice *dev)
  360. {
  361. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  362. struct ag7xxx_dma_desc *curr, *next;
  363. u32 start, end;
  364. int i;
  365. for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
  366. curr = &priv->rx_mac_descrtable[i];
  367. next = &priv->rx_mac_descrtable[(i + 1) % CONFIG_RX_DESCR_NUM];
  368. curr->data_addr = virt_to_phys(&priv->rxbuffs[i * CONFIG_ETH_BUFSIZE]);
  369. curr->config = AG7XXX_DMADESC_IS_EMPTY;
  370. curr->next_desc = virt_to_phys(next);
  371. }
  372. priv->rx_currdescnum = 0;
  373. /* Cache: Flush+Invalidate descriptors, Invalidate buffers. */
  374. start = (u32)(&priv->rx_mac_descrtable[0]);
  375. end = start + sizeof(priv->rx_mac_descrtable);
  376. flush_dcache_range(start, end);
  377. invalidate_dcache_range(start, end);
  378. start = (u32)&priv->rxbuffs;
  379. end = start + sizeof(priv->rxbuffs);
  380. invalidate_dcache_range(start, end);
  381. }
  382. /*
  383. * Ethernet I/O
  384. */
  385. static int ag7xxx_eth_send(struct udevice *dev, void *packet, int length)
  386. {
  387. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  388. struct ag7xxx_dma_desc *curr;
  389. u32 start, end;
  390. curr = &priv->tx_mac_descrtable[priv->tx_currdescnum];
  391. /* Cache: Invalidate descriptor. */
  392. start = (u32)curr;
  393. end = start + sizeof(*curr);
  394. invalidate_dcache_range(start, end);
  395. if (!(curr->config & AG7XXX_DMADESC_IS_EMPTY)) {
  396. printf("ag7xxx: Out of TX DMA descriptors!\n");
  397. return -EPERM;
  398. }
  399. /* Copy the packet into the data buffer. */
  400. memcpy(phys_to_virt(curr->data_addr), packet, length);
  401. curr->config = length & AG7XXX_DMADESC_PKT_SIZE_MASK;
  402. /* Cache: Flush descriptor, Flush buffer. */
  403. start = (u32)curr;
  404. end = start + sizeof(*curr);
  405. flush_dcache_range(start, end);
  406. start = (u32)phys_to_virt(curr->data_addr);
  407. end = start + length;
  408. flush_dcache_range(start, end);
  409. /* Load the DMA descriptor and start TX DMA. */
  410. writel(AG7XXX_ETH_DMA_TX_CTRL_TXE,
  411. priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
  412. /* Switch to next TX descriptor. */
  413. priv->tx_currdescnum = (priv->tx_currdescnum + 1) % CONFIG_TX_DESCR_NUM;
  414. return 0;
  415. }
  416. static int ag7xxx_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  417. {
  418. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  419. struct ag7xxx_dma_desc *curr;
  420. u32 start, end, length;
  421. curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
  422. /* Cache: Invalidate descriptor. */
  423. start = (u32)curr;
  424. end = start + sizeof(*curr);
  425. invalidate_dcache_range(start, end);
  426. /* No packets received. */
  427. if (curr->config & AG7XXX_DMADESC_IS_EMPTY)
  428. return -EAGAIN;
  429. length = curr->config & AG7XXX_DMADESC_PKT_SIZE_MASK;
  430. /* Cache: Invalidate buffer. */
  431. start = (u32)phys_to_virt(curr->data_addr);
  432. end = start + length;
  433. invalidate_dcache_range(start, end);
  434. /* Receive one packet and return length. */
  435. *packetp = phys_to_virt(curr->data_addr);
  436. return length;
  437. }
  438. static int ag7xxx_eth_free_pkt(struct udevice *dev, uchar *packet,
  439. int length)
  440. {
  441. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  442. struct ag7xxx_dma_desc *curr;
  443. u32 start, end;
  444. curr = &priv->rx_mac_descrtable[priv->rx_currdescnum];
  445. curr->config = AG7XXX_DMADESC_IS_EMPTY;
  446. /* Cache: Flush descriptor. */
  447. start = (u32)curr;
  448. end = start + sizeof(*curr);
  449. flush_dcache_range(start, end);
  450. /* Switch to next RX descriptor. */
  451. priv->rx_currdescnum = (priv->rx_currdescnum + 1) % CONFIG_RX_DESCR_NUM;
  452. return 0;
  453. }
  454. static int ag7xxx_eth_start(struct udevice *dev)
  455. {
  456. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  457. /* FIXME: Check if link up */
  458. /* Clear the DMA rings. */
  459. ag7xxx_dma_clean_tx(dev);
  460. ag7xxx_dma_clean_rx(dev);
  461. /* Load DMA descriptors and start the RX DMA. */
  462. writel(virt_to_phys(&priv->tx_mac_descrtable[priv->tx_currdescnum]),
  463. priv->regs + AG7XXX_ETH_DMA_TX_DESC);
  464. writel(virt_to_phys(&priv->rx_mac_descrtable[priv->rx_currdescnum]),
  465. priv->regs + AG7XXX_ETH_DMA_RX_DESC);
  466. writel(AG7XXX_ETH_DMA_RX_CTRL_RXE,
  467. priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
  468. return 0;
  469. }
  470. static void ag7xxx_eth_stop(struct udevice *dev)
  471. {
  472. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  473. /* Stop the TX DMA. */
  474. writel(0, priv->regs + AG7XXX_ETH_DMA_TX_CTRL);
  475. wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_TX_CTRL, ~0, 0,
  476. 1000, 0);
  477. /* Stop the RX DMA. */
  478. writel(0, priv->regs + AG7XXX_ETH_DMA_RX_CTRL);
  479. wait_for_bit_le32(priv->regs + AG7XXX_ETH_DMA_RX_CTRL, ~0, 0,
  480. 1000, 0);
  481. }
  482. /*
  483. * Hardware setup
  484. */
  485. static int ag7xxx_eth_write_hwaddr(struct udevice *dev)
  486. {
  487. struct eth_pdata *pdata = dev_get_platdata(dev);
  488. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  489. unsigned char *mac = pdata->enetaddr;
  490. u32 macid_lo, macid_hi;
  491. macid_hi = mac[3] | (mac[2] << 8) | (mac[1] << 16) | (mac[0] << 24);
  492. macid_lo = (mac[5] << 16) | (mac[4] << 24);
  493. writel(macid_lo, priv->regs + AG7XXX_ETH_ADDR1);
  494. writel(macid_hi, priv->regs + AG7XXX_ETH_ADDR2);
  495. return 0;
  496. }
  497. static void ag7xxx_hw_setup(struct udevice *dev)
  498. {
  499. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  500. u32 speed;
  501. setbits_be32(priv->regs + AG7XXX_ETH_CFG1,
  502. AG7XXX_ETH_CFG1_RX_RST | AG7XXX_ETH_CFG1_TX_RST |
  503. AG7XXX_ETH_CFG1_SOFT_RST);
  504. mdelay(10);
  505. writel(AG7XXX_ETH_CFG1_RX_EN | AG7XXX_ETH_CFG1_TX_EN,
  506. priv->regs + AG7XXX_ETH_CFG1);
  507. if (priv->interface == PHY_INTERFACE_MODE_RMII)
  508. speed = AG7XXX_ETH_CFG2_IF_10_100;
  509. else
  510. speed = AG7XXX_ETH_CFG2_IF_1000;
  511. clrsetbits_be32(priv->regs + AG7XXX_ETH_CFG2,
  512. AG7XXX_ETH_CFG2_IF_SPEED_MASK,
  513. speed | AG7XXX_ETH_CFG2_PAD_CRC_EN |
  514. AG7XXX_ETH_CFG2_LEN_CHECK);
  515. writel(0xfff0000, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
  516. writel(0x1fff, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
  517. writel(0x1f00, priv->regs + AG7XXX_ETH_FIFO_CFG_0);
  518. setbits_be32(priv->regs + AG7XXX_ETH_FIFO_CFG_4, 0x3ffff);
  519. writel(0x10ffff, priv->regs + AG7XXX_ETH_FIFO_CFG_1);
  520. writel(0xaaa0555, priv->regs + AG7XXX_ETH_FIFO_CFG_2);
  521. writel(0x7eccf, priv->regs + AG7XXX_ETH_FIFO_CFG_5);
  522. writel(0x1f00140, priv->regs + AG7XXX_ETH_FIFO_CFG_3);
  523. }
  524. static int ag7xxx_mii_get_div(void)
  525. {
  526. ulong freq = get_bus_freq(0);
  527. switch (freq / 1000000) {
  528. case 150: return 0x7;
  529. case 175: return 0x5;
  530. case 200: return 0x4;
  531. case 210: return 0x9;
  532. case 220: return 0x9;
  533. default: return 0x7;
  534. }
  535. }
  536. static int ag7xxx_mii_setup(struct udevice *dev)
  537. {
  538. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  539. int i, ret, div = ag7xxx_mii_get_div();
  540. u32 reg;
  541. if (priv->model == AG7XXX_MODEL_AG933X) {
  542. /* Unit 0 is PHY-less on AR9331, see datasheet Figure 2-3 */
  543. if (priv->interface == PHY_INTERFACE_MODE_RMII)
  544. return 0;
  545. }
  546. if (priv->model == AG7XXX_MODEL_AG934X)
  547. reg = 0x4;
  548. else if (priv->model == AG7XXX_MODEL_AG953X)
  549. reg = 0x2;
  550. else if (priv->model == AG7XXX_MODEL_AG956X)
  551. reg = 0x7;
  552. if (priv->model == AG7XXX_MODEL_AG934X ||
  553. priv->model == AG7XXX_MODEL_AG953X ||
  554. priv->model == AG7XXX_MODEL_AG956X) {
  555. writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | reg,
  556. priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
  557. writel(reg, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
  558. return 0;
  559. }
  560. for (i = 0; i < 10; i++) {
  561. writel(AG7XXX_ETH_MII_MGMT_CFG_RESET | div,
  562. priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
  563. writel(div, priv->regs + AG7XXX_ETH_MII_MGMT_CFG);
  564. /* Check the switch */
  565. ret = ag7xxx_switch_reg_read(priv->bus, 0x10c, &reg);
  566. if (ret)
  567. continue;
  568. if (reg != 0x18007fff)
  569. continue;
  570. return 0;
  571. }
  572. return -EINVAL;
  573. }
  574. static int ag933x_phy_setup_wan(struct udevice *dev)
  575. {
  576. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  577. /* Configure switch port 4 (GMAC0) */
  578. return ag7xxx_mdio_write(priv->bus, 4, 0, MII_BMCR, 0x9000);
  579. }
  580. static int ag933x_phy_setup_lan(struct udevice *dev)
  581. {
  582. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  583. int i, ret;
  584. u32 reg;
  585. /* Reset the switch */
  586. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  587. if (ret)
  588. return ret;
  589. reg |= BIT(31);
  590. ret = ag7xxx_switch_reg_write(priv->bus, 0, reg);
  591. if (ret)
  592. return ret;
  593. do {
  594. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  595. if (ret)
  596. return ret;
  597. } while (reg & BIT(31));
  598. /* Configure switch ports 0...3 (GMAC1) */
  599. for (i = 0; i < 4; i++) {
  600. ret = ag7xxx_mdio_write(priv->bus, 0x4, 0, MII_BMCR, 0x9000);
  601. if (ret)
  602. return ret;
  603. }
  604. /* Enable CPU port */
  605. ret = ag7xxx_switch_reg_write(priv->bus, 0x78, BIT(8));
  606. if (ret)
  607. return ret;
  608. for (i = 0; i < 4; i++) {
  609. ret = ag7xxx_switch_reg_write(priv->bus, i * 0x100, BIT(9));
  610. if (ret)
  611. return ret;
  612. }
  613. /* QM Control */
  614. ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
  615. if (ret)
  616. return ret;
  617. /* Disable Atheros header */
  618. ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
  619. if (ret)
  620. return ret;
  621. /* Tag priority mapping */
  622. ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
  623. if (ret)
  624. return ret;
  625. /* Enable ARP packets to the CPU */
  626. ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
  627. if (ret)
  628. return ret;
  629. reg |= 0x100000;
  630. ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg);
  631. if (ret)
  632. return ret;
  633. return 0;
  634. }
  635. static int ag953x_phy_setup_wan(struct udevice *dev)
  636. {
  637. int ret;
  638. u32 reg = 0;
  639. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  640. /* Set wan port connect to GE0 */
  641. ret = ag7xxx_switch_reg_read(priv->bus, 0x8, &reg);
  642. if (ret)
  643. return ret;
  644. ret = ag7xxx_switch_reg_write(priv->bus, 0x8, reg | BIT(28));
  645. if (ret)
  646. return ret;
  647. /* Configure switch port 4 (GMAC0) */
  648. ret = ag7xxx_switch_write(priv->bus, 4, MII_BMCR, 0x9000);
  649. if (ret)
  650. return ret;
  651. return 0;
  652. }
  653. static int ag953x_phy_setup_lan(struct udevice *dev)
  654. {
  655. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  656. int i, ret;
  657. u32 reg = 0;
  658. /* Reset the switch */
  659. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  660. if (ret)
  661. return ret;
  662. ret = ag7xxx_switch_reg_write(priv->bus, 0, reg | BIT(31));
  663. if (ret)
  664. return ret;
  665. do {
  666. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  667. if (ret)
  668. return ret;
  669. } while (reg & BIT(31));
  670. ret = ag7xxx_switch_reg_write(priv->bus, 0x100, 0x4e);
  671. if (ret)
  672. return ret;
  673. /* Set GMII mode */
  674. ret = ag7xxx_switch_reg_read(priv->bus, 0x4, &reg);
  675. if (ret)
  676. return ret;
  677. ret = ag7xxx_switch_reg_write(priv->bus, 0x4, reg | BIT(6));
  678. if (ret)
  679. return ret;
  680. /* Configure switch ports 0...4 (GMAC1) */
  681. for (i = 0; i < 5; i++) {
  682. ret = ag7xxx_switch_write(priv->bus, i, MII_BMCR, 0x9000);
  683. if (ret)
  684. return ret;
  685. }
  686. for (i = 0; i < 5; i++) {
  687. ret = ag7xxx_switch_reg_write(priv->bus, (i + 2) * 0x100, BIT(9));
  688. if (ret)
  689. return ret;
  690. }
  691. /* QM Control */
  692. ret = ag7xxx_switch_reg_write(priv->bus, 0x38, 0xc000050e);
  693. if (ret)
  694. return ret;
  695. /* Disable Atheros header */
  696. ret = ag7xxx_switch_reg_write(priv->bus, 0x104, 0x4004);
  697. if (ret)
  698. return ret;
  699. /* Tag priority mapping */
  700. ret = ag7xxx_switch_reg_write(priv->bus, 0x70, 0xfa50);
  701. if (ret)
  702. return ret;
  703. /* Enable ARP packets to the CPU */
  704. ret = ag7xxx_switch_reg_read(priv->bus, 0x5c, &reg);
  705. if (ret)
  706. return ret;
  707. ret = ag7xxx_switch_reg_write(priv->bus, 0x5c, reg | 0x100000);
  708. if (ret)
  709. return ret;
  710. /* Enable broadcast packets to the CPU */
  711. ret = ag7xxx_switch_reg_read(priv->bus, 0x2c, &reg);
  712. if (ret)
  713. return ret;
  714. ret = ag7xxx_switch_reg_write(priv->bus, 0x2c, reg | BIT(25) | BIT(26));
  715. if (ret)
  716. return ret;
  717. return 0;
  718. }
  719. static int ag933x_phy_setup_reset_set(struct udevice *dev, int port)
  720. {
  721. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  722. int ret;
  723. if (priv->model == AG7XXX_MODEL_AG953X ||
  724. priv->model == AG7XXX_MODEL_AG956X) {
  725. ret = ag7xxx_switch_write(priv->bus, port, MII_ADVERTISE,
  726. ADVERTISE_ALL);
  727. } else {
  728. ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_ADVERTISE,
  729. ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
  730. ADVERTISE_PAUSE_ASYM);
  731. }
  732. if (ret)
  733. return ret;
  734. if (priv->model == AG7XXX_MODEL_AG934X) {
  735. ret = ag7xxx_mdio_write(priv->bus, port, 0, MII_CTRL1000,
  736. ADVERTISE_1000FULL);
  737. if (ret)
  738. return ret;
  739. } else if (priv->model == AG7XXX_MODEL_AG956X) {
  740. ret = ag7xxx_switch_write(priv->bus, port, MII_CTRL1000,
  741. ADVERTISE_1000FULL);
  742. if (ret)
  743. return ret;
  744. }
  745. if (priv->model == AG7XXX_MODEL_AG953X ||
  746. priv->model == AG7XXX_MODEL_AG956X)
  747. return ag7xxx_switch_write(priv->bus, port, MII_BMCR,
  748. BMCR_ANENABLE | BMCR_RESET);
  749. return ag7xxx_mdio_write(priv->bus, port, 0, MII_BMCR,
  750. BMCR_ANENABLE | BMCR_RESET);
  751. }
  752. static int ag933x_phy_setup_reset_fin(struct udevice *dev, int port)
  753. {
  754. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  755. int ret;
  756. u16 reg;
  757. if (priv->model == AG7XXX_MODEL_AG953X ||
  758. priv->model == AG7XXX_MODEL_AG956X) {
  759. do {
  760. ret = ag7xxx_switch_read(priv->bus, port, MII_BMCR, &reg);
  761. if (ret < 0)
  762. return ret;
  763. mdelay(10);
  764. } while (reg & BMCR_RESET);
  765. } else {
  766. do {
  767. ret = ag7xxx_mdio_read(priv->bus, port, 0, MII_BMCR);
  768. if (ret < 0)
  769. return ret;
  770. mdelay(10);
  771. } while (ret & BMCR_RESET);
  772. }
  773. return 0;
  774. }
  775. static int ag933x_phy_setup_common(struct udevice *dev)
  776. {
  777. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  778. int i, ret, phymax;
  779. u16 reg;
  780. if (priv->model == AG7XXX_MODEL_AG933X)
  781. phymax = 4;
  782. else if (priv->model == AG7XXX_MODEL_AG934X ||
  783. priv->model == AG7XXX_MODEL_AG953X ||
  784. priv->model == AG7XXX_MODEL_AG956X)
  785. phymax = 5;
  786. else
  787. return -EINVAL;
  788. if (priv->interface == PHY_INTERFACE_MODE_RMII) {
  789. ret = ag933x_phy_setup_reset_set(dev, phymax);
  790. if (ret)
  791. return ret;
  792. ret = ag933x_phy_setup_reset_fin(dev, phymax);
  793. if (ret)
  794. return ret;
  795. /* Read out link status */
  796. if (priv->model == AG7XXX_MODEL_AG953X)
  797. ret = ag7xxx_switch_read(priv->bus, phymax, MII_MIPSCR, &reg);
  798. else
  799. ret = ag7xxx_mdio_read(priv->bus, phymax, 0, MII_MIPSCR);
  800. if (ret < 0)
  801. return ret;
  802. return 0;
  803. }
  804. /* Switch ports */
  805. for (i = 0; i < phymax; i++) {
  806. ret = ag933x_phy_setup_reset_set(dev, i);
  807. if (ret)
  808. return ret;
  809. }
  810. for (i = 0; i < phymax; i++) {
  811. ret = ag933x_phy_setup_reset_fin(dev, i);
  812. if (ret)
  813. return ret;
  814. }
  815. for (i = 0; i < phymax; i++) {
  816. /* Read out link status */
  817. if (priv->model == AG7XXX_MODEL_AG953X ||
  818. priv->model == AG7XXX_MODEL_AG956X)
  819. ret = ag7xxx_switch_read(priv->bus, i, MII_MIPSCR, &reg);
  820. else
  821. ret = ag7xxx_mdio_read(priv->bus, i, 0, MII_MIPSCR);
  822. if (ret < 0)
  823. return ret;
  824. }
  825. return 0;
  826. }
  827. static int ag934x_phy_setup(struct udevice *dev)
  828. {
  829. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  830. int i, ret;
  831. u32 reg;
  832. ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
  833. if (ret)
  834. return ret;
  835. ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x40000000);
  836. if (ret)
  837. return ret;
  838. ret = ag7xxx_switch_reg_write(priv->bus, 0x4, 0x07600000);
  839. if (ret)
  840. return ret;
  841. ret = ag7xxx_switch_reg_write(priv->bus, 0xc, 0x01000000);
  842. if (ret)
  843. return ret;
  844. ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
  845. if (ret)
  846. return ret;
  847. /* AR8327/AR8328 v1.0 fixup */
  848. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  849. if (ret)
  850. return ret;
  851. if ((reg & 0xffff) == 0x1201) {
  852. for (i = 0; i < 5; i++) {
  853. ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x0);
  854. if (ret)
  855. return ret;
  856. ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x02ea);
  857. if (ret)
  858. return ret;
  859. ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1d, 0x3d);
  860. if (ret)
  861. return ret;
  862. ret = ag7xxx_mdio_write(priv->bus, i, 0, 0x1e, 0x68a0);
  863. if (ret)
  864. return ret;
  865. }
  866. }
  867. ret = ag7xxx_switch_reg_read(priv->bus, 0x66c, &reg);
  868. if (ret)
  869. return ret;
  870. reg &= ~0x70000;
  871. ret = ag7xxx_switch_reg_write(priv->bus, 0x66c, reg);
  872. if (ret)
  873. return ret;
  874. return 0;
  875. }
  876. static int ag956x_phy_setup(struct udevice *dev)
  877. {
  878. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  879. int i, ret;
  880. u32 reg, ctrl;
  881. ret = ag7xxx_switch_reg_read(priv->bus, 0x0, &reg);
  882. if (ret)
  883. return ret;
  884. if ((reg & 0xffff) >= 0x1301)
  885. ctrl = 0xc74164de;
  886. else
  887. ctrl = 0xc74164d0;
  888. ret = ag7xxx_switch_reg_write(priv->bus, 0x4, BIT(7));
  889. if (ret)
  890. return ret;
  891. ret = ag7xxx_switch_reg_write(priv->bus, 0xe0, ctrl);
  892. if (ret)
  893. return ret;
  894. ret = ag7xxx_switch_reg_write(priv->bus, 0x624, 0x7f7f7f7f);
  895. if (ret)
  896. return ret;
  897. /*
  898. * Values suggested by the switch team when s17 in sgmii
  899. * configuration. 0x10(S17_PWS_REG) = 0x602613a0
  900. */
  901. ret = ag7xxx_switch_reg_write(priv->bus, 0x10, 0x602613a0);
  902. if (ret)
  903. return ret;
  904. ret = ag7xxx_switch_reg_write(priv->bus, 0x7c, 0x0000007e);
  905. if (ret)
  906. return ret;
  907. /* AR8337/AR8334 v1.0 fixup */
  908. ret = ag7xxx_switch_reg_read(priv->bus, 0, &reg);
  909. if (ret)
  910. return ret;
  911. if ((reg & 0xffff) == 0x1301) {
  912. for (i = 0; i < 5; i++) {
  913. /* Turn on Gigabit clock */
  914. ret = ag7xxx_switch_write(priv->bus, i, 0x1d, 0x3d);
  915. if (ret)
  916. return ret;
  917. ret = ag7xxx_switch_write(priv->bus, i, 0x1e, 0x6820);
  918. if (ret)
  919. return ret;
  920. }
  921. }
  922. return 0;
  923. }
  924. static int ag7xxx_mac_probe(struct udevice *dev)
  925. {
  926. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  927. int ret;
  928. ag7xxx_hw_setup(dev);
  929. ret = ag7xxx_mii_setup(dev);
  930. if (ret)
  931. return ret;
  932. ag7xxx_eth_write_hwaddr(dev);
  933. if (priv->model == AG7XXX_MODEL_AG933X) {
  934. if (priv->interface == PHY_INTERFACE_MODE_RMII)
  935. ret = ag933x_phy_setup_wan(dev);
  936. else
  937. ret = ag933x_phy_setup_lan(dev);
  938. } else if (priv->model == AG7XXX_MODEL_AG953X) {
  939. if (priv->interface == PHY_INTERFACE_MODE_RMII)
  940. ret = ag953x_phy_setup_wan(dev);
  941. else
  942. ret = ag953x_phy_setup_lan(dev);
  943. } else if (priv->model == AG7XXX_MODEL_AG934X) {
  944. ret = ag934x_phy_setup(dev);
  945. } else if (priv->model == AG7XXX_MODEL_AG956X) {
  946. ret = ag956x_phy_setup(dev);
  947. } else {
  948. return -EINVAL;
  949. }
  950. if (ret)
  951. return ret;
  952. return ag933x_phy_setup_common(dev);
  953. }
  954. static int ag7xxx_mdio_probe(struct udevice *dev)
  955. {
  956. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  957. struct mii_dev *bus = mdio_alloc();
  958. if (!bus)
  959. return -ENOMEM;
  960. bus->read = ag7xxx_mdio_read;
  961. bus->write = ag7xxx_mdio_write;
  962. snprintf(bus->name, sizeof(bus->name), dev->name);
  963. bus->priv = (void *)priv;
  964. return mdio_register(bus);
  965. }
  966. static int ag7xxx_get_phy_iface_offset(struct udevice *dev)
  967. {
  968. int offset;
  969. offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "phy");
  970. if (offset <= 0) {
  971. debug("%s: PHY OF node not found (ret=%i)\n", __func__, offset);
  972. return -EINVAL;
  973. }
  974. offset = fdt_parent_offset(gd->fdt_blob, offset);
  975. if (offset <= 0) {
  976. debug("%s: PHY OF node parent MDIO bus not found (ret=%i)\n",
  977. __func__, offset);
  978. return -EINVAL;
  979. }
  980. offset = fdt_parent_offset(gd->fdt_blob, offset);
  981. if (offset <= 0) {
  982. debug("%s: PHY MDIO OF node parent MAC not found (ret=%i)\n",
  983. __func__, offset);
  984. return -EINVAL;
  985. }
  986. return offset;
  987. }
  988. static int ag7xxx_eth_probe(struct udevice *dev)
  989. {
  990. struct eth_pdata *pdata = dev_get_platdata(dev);
  991. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  992. void __iomem *iobase, *phyiobase;
  993. int ret, phyreg;
  994. /* Decoding of convoluted PHY wiring on Atheros MIPS. */
  995. ret = ag7xxx_get_phy_iface_offset(dev);
  996. if (ret <= 0)
  997. return ret;
  998. phyreg = fdtdec_get_int(gd->fdt_blob, ret, "reg", -1);
  999. iobase = map_physmem(pdata->iobase, 0x200, MAP_NOCACHE);
  1000. phyiobase = map_physmem(phyreg, 0x200, MAP_NOCACHE);
  1001. debug("%s, iobase=%p, phyiobase=%p, priv=%p\n",
  1002. __func__, iobase, phyiobase, priv);
  1003. priv->regs = iobase;
  1004. priv->phyregs = phyiobase;
  1005. priv->interface = pdata->phy_interface;
  1006. priv->model = dev_get_driver_data(dev);
  1007. ret = ag7xxx_mdio_probe(dev);
  1008. if (ret)
  1009. return ret;
  1010. priv->bus = miiphy_get_dev_by_name(dev->name);
  1011. ret = ag7xxx_mac_probe(dev);
  1012. debug("%s, ret=%d\n", __func__, ret);
  1013. return ret;
  1014. }
  1015. static int ag7xxx_eth_remove(struct udevice *dev)
  1016. {
  1017. struct ar7xxx_eth_priv *priv = dev_get_priv(dev);
  1018. free(priv->phydev);
  1019. mdio_unregister(priv->bus);
  1020. mdio_free(priv->bus);
  1021. return 0;
  1022. }
  1023. static const struct eth_ops ag7xxx_eth_ops = {
  1024. .start = ag7xxx_eth_start,
  1025. .send = ag7xxx_eth_send,
  1026. .recv = ag7xxx_eth_recv,
  1027. .free_pkt = ag7xxx_eth_free_pkt,
  1028. .stop = ag7xxx_eth_stop,
  1029. .write_hwaddr = ag7xxx_eth_write_hwaddr,
  1030. };
  1031. static int ag7xxx_eth_ofdata_to_platdata(struct udevice *dev)
  1032. {
  1033. struct eth_pdata *pdata = dev_get_platdata(dev);
  1034. const char *phy_mode;
  1035. int ret;
  1036. pdata->iobase = dev_read_addr(dev);
  1037. pdata->phy_interface = -1;
  1038. /* Decoding of convoluted PHY wiring on Atheros MIPS. */
  1039. ret = ag7xxx_get_phy_iface_offset(dev);
  1040. if (ret <= 0)
  1041. return ret;
  1042. phy_mode = fdt_getprop(gd->fdt_blob, ret, "phy-mode", NULL);
  1043. if (phy_mode)
  1044. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  1045. if (pdata->phy_interface == -1) {
  1046. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  1047. return -EINVAL;
  1048. }
  1049. return 0;
  1050. }
  1051. static const struct udevice_id ag7xxx_eth_ids[] = {
  1052. { .compatible = "qca,ag933x-mac", .data = AG7XXX_MODEL_AG933X },
  1053. { .compatible = "qca,ag934x-mac", .data = AG7XXX_MODEL_AG934X },
  1054. { .compatible = "qca,ag953x-mac", .data = AG7XXX_MODEL_AG953X },
  1055. { .compatible = "qca,ag956x-mac", .data = AG7XXX_MODEL_AG956X },
  1056. { }
  1057. };
  1058. U_BOOT_DRIVER(eth_ag7xxx) = {
  1059. .name = "eth_ag7xxx",
  1060. .id = UCLASS_ETH,
  1061. .of_match = ag7xxx_eth_ids,
  1062. .ofdata_to_platdata = ag7xxx_eth_ofdata_to_platdata,
  1063. .probe = ag7xxx_eth_probe,
  1064. .remove = ag7xxx_eth_remove,
  1065. .ops = &ag7xxx_eth_ops,
  1066. .priv_auto_alloc_size = sizeof(struct ar7xxx_eth_priv),
  1067. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  1068. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  1069. };