bcmstb_sdhci.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018 Cisco Systems, Inc.
  4. * (C) Copyright 2019 Synamedia
  5. *
  6. * Author: Thomas Fitzsimmons <fitzsim@fitzsim.org>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <mach/sdhci.h>
  11. #include <malloc.h>
  12. #include <sdhci.h>
  13. /*
  14. * The BCMSTB SDHCI has a quirk in that its actual maximum frequency
  15. * capability is 100 MHz. The divisor that is eventually written to
  16. * SDHCI_CLOCK_CONTROL is calculated based on what the MMC device
  17. * reports, and relative to this maximum frequency.
  18. *
  19. * This define used to be set to 52000000 (52 MHz), the desired
  20. * maximum frequency, but that would result in the communication
  21. * actually running at 100 MHz (seemingly without issue), which is
  22. * out-of-spec.
  23. *
  24. * Now, by setting this to 0 (auto-detect), 100 MHz will be read from
  25. * the capabilities register, and the resulting divisor will be
  26. * doubled, meaning that the clock control register will be set to the
  27. * in-spec 52 MHz value.
  28. */
  29. #define BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY 0
  30. /*
  31. * When the minimum clock frequency is set to 0 (auto-detect), U-Boot
  32. * sets it to 100 MHz divided by SDHCI_MAX_DIV_SPEC_300, or 48,875 Hz,
  33. * which results in the controller timing out when trying to
  34. * communicate with the MMC device. Hard-code this value to 400000
  35. * (400 kHz) to prevent this.
  36. */
  37. #define BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY 400000
  38. /*
  39. * This driver has only been tested with eMMC devices; SD devices may
  40. * not work.
  41. */
  42. struct sdhci_bcmstb_plat {
  43. struct mmc_config cfg;
  44. struct mmc mmc;
  45. };
  46. static int sdhci_bcmstb_bind(struct udevice *dev)
  47. {
  48. struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
  49. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  50. }
  51. static int sdhci_bcmstb_probe(struct udevice *dev)
  52. {
  53. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  54. struct sdhci_bcmstb_plat *plat = dev_get_platdata(dev);
  55. struct sdhci_host *host = dev_get_priv(dev);
  56. fdt_addr_t base;
  57. int ret;
  58. base = dev_read_addr(dev);
  59. if (base == FDT_ADDR_T_NONE)
  60. return -EINVAL;
  61. host->name = dev->name;
  62. host->ioaddr = (void *)base;
  63. ret = mmc_of_parse(dev, &plat->cfg);
  64. if (ret)
  65. return ret;
  66. host->mmc = &plat->mmc;
  67. host->mmc->dev = dev;
  68. ret = sdhci_setup_cfg(&plat->cfg, host,
  69. BCMSTB_SDHCI_MAXIMUM_CLOCK_FREQUENCY,
  70. BCMSTB_SDHCI_MINIMUM_CLOCK_FREQUENCY);
  71. if (ret)
  72. return ret;
  73. upriv->mmc = &plat->mmc;
  74. host->mmc->priv = host;
  75. return sdhci_probe(dev);
  76. }
  77. static const struct udevice_id sdhci_bcmstb_match[] = {
  78. { .compatible = "brcm,bcm7425-sdhci" },
  79. { .compatible = "brcm,sdhci-brcmstb" },
  80. { }
  81. };
  82. U_BOOT_DRIVER(sdhci_bcmstb) = {
  83. .name = "sdhci-bcmstb",
  84. .id = UCLASS_MMC,
  85. .of_match = sdhci_bcmstb_match,
  86. .ops = &sdhci_ops,
  87. .bind = sdhci_bcmstb_bind,
  88. .probe = sdhci_bcmstb_probe,
  89. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  90. .platdata_auto_alloc_size = sizeof(struct sdhci_bcmstb_plat),
  91. };