bcm2835_sdhost.c 21 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * bcm2835 sdhost driver.
  4. *
  5. * The 2835 has two SD controllers: The Arasan sdhci controller
  6. * (supported by the iproc driver) and a custom sdhost controller
  7. * (supported by this driver).
  8. *
  9. * The sdhci controller supports both sdcard and sdio. The sdhost
  10. * controller supports the sdcard only, but has better performance.
  11. * Also note that the rpi3 has sdio wifi, so driving the sdcard with
  12. * the sdhost controller allows to use the sdhci controller for wifi
  13. * support.
  14. *
  15. * The configuration is done by devicetree via pin muxing. Both
  16. * SD controller are available on the same pins (2 pin groups = pin 22
  17. * to 27 + pin 48 to 53). So it's possible to use both SD controllers
  18. * at the same time with different pin groups.
  19. *
  20. * This code was ported to U-Boot by
  21. * Alexander Graf <agraf@suse.de>
  22. * and is based on drivers/mmc/host/bcm2835.c in Linux which is written by
  23. * Phil Elwell <phil@raspberrypi.org>
  24. * Copyright (C) 2015-2016 Raspberry Pi (Trading) Ltd.
  25. * which is based on
  26. * mmc-bcm2835.c by Gellert Weisz
  27. * which is, in turn, based on
  28. * sdhci-bcm2708.c by Broadcom
  29. * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
  30. * sdhci.c and sdhci-pci.c by Pierre Ossman
  31. */
  32. #include <clk.h>
  33. #include <common.h>
  34. #include <dm.h>
  35. #include <mmc.h>
  36. #include <asm/arch/msg.h>
  37. #include <asm/arch/mbox.h>
  38. #include <asm/unaligned.h>
  39. #include <dm/device_compat.h>
  40. #include <linux/bitops.h>
  41. #include <linux/bug.h>
  42. #include <linux/compat.h>
  43. #include <linux/delay.h>
  44. #include <linux/io.h>
  45. #include <linux/iopoll.h>
  46. #include <linux/sizes.h>
  47. #include <mach/gpio.h>
  48. #include <power/regulator.h>
  49. #define msleep(a) udelay(a * 1000)
  50. #define SDCMD 0x00 /* Command to SD card - 16 R/W */
  51. #define SDARG 0x04 /* Argument to SD card - 32 R/W */
  52. #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */
  53. #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */
  54. #define SDRSP0 0x10 /* SD card response (31:0) - 32 R */
  55. #define SDRSP1 0x14 /* SD card response (63:32) - 32 R */
  56. #define SDRSP2 0x18 /* SD card response (95:64) - 32 R */
  57. #define SDRSP3 0x1c /* SD card response (127:96) - 32 R */
  58. #define SDHSTS 0x20 /* SD host status - 11 R/W */
  59. #define SDVDD 0x30 /* SD card power control - 1 R/W */
  60. #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */
  61. #define SDHCFG 0x38 /* Host configuration - 2 R/W */
  62. #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */
  63. #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */
  64. #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */
  65. #define SDCMD_NEW_FLAG 0x8000
  66. #define SDCMD_FAIL_FLAG 0x4000
  67. #define SDCMD_BUSYWAIT 0x800
  68. #define SDCMD_NO_RESPONSE 0x400
  69. #define SDCMD_LONG_RESPONSE 0x200
  70. #define SDCMD_WRITE_CMD 0x80
  71. #define SDCMD_READ_CMD 0x40
  72. #define SDCMD_CMD_MASK 0x3f
  73. #define SDCDIV_MAX_CDIV 0x7ff
  74. #define SDHSTS_BUSY_IRPT 0x400
  75. #define SDHSTS_BLOCK_IRPT 0x200
  76. #define SDHSTS_SDIO_IRPT 0x100
  77. #define SDHSTS_REW_TIME_OUT 0x80
  78. #define SDHSTS_CMD_TIME_OUT 0x40
  79. #define SDHSTS_CRC16_ERROR 0x20
  80. #define SDHSTS_CRC7_ERROR 0x10
  81. #define SDHSTS_FIFO_ERROR 0x08
  82. #define SDHSTS_DATA_FLAG 0x01
  83. #define SDHSTS_CLEAR_MASK (SDHSTS_BUSY_IRPT | \
  84. SDHSTS_BLOCK_IRPT | \
  85. SDHSTS_SDIO_IRPT | \
  86. SDHSTS_REW_TIME_OUT | \
  87. SDHSTS_CMD_TIME_OUT | \
  88. SDHSTS_CRC16_ERROR | \
  89. SDHSTS_CRC7_ERROR | \
  90. SDHSTS_FIFO_ERROR)
  91. #define SDHSTS_TRANSFER_ERROR_MASK (SDHSTS_CRC7_ERROR | \
  92. SDHSTS_CRC16_ERROR | \
  93. SDHSTS_REW_TIME_OUT | \
  94. SDHSTS_FIFO_ERROR)
  95. #define SDHSTS_ERROR_MASK (SDHSTS_CMD_TIME_OUT | \
  96. SDHSTS_TRANSFER_ERROR_MASK)
  97. #define SDHCFG_BUSY_IRPT_EN BIT(10)
  98. #define SDHCFG_BLOCK_IRPT_EN BIT(8)
  99. #define SDHCFG_SDIO_IRPT_EN BIT(5)
  100. #define SDHCFG_DATA_IRPT_EN BIT(4)
  101. #define SDHCFG_SLOW_CARD BIT(3)
  102. #define SDHCFG_WIDE_EXT_BUS BIT(2)
  103. #define SDHCFG_WIDE_INT_BUS BIT(1)
  104. #define SDHCFG_REL_CMD_LINE BIT(0)
  105. #define SDVDD_POWER_OFF 0
  106. #define SDVDD_POWER_ON 1
  107. #define SDEDM_FORCE_DATA_MODE BIT(19)
  108. #define SDEDM_CLOCK_PULSE BIT(20)
  109. #define SDEDM_BYPASS BIT(21)
  110. #define SDEDM_FIFO_FILL_SHIFT 4
  111. #define SDEDM_FIFO_FILL_MASK 0x1f
  112. static u32 edm_fifo_fill(u32 edm)
  113. {
  114. return (edm >> SDEDM_FIFO_FILL_SHIFT) & SDEDM_FIFO_FILL_MASK;
  115. }
  116. #define SDEDM_WRITE_THRESHOLD_SHIFT 9
  117. #define SDEDM_READ_THRESHOLD_SHIFT 14
  118. #define SDEDM_THRESHOLD_MASK 0x1f
  119. #define SDEDM_FSM_MASK 0xf
  120. #define SDEDM_FSM_IDENTMODE 0x0
  121. #define SDEDM_FSM_DATAMODE 0x1
  122. #define SDEDM_FSM_READDATA 0x2
  123. #define SDEDM_FSM_WRITEDATA 0x3
  124. #define SDEDM_FSM_READWAIT 0x4
  125. #define SDEDM_FSM_READCRC 0x5
  126. #define SDEDM_FSM_WRITECRC 0x6
  127. #define SDEDM_FSM_WRITEWAIT1 0x7
  128. #define SDEDM_FSM_POWERDOWN 0x8
  129. #define SDEDM_FSM_POWERUP 0x9
  130. #define SDEDM_FSM_WRITESTART1 0xa
  131. #define SDEDM_FSM_WRITESTART2 0xb
  132. #define SDEDM_FSM_GENPULSES 0xc
  133. #define SDEDM_FSM_WRITEWAIT2 0xd
  134. #define SDEDM_FSM_STARTPOWDOWN 0xf
  135. #define SDDATA_FIFO_WORDS 16
  136. #define FIFO_READ_THRESHOLD 4
  137. #define FIFO_WRITE_THRESHOLD 4
  138. #define SDDATA_FIFO_PIO_BURST 8
  139. #define SDHST_TIMEOUT_MAX_USEC 100000
  140. struct bcm2835_plat {
  141. struct mmc_config cfg;
  142. struct mmc mmc;
  143. };
  144. struct bcm2835_host {
  145. void __iomem *ioaddr;
  146. u32 phys_addr;
  147. int clock; /* Current clock speed */
  148. unsigned int max_clk; /* Max possible freq */
  149. unsigned int blocks; /* remaining PIO blocks */
  150. u32 ns_per_fifo_word;
  151. /* cached registers */
  152. u32 hcfg;
  153. u32 cdiv;
  154. struct mmc_cmd *cmd; /* Current command */
  155. struct mmc_data *data; /* Current data request */
  156. bool use_busy:1; /* Wait for busy interrupt */
  157. struct udevice *dev;
  158. struct mmc *mmc;
  159. struct bcm2835_plat *plat;
  160. };
  161. static void bcm2835_dumpregs(struct bcm2835_host *host)
  162. {
  163. dev_dbg(dev, "=========== REGISTER DUMP ===========\n");
  164. dev_dbg(dev, "SDCMD 0x%08x\n", readl(host->ioaddr + SDCMD));
  165. dev_dbg(dev, "SDARG 0x%08x\n", readl(host->ioaddr + SDARG));
  166. dev_dbg(dev, "SDTOUT 0x%08x\n", readl(host->ioaddr + SDTOUT));
  167. dev_dbg(dev, "SDCDIV 0x%08x\n", readl(host->ioaddr + SDCDIV));
  168. dev_dbg(dev, "SDRSP0 0x%08x\n", readl(host->ioaddr + SDRSP0));
  169. dev_dbg(dev, "SDRSP1 0x%08x\n", readl(host->ioaddr + SDRSP1));
  170. dev_dbg(dev, "SDRSP2 0x%08x\n", readl(host->ioaddr + SDRSP2));
  171. dev_dbg(dev, "SDRSP3 0x%08x\n", readl(host->ioaddr + SDRSP3));
  172. dev_dbg(dev, "SDHSTS 0x%08x\n", readl(host->ioaddr + SDHSTS));
  173. dev_dbg(dev, "SDVDD 0x%08x\n", readl(host->ioaddr + SDVDD));
  174. dev_dbg(dev, "SDEDM 0x%08x\n", readl(host->ioaddr + SDEDM));
  175. dev_dbg(dev, "SDHCFG 0x%08x\n", readl(host->ioaddr + SDHCFG));
  176. dev_dbg(dev, "SDHBCT 0x%08x\n", readl(host->ioaddr + SDHBCT));
  177. dev_dbg(dev, "SDHBLC 0x%08x\n", readl(host->ioaddr + SDHBLC));
  178. dev_dbg(dev, "===========================================\n");
  179. }
  180. static void bcm2835_reset_internal(struct bcm2835_host *host)
  181. {
  182. u32 temp;
  183. writel(SDVDD_POWER_OFF, host->ioaddr + SDVDD);
  184. writel(0, host->ioaddr + SDCMD);
  185. writel(0, host->ioaddr + SDARG);
  186. /* Set timeout to a big enough value so we don't hit it */
  187. writel(0xf00000, host->ioaddr + SDTOUT);
  188. writel(0, host->ioaddr + SDCDIV);
  189. /* Clear status register */
  190. writel(SDHSTS_CLEAR_MASK, host->ioaddr + SDHSTS);
  191. writel(0, host->ioaddr + SDHCFG);
  192. writel(0, host->ioaddr + SDHBCT);
  193. writel(0, host->ioaddr + SDHBLC);
  194. /* Limit fifo usage due to silicon bug */
  195. temp = readl(host->ioaddr + SDEDM);
  196. temp &= ~((SDEDM_THRESHOLD_MASK << SDEDM_READ_THRESHOLD_SHIFT) |
  197. (SDEDM_THRESHOLD_MASK << SDEDM_WRITE_THRESHOLD_SHIFT));
  198. temp |= (FIFO_READ_THRESHOLD << SDEDM_READ_THRESHOLD_SHIFT) |
  199. (FIFO_WRITE_THRESHOLD << SDEDM_WRITE_THRESHOLD_SHIFT);
  200. writel(temp, host->ioaddr + SDEDM);
  201. /* Wait for FIFO threshold to populate */
  202. msleep(20);
  203. writel(SDVDD_POWER_ON, host->ioaddr + SDVDD);
  204. /* Wait for all components to go through power on cycle */
  205. msleep(20);
  206. host->clock = 0;
  207. writel(host->hcfg, host->ioaddr + SDHCFG);
  208. writel(host->cdiv, host->ioaddr + SDCDIV);
  209. }
  210. static int bcm2835_wait_transfer_complete(struct bcm2835_host *host)
  211. {
  212. ulong tstart_ms = get_timer(0);
  213. while (1) {
  214. u32 edm, fsm;
  215. edm = readl(host->ioaddr + SDEDM);
  216. fsm = edm & SDEDM_FSM_MASK;
  217. if ((fsm == SDEDM_FSM_IDENTMODE) ||
  218. (fsm == SDEDM_FSM_DATAMODE))
  219. break;
  220. if ((fsm == SDEDM_FSM_READWAIT) ||
  221. (fsm == SDEDM_FSM_WRITESTART1) ||
  222. (fsm == SDEDM_FSM_READDATA)) {
  223. writel(edm | SDEDM_FORCE_DATA_MODE,
  224. host->ioaddr + SDEDM);
  225. break;
  226. }
  227. /* Error out after ~1s */
  228. ulong tlapse_ms = get_timer(tstart_ms);
  229. if ( tlapse_ms > 1000 /* ms */ ) {
  230. dev_err(host->dev,
  231. "wait_transfer_complete - still waiting after %lu ms\n",
  232. tlapse_ms);
  233. bcm2835_dumpregs(host);
  234. return -ETIMEDOUT;
  235. }
  236. }
  237. return 0;
  238. }
  239. static int bcm2835_transfer_block_pio(struct bcm2835_host *host, bool is_read)
  240. {
  241. struct mmc_data *data = host->data;
  242. size_t blksize = data->blocksize;
  243. int copy_words;
  244. u32 hsts = 0;
  245. u32 *buf;
  246. if (blksize % sizeof(u32))
  247. return -EINVAL;
  248. buf = is_read ? (u32 *)data->dest : (u32 *)data->src;
  249. if (is_read)
  250. data->dest += blksize;
  251. else
  252. data->src += blksize;
  253. copy_words = blksize / sizeof(u32);
  254. /*
  255. * Copy all contents from/to the FIFO as far as it reaches,
  256. * then wait for it to fill/empty again and rewind.
  257. */
  258. while (copy_words) {
  259. int burst_words, words;
  260. u32 edm;
  261. burst_words = min(SDDATA_FIFO_PIO_BURST, copy_words);
  262. edm = readl(host->ioaddr + SDEDM);
  263. if (is_read)
  264. words = edm_fifo_fill(edm);
  265. else
  266. words = SDDATA_FIFO_WORDS - edm_fifo_fill(edm);
  267. if (words < burst_words) {
  268. int fsm_state = (edm & SDEDM_FSM_MASK);
  269. if ((is_read &&
  270. (fsm_state != SDEDM_FSM_READDATA &&
  271. fsm_state != SDEDM_FSM_READWAIT &&
  272. fsm_state != SDEDM_FSM_READCRC)) ||
  273. (!is_read &&
  274. (fsm_state != SDEDM_FSM_WRITEDATA &&
  275. fsm_state != SDEDM_FSM_WRITEWAIT1 &&
  276. fsm_state != SDEDM_FSM_WRITEWAIT2 &&
  277. fsm_state != SDEDM_FSM_WRITECRC &&
  278. fsm_state != SDEDM_FSM_WRITESTART1 &&
  279. fsm_state != SDEDM_FSM_WRITESTART2))) {
  280. hsts = readl(host->ioaddr + SDHSTS);
  281. printf("fsm %x, hsts %08x\n", fsm_state, hsts);
  282. if (hsts & SDHSTS_ERROR_MASK)
  283. break;
  284. }
  285. continue;
  286. } else if (words > copy_words) {
  287. words = copy_words;
  288. }
  289. copy_words -= words;
  290. /* Copy current chunk to/from the FIFO */
  291. while (words) {
  292. if (is_read)
  293. *(buf++) = readl(host->ioaddr + SDDATA);
  294. else
  295. writel(*(buf++), host->ioaddr + SDDATA);
  296. words--;
  297. }
  298. }
  299. return 0;
  300. }
  301. static int bcm2835_transfer_pio(struct bcm2835_host *host)
  302. {
  303. u32 sdhsts;
  304. bool is_read;
  305. int ret = 0;
  306. is_read = (host->data->flags & MMC_DATA_READ) != 0;
  307. ret = bcm2835_transfer_block_pio(host, is_read);
  308. if (ret)
  309. return ret;
  310. sdhsts = readl(host->ioaddr + SDHSTS);
  311. if (sdhsts & (SDHSTS_CRC16_ERROR |
  312. SDHSTS_CRC7_ERROR |
  313. SDHSTS_FIFO_ERROR)) {
  314. printf("%s transfer error - HSTS %08x\n",
  315. is_read ? "read" : "write", sdhsts);
  316. ret = -EILSEQ;
  317. } else if ((sdhsts & (SDHSTS_CMD_TIME_OUT |
  318. SDHSTS_REW_TIME_OUT))) {
  319. printf("%s timeout error - HSTS %08x\n",
  320. is_read ? "read" : "write", sdhsts);
  321. ret = -ETIMEDOUT;
  322. }
  323. return ret;
  324. }
  325. static void bcm2835_prepare_data(struct bcm2835_host *host, struct mmc_cmd *cmd,
  326. struct mmc_data *data)
  327. {
  328. WARN_ON(host->data);
  329. host->data = data;
  330. if (!data)
  331. return;
  332. /* Use PIO */
  333. host->blocks = data->blocks;
  334. writel(data->blocksize, host->ioaddr + SDHBCT);
  335. writel(data->blocks, host->ioaddr + SDHBLC);
  336. }
  337. static u32 bcm2835_read_wait_sdcmd(struct bcm2835_host *host)
  338. {
  339. u32 value;
  340. int ret;
  341. int timeout_us = SDHST_TIMEOUT_MAX_USEC;
  342. ret = readl_poll_timeout(host->ioaddr + SDCMD, value,
  343. !(value & SDCMD_NEW_FLAG), timeout_us);
  344. if (ret == -ETIMEDOUT)
  345. printf("%s: timeout (%d us)\n", __func__, timeout_us);
  346. return value;
  347. }
  348. static int bcm2835_send_command(struct bcm2835_host *host, struct mmc_cmd *cmd,
  349. struct mmc_data *data)
  350. {
  351. u32 sdcmd, sdhsts;
  352. WARN_ON(host->cmd);
  353. if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY)) {
  354. printf("unsupported response type!\n");
  355. return -EINVAL;
  356. }
  357. sdcmd = bcm2835_read_wait_sdcmd(host);
  358. if (sdcmd & SDCMD_NEW_FLAG) {
  359. printf("previous command never completed.\n");
  360. bcm2835_dumpregs(host);
  361. return -EBUSY;
  362. }
  363. host->cmd = cmd;
  364. /* Clear any error flags */
  365. sdhsts = readl(host->ioaddr + SDHSTS);
  366. if (sdhsts & SDHSTS_ERROR_MASK)
  367. writel(sdhsts, host->ioaddr + SDHSTS);
  368. bcm2835_prepare_data(host, cmd, data);
  369. writel(cmd->cmdarg, host->ioaddr + SDARG);
  370. sdcmd = cmd->cmdidx & SDCMD_CMD_MASK;
  371. host->use_busy = false;
  372. if (!(cmd->resp_type & MMC_RSP_PRESENT)) {
  373. sdcmd |= SDCMD_NO_RESPONSE;
  374. } else {
  375. if (cmd->resp_type & MMC_RSP_136)
  376. sdcmd |= SDCMD_LONG_RESPONSE;
  377. if (cmd->resp_type & MMC_RSP_BUSY) {
  378. sdcmd |= SDCMD_BUSYWAIT;
  379. host->use_busy = true;
  380. }
  381. }
  382. if (data) {
  383. if (data->flags & MMC_DATA_WRITE)
  384. sdcmd |= SDCMD_WRITE_CMD;
  385. if (data->flags & MMC_DATA_READ)
  386. sdcmd |= SDCMD_READ_CMD;
  387. }
  388. writel(sdcmd | SDCMD_NEW_FLAG, host->ioaddr + SDCMD);
  389. return 0;
  390. }
  391. static int bcm2835_finish_command(struct bcm2835_host *host)
  392. {
  393. struct mmc_cmd *cmd = host->cmd;
  394. u32 sdcmd;
  395. int ret = 0;
  396. sdcmd = bcm2835_read_wait_sdcmd(host);
  397. /* Check for errors */
  398. if (sdcmd & SDCMD_NEW_FLAG) {
  399. printf("command never completed.\n");
  400. bcm2835_dumpregs(host);
  401. return -EIO;
  402. } else if (sdcmd & SDCMD_FAIL_FLAG) {
  403. u32 sdhsts = readl(host->ioaddr + SDHSTS);
  404. /* Clear the errors */
  405. writel(SDHSTS_ERROR_MASK, host->ioaddr + SDHSTS);
  406. if (!(sdhsts & SDHSTS_CRC7_ERROR) ||
  407. (host->cmd->cmdidx != MMC_CMD_SEND_OP_COND)) {
  408. if (sdhsts & SDHSTS_CMD_TIME_OUT) {
  409. ret = -ETIMEDOUT;
  410. } else {
  411. printf("unexpected command %d error\n",
  412. host->cmd->cmdidx);
  413. bcm2835_dumpregs(host);
  414. ret = -EILSEQ;
  415. }
  416. return ret;
  417. }
  418. }
  419. if (cmd->resp_type & MMC_RSP_PRESENT) {
  420. if (cmd->resp_type & MMC_RSP_136) {
  421. int i;
  422. for (i = 0; i < 4; i++) {
  423. cmd->response[3 - i] =
  424. readl(host->ioaddr + SDRSP0 + i * 4);
  425. }
  426. } else {
  427. cmd->response[0] = readl(host->ioaddr + SDRSP0);
  428. }
  429. }
  430. /* Processed actual command. */
  431. host->cmd = NULL;
  432. return ret;
  433. }
  434. static int bcm2835_check_cmd_error(struct bcm2835_host *host, u32 intmask)
  435. {
  436. int ret = -EINVAL;
  437. if (!(intmask & SDHSTS_ERROR_MASK))
  438. return 0;
  439. if (!host->cmd)
  440. return -EINVAL;
  441. printf("sdhost_busy_irq: intmask %08x\n", intmask);
  442. if (intmask & SDHSTS_CRC7_ERROR) {
  443. ret = -EILSEQ;
  444. } else if (intmask & (SDHSTS_CRC16_ERROR |
  445. SDHSTS_FIFO_ERROR)) {
  446. ret = -EILSEQ;
  447. } else if (intmask & (SDHSTS_REW_TIME_OUT | SDHSTS_CMD_TIME_OUT)) {
  448. ret = -ETIMEDOUT;
  449. }
  450. bcm2835_dumpregs(host);
  451. return ret;
  452. }
  453. static int bcm2835_check_data_error(struct bcm2835_host *host, u32 intmask)
  454. {
  455. int ret = 0;
  456. if (!host->data)
  457. return 0;
  458. if (intmask & (SDHSTS_CRC16_ERROR | SDHSTS_FIFO_ERROR))
  459. ret = -EILSEQ;
  460. if (intmask & SDHSTS_REW_TIME_OUT)
  461. ret = -ETIMEDOUT;
  462. if (ret)
  463. printf("%s:%d %d\n", __func__, __LINE__, ret);
  464. return ret;
  465. }
  466. static int bcm2835_transmit(struct bcm2835_host *host)
  467. {
  468. u32 intmask = readl(host->ioaddr + SDHSTS);
  469. int ret;
  470. /* Check for errors */
  471. ret = bcm2835_check_data_error(host, intmask);
  472. if (ret)
  473. return ret;
  474. ret = bcm2835_check_cmd_error(host, intmask);
  475. if (ret)
  476. return ret;
  477. /* Handle wait for busy end */
  478. if (host->use_busy && (intmask & SDHSTS_BUSY_IRPT)) {
  479. writel(SDHSTS_BUSY_IRPT, host->ioaddr + SDHSTS);
  480. host->use_busy = false;
  481. bcm2835_finish_command(host);
  482. }
  483. /* Handle PIO data transfer */
  484. if (host->data) {
  485. ret = bcm2835_transfer_pio(host);
  486. if (ret)
  487. return ret;
  488. host->blocks--;
  489. if (host->blocks == 0) {
  490. /* Wait for command to complete for real */
  491. ret = bcm2835_wait_transfer_complete(host);
  492. if (ret)
  493. return ret;
  494. /* Transfer complete */
  495. host->data = NULL;
  496. }
  497. }
  498. return 0;
  499. }
  500. static void bcm2835_set_clock(struct bcm2835_host *host, unsigned int clock)
  501. {
  502. int div;
  503. /* The SDCDIV register has 11 bits, and holds (div - 2). But
  504. * in data mode the max is 50MHz wihout a minimum, and only
  505. * the bottom 3 bits are used. Since the switch over is
  506. * automatic (unless we have marked the card as slow...),
  507. * chosen values have to make sense in both modes. Ident mode
  508. * must be 100-400KHz, so can range check the requested
  509. * clock. CMD15 must be used to return to data mode, so this
  510. * can be monitored.
  511. *
  512. * clock 250MHz -> 0->125MHz, 1->83.3MHz, 2->62.5MHz, 3->50.0MHz
  513. * 4->41.7MHz, 5->35.7MHz, 6->31.3MHz, 7->27.8MHz
  514. *
  515. * 623->400KHz/27.8MHz
  516. * reset value (507)->491159/50MHz
  517. *
  518. * BUT, the 3-bit clock divisor in data mode is too small if
  519. * the core clock is higher than 250MHz, so instead use the
  520. * SLOW_CARD configuration bit to force the use of the ident
  521. * clock divisor at all times.
  522. */
  523. if (clock < 100000) {
  524. /* Can't stop the clock, but make it as slow as possible
  525. * to show willing
  526. */
  527. host->cdiv = SDCDIV_MAX_CDIV;
  528. writel(host->cdiv, host->ioaddr + SDCDIV);
  529. return;
  530. }
  531. div = host->max_clk / clock;
  532. if (div < 2)
  533. div = 2;
  534. if ((host->max_clk / div) > clock)
  535. div++;
  536. div -= 2;
  537. if (div > SDCDIV_MAX_CDIV)
  538. div = SDCDIV_MAX_CDIV;
  539. clock = host->max_clk / (div + 2);
  540. host->mmc->clock = clock;
  541. /* Calibrate some delays */
  542. host->ns_per_fifo_word = (1000000000 / clock) *
  543. ((host->mmc->card_caps & MMC_MODE_4BIT) ? 8 : 32);
  544. host->cdiv = div;
  545. writel(host->cdiv, host->ioaddr + SDCDIV);
  546. /* Set the timeout to 500ms */
  547. writel(host->mmc->clock / 2, host->ioaddr + SDTOUT);
  548. }
  549. static inline int is_power_of_2(u64 x)
  550. {
  551. return !(x & (x - 1));
  552. }
  553. static int bcm2835_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  554. struct mmc_data *data)
  555. {
  556. struct bcm2835_host *host = dev_get_priv(dev);
  557. u32 edm, fsm;
  558. int ret = 0;
  559. if (data && !is_power_of_2(data->blocksize)) {
  560. printf("unsupported block size (%d bytes)\n", data->blocksize);
  561. if (cmd)
  562. return -EINVAL;
  563. }
  564. edm = readl(host->ioaddr + SDEDM);
  565. fsm = edm & SDEDM_FSM_MASK;
  566. if ((fsm != SDEDM_FSM_IDENTMODE) &&
  567. (fsm != SDEDM_FSM_DATAMODE) &&
  568. (cmd && cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) {
  569. printf("previous command (%d) not complete (EDM %08x)\n",
  570. readl(host->ioaddr + SDCMD) & SDCMD_CMD_MASK, edm);
  571. bcm2835_dumpregs(host);
  572. if (cmd)
  573. return -EILSEQ;
  574. return 0;
  575. }
  576. if (cmd) {
  577. ret = bcm2835_send_command(host, cmd, data);
  578. if (!ret && !host->use_busy)
  579. ret = bcm2835_finish_command(host);
  580. }
  581. /* Wait for completion of busy signal or data transfer */
  582. while (host->use_busy || host->data) {
  583. ret = bcm2835_transmit(host);
  584. if (ret)
  585. break;
  586. }
  587. return ret;
  588. }
  589. static int bcm2835_set_ios(struct udevice *dev)
  590. {
  591. struct bcm2835_host *host = dev_get_priv(dev);
  592. struct mmc *mmc = mmc_get_mmc_dev(dev);
  593. if (!mmc->clock || mmc->clock != host->clock) {
  594. bcm2835_set_clock(host, mmc->clock);
  595. host->clock = mmc->clock;
  596. }
  597. /* set bus width */
  598. host->hcfg &= ~SDHCFG_WIDE_EXT_BUS;
  599. if (mmc->bus_width == 4)
  600. host->hcfg |= SDHCFG_WIDE_EXT_BUS;
  601. host->hcfg |= SDHCFG_WIDE_INT_BUS;
  602. /* Disable clever clock switching, to cope with fast core clocks */
  603. host->hcfg |= SDHCFG_SLOW_CARD;
  604. writel(host->hcfg, host->ioaddr + SDHCFG);
  605. return 0;
  606. }
  607. static void bcm2835_add_host(struct bcm2835_host *host)
  608. {
  609. struct mmc_config *cfg = &host->plat->cfg;
  610. cfg->f_max = host->max_clk;
  611. cfg->f_min = host->max_clk / SDCDIV_MAX_CDIV;
  612. cfg->b_max = 65535;
  613. dev_dbg(dev, "f_max %d, f_min %d\n",
  614. cfg->f_max, cfg->f_min);
  615. /* host controller capabilities */
  616. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_HS | MMC_MODE_HS_52MHz;
  617. /* report supported voltage ranges */
  618. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  619. /* Set interrupt enables */
  620. host->hcfg = SDHCFG_BUSY_IRPT_EN;
  621. bcm2835_reset_internal(host);
  622. }
  623. static int bcm2835_probe(struct udevice *dev)
  624. {
  625. struct bcm2835_plat *plat = dev_get_platdata(dev);
  626. struct bcm2835_host *host = dev_get_priv(dev);
  627. struct mmc *mmc = mmc_get_mmc_dev(dev);
  628. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  629. host->dev = dev;
  630. host->mmc = mmc;
  631. host->plat = plat;
  632. upriv->mmc = &plat->mmc;
  633. plat->cfg.name = dev->name;
  634. host->phys_addr = dev_read_addr(dev);
  635. if (host->phys_addr == FDT_ADDR_T_NONE)
  636. return -EINVAL;
  637. host->ioaddr = devm_ioremap(dev, host->phys_addr, SZ_256);
  638. if (!host->ioaddr)
  639. return -ENOMEM;
  640. host->max_clk = bcm2835_get_mmc_clock(BCM2835_MBOX_CLOCK_ID_CORE);
  641. bcm2835_add_host(host);
  642. dev_dbg(dev, "%s -> OK\n", __func__);
  643. return 0;
  644. }
  645. static const struct udevice_id bcm2835_match[] = {
  646. { .compatible = "brcm,bcm2835-sdhost" },
  647. { }
  648. };
  649. static const struct dm_mmc_ops bcm2835_ops = {
  650. .send_cmd = bcm2835_send_cmd,
  651. .set_ios = bcm2835_set_ios,
  652. };
  653. static int bcm2835_bind(struct udevice *dev)
  654. {
  655. struct bcm2835_plat *plat = dev_get_platdata(dev);
  656. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  657. }
  658. U_BOOT_DRIVER(bcm2835_sdhost) = {
  659. .name = "bcm2835-sdhost",
  660. .id = UCLASS_MMC,
  661. .of_match = bcm2835_match,
  662. .bind = bcm2835_bind,
  663. .probe = bcm2835_probe,
  664. .priv_auto_alloc_size = sizeof(struct bcm2835_host),
  665. .platdata_auto_alloc_size = sizeof(struct bcm2835_plat),
  666. .ops = &bcm2835_ops,
  667. };