omap24xx_i2c.c 30 KB

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  1. /*
  2. * Basic I2C functions
  3. *
  4. * Copyright (c) 2004 Texas Instruments
  5. *
  6. * This package is free software; you can redistribute it and/or
  7. * modify it under the terms of the license found in the file
  8. * named COPYING that should have accompanied this file.
  9. *
  10. * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
  11. * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
  12. * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
  13. *
  14. * Author: Jian Zhang jzhang@ti.com, Texas Instruments
  15. *
  16. * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
  17. * Rewritten to fit into the current U-Boot framework
  18. *
  19. * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
  20. *
  21. * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
  22. * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
  23. * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
  24. * OMAPs and derivatives as well. The only anticipated exception would
  25. * be the OMAP2420, which shall require driver modification.
  26. * - Rewritten i2c_read to operate correctly with all types of chips
  27. * (old function could not read consistent data from some I2C slaves).
  28. * - Optimized i2c_write.
  29. * - New i2c_probe, performs write access vs read. The old probe could
  30. * hang the system under certain conditions (e.g. unconfigured pads).
  31. * - The read/write/probe functions try to identify unconfigured bus.
  32. * - Status functions now read irqstatus_raw as per TRM guidelines
  33. * (except for OMAP243X and OMAP34XX).
  34. * - Driver now supports up to I2C5 (OMAP5).
  35. *
  36. * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
  37. * - Added support for set_speed
  38. *
  39. */
  40. #include <common.h>
  41. #include <dm.h>
  42. #include <i2c.h>
  43. #include <log.h>
  44. #include <linux/delay.h>
  45. #include <asm/io.h>
  46. #include <asm/omap_i2c.h>
  47. /*
  48. * Provide access to architecture-specific I2C header files for platforms
  49. * that are NOT yet solely relying on CONFIG_DM_I2C, CONFIG_OF_CONTROL, and
  50. * the defaults provided in 'omap24xx_i2c.h' for all U-Boot stages where I2C
  51. * access is desired.
  52. */
  53. #ifndef CONFIG_ARCH_K3
  54. #include <asm/arch/i2c.h>
  55. #endif
  56. #include "omap24xx_i2c.h"
  57. #define I2C_TIMEOUT 1000
  58. /* Absolutely safe for status update at 100 kHz I2C: */
  59. #define I2C_WAIT 200
  60. enum {
  61. OMAP_I2C_REV_REG = 0, /* Only on IP V1 (OMAP34XX) */
  62. OMAP_I2C_IE_REG, /* Only on IP V1 (OMAP34XX) */
  63. OMAP_I2C_STAT_REG,
  64. OMAP_I2C_WE_REG,
  65. OMAP_I2C_SYSS_REG,
  66. OMAP_I2C_BUF_REG,
  67. OMAP_I2C_CNT_REG,
  68. OMAP_I2C_DATA_REG,
  69. OMAP_I2C_SYSC_REG,
  70. OMAP_I2C_CON_REG,
  71. OMAP_I2C_OA_REG,
  72. OMAP_I2C_SA_REG,
  73. OMAP_I2C_PSC_REG,
  74. OMAP_I2C_SCLL_REG,
  75. OMAP_I2C_SCLH_REG,
  76. OMAP_I2C_SYSTEST_REG,
  77. OMAP_I2C_BUFSTAT_REG,
  78. /* Only on IP V2 (OMAP4430, etc.) */
  79. OMAP_I2C_IP_V2_REVNB_LO,
  80. OMAP_I2C_IP_V2_REVNB_HI,
  81. OMAP_I2C_IP_V2_IRQSTATUS_RAW,
  82. OMAP_I2C_IP_V2_IRQENABLE_SET,
  83. OMAP_I2C_IP_V2_IRQENABLE_CLR,
  84. };
  85. static const u8 __maybe_unused reg_map_ip_v1[] = {
  86. [OMAP_I2C_REV_REG] = 0x00,
  87. [OMAP_I2C_IE_REG] = 0x04,
  88. [OMAP_I2C_STAT_REG] = 0x08,
  89. [OMAP_I2C_WE_REG] = 0x0c,
  90. [OMAP_I2C_SYSS_REG] = 0x10,
  91. [OMAP_I2C_BUF_REG] = 0x14,
  92. [OMAP_I2C_CNT_REG] = 0x18,
  93. [OMAP_I2C_DATA_REG] = 0x1c,
  94. [OMAP_I2C_SYSC_REG] = 0x20,
  95. [OMAP_I2C_CON_REG] = 0x24,
  96. [OMAP_I2C_OA_REG] = 0x28,
  97. [OMAP_I2C_SA_REG] = 0x2c,
  98. [OMAP_I2C_PSC_REG] = 0x30,
  99. [OMAP_I2C_SCLL_REG] = 0x34,
  100. [OMAP_I2C_SCLH_REG] = 0x38,
  101. [OMAP_I2C_SYSTEST_REG] = 0x3c,
  102. [OMAP_I2C_BUFSTAT_REG] = 0x40,
  103. };
  104. static const u8 __maybe_unused reg_map_ip_v2[] = {
  105. [OMAP_I2C_STAT_REG] = 0x28,
  106. [OMAP_I2C_WE_REG] = 0x34,
  107. [OMAP_I2C_SYSS_REG] = 0x90,
  108. [OMAP_I2C_BUF_REG] = 0x94,
  109. [OMAP_I2C_CNT_REG] = 0x98,
  110. [OMAP_I2C_DATA_REG] = 0x9c,
  111. [OMAP_I2C_SYSC_REG] = 0x10,
  112. [OMAP_I2C_CON_REG] = 0xa4,
  113. [OMAP_I2C_OA_REG] = 0xa8,
  114. [OMAP_I2C_SA_REG] = 0xac,
  115. [OMAP_I2C_PSC_REG] = 0xb0,
  116. [OMAP_I2C_SCLL_REG] = 0xb4,
  117. [OMAP_I2C_SCLH_REG] = 0xb8,
  118. [OMAP_I2C_SYSTEST_REG] = 0xbc,
  119. [OMAP_I2C_BUFSTAT_REG] = 0xc0,
  120. [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
  121. [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
  122. [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
  123. [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
  124. [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
  125. };
  126. struct omap_i2c {
  127. struct udevice *clk;
  128. int ip_rev;
  129. struct i2c *regs;
  130. unsigned int speed;
  131. int waitdelay;
  132. int clk_id;
  133. };
  134. static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev)
  135. {
  136. switch (ip_rev) {
  137. case OMAP_I2C_REV_V1:
  138. return reg_map_ip_v1;
  139. case OMAP_I2C_REV_V2:
  140. /* Fall through... */
  141. default:
  142. return reg_map_ip_v2;
  143. }
  144. }
  145. static inline void omap_i2c_write_reg(void __iomem *base, int ip_rev,
  146. u16 val, int reg)
  147. {
  148. writew(val, base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
  149. }
  150. static inline u16 omap_i2c_read_reg(void __iomem *base, int ip_rev, int reg)
  151. {
  152. return readw(base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
  153. }
  154. static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
  155. {
  156. unsigned long internal_clk = 0, fclk;
  157. unsigned int prescaler;
  158. /*
  159. * This method is only called for Standard and Fast Mode speeds
  160. *
  161. * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
  162. * page 5685, Table 24-7)
  163. * that the internal I2C clock (after prescaler) should be between
  164. * 7-12 MHz (at least for Fast Mode (FS)).
  165. *
  166. * Such approach is used in v4.9 Linux kernel in:
  167. * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
  168. */
  169. speed /= 1000; /* convert speed to kHz */
  170. if (speed > 100)
  171. internal_clk = 9600;
  172. else
  173. internal_clk = 4000;
  174. fclk = I2C_IP_CLK / 1000;
  175. prescaler = fclk / internal_clk;
  176. prescaler = prescaler - 1;
  177. if (speed > 100) {
  178. unsigned long scl;
  179. /* Fast mode */
  180. scl = internal_clk / speed;
  181. *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
  182. *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
  183. } else {
  184. /* Standard mode */
  185. *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
  186. *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
  187. }
  188. debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
  189. __func__, speed, prescaler, *pscl, *psch);
  190. if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
  191. return -EINVAL;
  192. return prescaler;
  193. }
  194. /*
  195. * Wait for the bus to be free by checking the Bus Busy (BB)
  196. * bit to become clear
  197. */
  198. static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay)
  199. {
  200. int timeout = I2C_TIMEOUT;
  201. int irq_stat_reg;
  202. u16 stat;
  203. irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
  204. OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
  205. /* clear current interrupts */
  206. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  207. while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) &
  208. I2C_STAT_BB) && timeout--) {
  209. omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG);
  210. udelay(waitdelay);
  211. }
  212. if (timeout <= 0) {
  213. printf("Timed out in %s: status=%04x\n", __func__, stat);
  214. return 1;
  215. }
  216. /* clear delayed stuff */
  217. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  218. return 0;
  219. }
  220. /*
  221. * Wait for the I2C controller to complete current action
  222. * and update status
  223. */
  224. static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay)
  225. {
  226. u16 status;
  227. int timeout = I2C_TIMEOUT;
  228. int irq_stat_reg;
  229. irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
  230. OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
  231. do {
  232. udelay(waitdelay);
  233. status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg);
  234. } while (!(status &
  235. (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
  236. I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
  237. I2C_STAT_AL)) && timeout--);
  238. if (timeout <= 0) {
  239. printf("Timed out in %s: status=%04x\n", __func__, status);
  240. /*
  241. * If status is still 0 here, probably the bus pads have
  242. * not been configured for I2C, and/or pull-ups are missing.
  243. */
  244. printf("Check if pads/pull-ups of bus are properly configured\n");
  245. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  246. status = 0;
  247. }
  248. return status;
  249. }
  250. static void flush_fifo(void __iomem *i2c_base, int ip_rev)
  251. {
  252. u16 stat;
  253. /*
  254. * note: if you try and read data when its not there or ready
  255. * you get a bus error
  256. */
  257. while (1) {
  258. stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG);
  259. if (stat == I2C_STAT_RRDY) {
  260. omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_DATA_REG);
  261. omap_i2c_write_reg(i2c_base, ip_rev,
  262. I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
  263. udelay(1000);
  264. } else
  265. break;
  266. }
  267. }
  268. static int __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed,
  269. int *waitdelay)
  270. {
  271. int psc, fsscll = 0, fssclh = 0;
  272. int hsscll = 0, hssclh = 0;
  273. u32 scll = 0, sclh = 0;
  274. if (speed >= I2C_SPEED_HIGH_RATE) {
  275. /* High speed */
  276. psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
  277. psc -= 1;
  278. if (psc < I2C_PSC_MIN) {
  279. printf("Error : I2C unsupported prescaler %d\n", psc);
  280. return -1;
  281. }
  282. /* For first phase of HS mode */
  283. fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  284. fssclh = fsscll;
  285. fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
  286. fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
  287. if (((fsscll < 0) || (fssclh < 0)) ||
  288. ((fsscll > 255) || (fssclh > 255))) {
  289. puts("Error : I2C initializing first phase clock\n");
  290. return -1;
  291. }
  292. /* For second phase of HS mode */
  293. hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
  294. hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
  295. hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
  296. if (((fsscll < 0) || (fssclh < 0)) ||
  297. ((fsscll > 255) || (fssclh > 255))) {
  298. puts("Error : I2C initializing second phase clock\n");
  299. return -1;
  300. }
  301. scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
  302. sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
  303. } else {
  304. /* Standard and fast speed */
  305. psc = omap24_i2c_findpsc(&scll, &sclh, speed);
  306. if (0 > psc) {
  307. puts("Error : I2C initializing clock\n");
  308. return -1;
  309. }
  310. }
  311. /* wait for 20 clkperiods */
  312. *waitdelay = (10000000 / speed) * 2;
  313. omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
  314. omap_i2c_write_reg(i2c_base, ip_rev, psc, OMAP_I2C_PSC_REG);
  315. omap_i2c_write_reg(i2c_base, ip_rev, scll, OMAP_I2C_SCLL_REG);
  316. omap_i2c_write_reg(i2c_base, ip_rev, sclh, OMAP_I2C_SCLH_REG);
  317. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
  318. /* clear all pending status */
  319. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  320. return 0;
  321. }
  322. static void omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev)
  323. {
  324. int i;
  325. u16 systest;
  326. u16 orgsystest;
  327. /* set test mode ST_EN = 1 */
  328. orgsystest = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSTEST_REG);
  329. systest = orgsystest;
  330. /* enable testmode */
  331. systest |= I2C_SYSTEST_ST_EN;
  332. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  333. systest &= ~I2C_SYSTEST_TMODE_MASK;
  334. systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
  335. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  336. /* set SCL, SDA = 1 */
  337. systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
  338. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  339. udelay(10);
  340. /* toggle scl 9 clocks */
  341. for (i = 0; i < 9; i++) {
  342. /* SCL = 0 */
  343. systest &= ~I2C_SYSTEST_SCL_O;
  344. omap_i2c_write_reg(i2c_base, ip_rev,
  345. systest, OMAP_I2C_SYSTEST_REG);
  346. udelay(10);
  347. /* SCL = 1 */
  348. systest |= I2C_SYSTEST_SCL_O;
  349. omap_i2c_write_reg(i2c_base, ip_rev,
  350. systest, OMAP_I2C_SYSTEST_REG);
  351. udelay(10);
  352. }
  353. /* send stop */
  354. systest &= ~I2C_SYSTEST_SDA_O;
  355. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  356. udelay(10);
  357. systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
  358. omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
  359. udelay(10);
  360. /* restore original mode */
  361. omap_i2c_write_reg(i2c_base, ip_rev, orgsystest, OMAP_I2C_SYSTEST_REG);
  362. }
  363. static void __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed,
  364. int slaveadd, int *waitdelay)
  365. {
  366. int timeout = I2C_TIMEOUT;
  367. int deblock = 1;
  368. retry:
  369. if (omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_CON_REG) &
  370. I2C_CON_EN) {
  371. omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
  372. udelay(50000);
  373. }
  374. /* for ES2 after soft reset */
  375. omap_i2c_write_reg(i2c_base, ip_rev, 0x2, OMAP_I2C_SYSC_REG);
  376. udelay(1000);
  377. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
  378. while (!(omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSS_REG) &
  379. I2C_SYSS_RDONE) && timeout--) {
  380. if (timeout <= 0) {
  381. puts("ERROR: Timeout in soft-reset\n");
  382. return;
  383. }
  384. udelay(1000);
  385. }
  386. if (__omap24_i2c_setspeed(i2c_base, ip_rev, speed, waitdelay)) {
  387. printf("ERROR: failed to setup I2C bus-speed!\n");
  388. return;
  389. }
  390. /* own address */
  391. omap_i2c_write_reg(i2c_base, ip_rev, slaveadd, OMAP_I2C_OA_REG);
  392. if (ip_rev == OMAP_I2C_REV_V1) {
  393. /*
  394. * Have to enable interrupts for OMAP2/3, these IPs don't have
  395. * an 'irqstatus_raw' register and we shall have to poll 'stat'
  396. */
  397. omap_i2c_write_reg(i2c_base, ip_rev, I2C_IE_XRDY_IE |
  398. I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
  399. I2C_IE_NACK_IE | I2C_IE_AL_IE,
  400. OMAP_I2C_IE_REG);
  401. }
  402. udelay(1000);
  403. flush_fifo(i2c_base, ip_rev);
  404. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  405. /* Handle possible failed I2C state */
  406. if (wait_for_bb(i2c_base, ip_rev, *waitdelay))
  407. if (deblock == 1) {
  408. omap24_i2c_deblock(i2c_base, ip_rev);
  409. deblock = 0;
  410. goto retry;
  411. }
  412. }
  413. /*
  414. * i2c_probe: Use write access. Allows to identify addresses that are
  415. * write-only (like the config register of dual-port EEPROMs)
  416. */
  417. static int __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay,
  418. uchar chip)
  419. {
  420. u16 status;
  421. int res = 1; /* default = fail */
  422. if (chip == omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_OA_REG))
  423. return res;
  424. /* Wait until bus is free */
  425. if (wait_for_bb(i2c_base, ip_rev, waitdelay))
  426. return res;
  427. /* No data transfer, slave addr only */
  428. omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
  429. /* Stop bit needed here */
  430. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  431. I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
  432. OMAP_I2C_CON_REG);
  433. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  434. if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
  435. /*
  436. * With current high-level command implementation, notifying
  437. * the user shall flood the console with 127 messages. If
  438. * silent exit is desired upon unconfigured bus, remove the
  439. * following 'if' section:
  440. */
  441. if (status == I2C_STAT_XRDY)
  442. printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
  443. status);
  444. goto pr_exit;
  445. }
  446. /* Check for ACK (!NAK) */
  447. if (!(status & I2C_STAT_NACK)) {
  448. res = 0; /* Device found */
  449. udelay(waitdelay);/* Required by AM335X in SPL */
  450. /* Abort transfer (force idle state) */
  451. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_MST | I2C_CON_TRX,
  452. OMAP_I2C_CON_REG); /* Reset */
  453. udelay(1000);
  454. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  455. I2C_CON_TRX | I2C_CON_STP,
  456. OMAP_I2C_CON_REG); /* STP */
  457. }
  458. pr_exit:
  459. flush_fifo(i2c_base, ip_rev);
  460. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  461. return res;
  462. }
  463. /*
  464. * i2c_read: Function now uses a single I2C read transaction with bulk transfer
  465. * of the requested number of bytes (note that the 'i2c md' command
  466. * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
  467. * defined in the board config header, this transaction shall be with
  468. * Repeated Start (Sr) between the address and data phases; otherwise
  469. * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
  470. * The address (reg offset) may be 0, 1 or 2 bytes long.
  471. * Function now reads correctly from chips that return more than one
  472. * byte of data per addressed register (like TI temperature sensors),
  473. * or that do not need a register address at all (such as some clock
  474. * distributors).
  475. */
  476. static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay,
  477. uchar chip, uint addr, int alen, uchar *buffer,
  478. int len)
  479. {
  480. int i2c_error = 0;
  481. u16 status;
  482. if (alen < 0) {
  483. puts("I2C read: addr len < 0\n");
  484. return 1;
  485. }
  486. if (len < 0) {
  487. puts("I2C read: data len < 0\n");
  488. return 1;
  489. }
  490. if (buffer == NULL) {
  491. puts("I2C read: NULL pointer passed\n");
  492. return 1;
  493. }
  494. if (alen > 2) {
  495. printf("I2C read: addr len %d not supported\n", alen);
  496. return 1;
  497. }
  498. if (addr + len > (1 << 16)) {
  499. puts("I2C read: address out of range\n");
  500. return 1;
  501. }
  502. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  503. /*
  504. * EEPROM chips that implement "address overflow" are ones
  505. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  506. * address and the extra bits end up in the "chip address"
  507. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  508. * four 256 byte chips.
  509. *
  510. * Note that we consider the length of the address field to
  511. * still be one byte because the extra address bits are
  512. * hidden in the chip address.
  513. */
  514. if (alen > 0)
  515. chip |= ((addr >> (alen * 8)) &
  516. CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  517. #endif
  518. /* Wait until bus not busy */
  519. if (wait_for_bb(i2c_base, ip_rev, waitdelay))
  520. return 1;
  521. /* Zero, one or two bytes reg address (offset) */
  522. omap_i2c_write_reg(i2c_base, ip_rev, alen, OMAP_I2C_CNT_REG);
  523. /* Set slave address */
  524. omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
  525. if (alen) {
  526. /* Must write reg offset first */
  527. #ifdef CONFIG_I2C_REPEATED_START
  528. /* No stop bit, use Repeated Start (Sr) */
  529. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  530. I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG);
  531. #else
  532. /* Stop - Start (P-S) */
  533. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  534. I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX,
  535. OMAP_I2C_CON_REG);
  536. #endif
  537. /* Send register offset */
  538. while (1) {
  539. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  540. /* Try to identify bus that is not padconf'd for I2C */
  541. if (status == I2C_STAT_XRDY) {
  542. i2c_error = 2;
  543. printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
  544. status);
  545. goto rd_exit;
  546. }
  547. if (status == 0 || (status & I2C_STAT_NACK)) {
  548. i2c_error = 1;
  549. printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
  550. status);
  551. goto rd_exit;
  552. }
  553. if (alen) {
  554. if (status & I2C_STAT_XRDY) {
  555. u8 addr_byte;
  556. alen--;
  557. addr_byte = (addr >> (8 * alen)) & 0xff;
  558. omap_i2c_write_reg(i2c_base, ip_rev,
  559. addr_byte,
  560. OMAP_I2C_DATA_REG);
  561. omap_i2c_write_reg(i2c_base, ip_rev,
  562. I2C_STAT_XRDY,
  563. OMAP_I2C_STAT_REG);
  564. }
  565. }
  566. if (status & I2C_STAT_ARDY) {
  567. omap_i2c_write_reg(i2c_base, ip_rev,
  568. I2C_STAT_ARDY,
  569. OMAP_I2C_STAT_REG);
  570. break;
  571. }
  572. }
  573. }
  574. /* Set slave address */
  575. omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
  576. /* Read len bytes from slave */
  577. omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG);
  578. /* Need stop bit here */
  579. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  580. I2C_CON_STT | I2C_CON_STP, OMAP_I2C_CON_REG);
  581. /* Receive data */
  582. while (1) {
  583. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  584. /*
  585. * Try to identify bus that is not padconf'd for I2C. This
  586. * state could be left over from previous transactions if
  587. * the address phase is skipped due to alen=0.
  588. */
  589. if (status == I2C_STAT_XRDY) {
  590. i2c_error = 2;
  591. printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
  592. status);
  593. goto rd_exit;
  594. }
  595. if (status == 0 || (status & I2C_STAT_NACK)) {
  596. i2c_error = 1;
  597. goto rd_exit;
  598. }
  599. if (status & I2C_STAT_RRDY) {
  600. *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev,
  601. OMAP_I2C_DATA_REG);
  602. omap_i2c_write_reg(i2c_base, ip_rev,
  603. I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
  604. }
  605. if (status & I2C_STAT_ARDY) {
  606. omap_i2c_write_reg(i2c_base, ip_rev,
  607. I2C_STAT_ARDY, OMAP_I2C_STAT_REG);
  608. break;
  609. }
  610. }
  611. rd_exit:
  612. flush_fifo(i2c_base, ip_rev);
  613. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  614. return i2c_error;
  615. }
  616. /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
  617. static int __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay,
  618. uchar chip, uint addr, int alen, uchar *buffer,
  619. int len)
  620. {
  621. int i;
  622. u16 status;
  623. int i2c_error = 0;
  624. int timeout = I2C_TIMEOUT;
  625. if (alen < 0) {
  626. puts("I2C write: addr len < 0\n");
  627. return 1;
  628. }
  629. if (len < 0) {
  630. puts("I2C write: data len < 0\n");
  631. return 1;
  632. }
  633. if (buffer == NULL) {
  634. puts("I2C write: NULL pointer passed\n");
  635. return 1;
  636. }
  637. if (alen > 2) {
  638. printf("I2C write: addr len %d not supported\n", alen);
  639. return 1;
  640. }
  641. if (addr + len > (1 << 16)) {
  642. printf("I2C write: address 0x%x + 0x%x out of range\n",
  643. addr, len);
  644. return 1;
  645. }
  646. #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
  647. /*
  648. * EEPROM chips that implement "address overflow" are ones
  649. * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  650. * address and the extra bits end up in the "chip address"
  651. * bit slots. This makes a 24WC08 (1Kbyte) chip look like
  652. * four 256 byte chips.
  653. *
  654. * Note that we consider the length of the address field to
  655. * still be one byte because the extra address bits are
  656. * hidden in the chip address.
  657. */
  658. if (alen > 0)
  659. chip |= ((addr >> (alen * 8)) &
  660. CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
  661. #endif
  662. /* Wait until bus not busy */
  663. if (wait_for_bb(i2c_base, ip_rev, waitdelay))
  664. return 1;
  665. /* Start address phase - will write regoffset + len bytes data */
  666. omap_i2c_write_reg(i2c_base, ip_rev, alen + len, OMAP_I2C_CNT_REG);
  667. /* Set slave address */
  668. omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
  669. /* Stop bit needed here */
  670. omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
  671. I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
  672. OMAP_I2C_CON_REG);
  673. while (alen) {
  674. /* Must write reg offset (one or two bytes) */
  675. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  676. /* Try to identify bus that is not padconf'd for I2C */
  677. if (status == I2C_STAT_XRDY) {
  678. i2c_error = 2;
  679. printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
  680. status);
  681. goto wr_exit;
  682. }
  683. if (status == 0 || (status & I2C_STAT_NACK)) {
  684. i2c_error = 1;
  685. printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
  686. status);
  687. goto wr_exit;
  688. }
  689. if (status & I2C_STAT_XRDY) {
  690. alen--;
  691. omap_i2c_write_reg(i2c_base, ip_rev,
  692. (addr >> (8 * alen)) & 0xff,
  693. OMAP_I2C_DATA_REG);
  694. omap_i2c_write_reg(i2c_base, ip_rev,
  695. I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
  696. } else {
  697. i2c_error = 1;
  698. printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
  699. status);
  700. goto wr_exit;
  701. }
  702. }
  703. /* Address phase is over, now write data */
  704. for (i = 0; i < len; i++) {
  705. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  706. if (status == 0 || (status & I2C_STAT_NACK)) {
  707. i2c_error = 1;
  708. printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
  709. status);
  710. goto wr_exit;
  711. }
  712. if (status & I2C_STAT_XRDY) {
  713. omap_i2c_write_reg(i2c_base, ip_rev,
  714. buffer[i], OMAP_I2C_DATA_REG);
  715. omap_i2c_write_reg(i2c_base, ip_rev,
  716. I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
  717. } else {
  718. i2c_error = 1;
  719. printf("i2c_write: bus not ready for data Tx (i=%d)\n",
  720. i);
  721. goto wr_exit;
  722. }
  723. }
  724. /*
  725. * poll ARDY bit for making sure that last byte really has been
  726. * transferred on the bus.
  727. */
  728. do {
  729. status = wait_for_event(i2c_base, ip_rev, waitdelay);
  730. } while (!(status & I2C_STAT_ARDY) && timeout--);
  731. if (timeout <= 0)
  732. printf("i2c_write: timed out writig last byte!\n");
  733. wr_exit:
  734. flush_fifo(i2c_base, ip_rev);
  735. omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
  736. return i2c_error;
  737. }
  738. #ifndef CONFIG_DM_I2C
  739. /*
  740. * The legacy I2C functions. These need to get removed once
  741. * all users of this driver are converted to DM.
  742. */
  743. static void __iomem *omap24_get_base(struct i2c_adapter *adap)
  744. {
  745. switch (adap->hwadapnr) {
  746. case 0:
  747. return (void __iomem *)I2C_BASE1;
  748. break;
  749. case 1:
  750. return (void __iomem *)I2C_BASE2;
  751. break;
  752. #if (CONFIG_SYS_I2C_BUS_MAX > 2)
  753. case 2:
  754. return (void __iomem *)I2C_BASE3;
  755. break;
  756. #if (CONFIG_SYS_I2C_BUS_MAX > 3)
  757. case 3:
  758. return (void __iomem *)I2C_BASE4;
  759. break;
  760. #if (CONFIG_SYS_I2C_BUS_MAX > 4)
  761. case 4:
  762. return (void __iomem *)I2C_BASE5;
  763. break;
  764. #endif
  765. #endif
  766. #endif
  767. default:
  768. printf("wrong hwadapnr: %d\n", adap->hwadapnr);
  769. break;
  770. }
  771. return NULL;
  772. }
  773. static int omap24_get_ip_rev(void)
  774. {
  775. #ifdef CONFIG_OMAP34XX
  776. return OMAP_I2C_REV_V1;
  777. #else
  778. return OMAP_I2C_REV_V2;
  779. #endif
  780. }
  781. static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
  782. int alen, uchar *buffer, int len)
  783. {
  784. void __iomem *i2c_base = omap24_get_base(adap);
  785. int ip_rev = omap24_get_ip_rev();
  786. return __omap24_i2c_read(i2c_base, ip_rev, adap->waitdelay, chip, addr,
  787. alen, buffer, len);
  788. }
  789. static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
  790. int alen, uchar *buffer, int len)
  791. {
  792. void __iomem *i2c_base = omap24_get_base(adap);
  793. int ip_rev = omap24_get_ip_rev();
  794. return __omap24_i2c_write(i2c_base, ip_rev, adap->waitdelay, chip, addr,
  795. alen, buffer, len);
  796. }
  797. static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
  798. {
  799. void __iomem *i2c_base = omap24_get_base(adap);
  800. int ip_rev = omap24_get_ip_rev();
  801. int ret;
  802. ret = __omap24_i2c_setspeed(i2c_base, ip_rev, speed, &adap->waitdelay);
  803. if (ret) {
  804. pr_err("%s: set i2c speed failed\n", __func__);
  805. return ret;
  806. }
  807. adap->speed = speed;
  808. return 0;
  809. }
  810. static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
  811. {
  812. void __iomem *i2c_base = omap24_get_base(adap);
  813. int ip_rev = omap24_get_ip_rev();
  814. return __omap24_i2c_init(i2c_base, ip_rev, speed, slaveadd,
  815. &adap->waitdelay);
  816. }
  817. static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
  818. {
  819. void __iomem *i2c_base = omap24_get_base(adap);
  820. int ip_rev = omap24_get_ip_rev();
  821. return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip);
  822. }
  823. #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
  824. #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
  825. #endif
  826. #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
  827. #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
  828. #endif
  829. U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
  830. omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
  831. CONFIG_SYS_OMAP24_I2C_SPEED,
  832. CONFIG_SYS_OMAP24_I2C_SLAVE,
  833. 0)
  834. U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
  835. omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
  836. CONFIG_SYS_OMAP24_I2C_SPEED1,
  837. CONFIG_SYS_OMAP24_I2C_SLAVE1,
  838. 1)
  839. #if (CONFIG_SYS_I2C_BUS_MAX > 2)
  840. #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
  841. #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
  842. #endif
  843. #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
  844. #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
  845. #endif
  846. U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
  847. omap24_i2c_read, omap24_i2c_write, NULL,
  848. CONFIG_SYS_OMAP24_I2C_SPEED2,
  849. CONFIG_SYS_OMAP24_I2C_SLAVE2,
  850. 2)
  851. #if (CONFIG_SYS_I2C_BUS_MAX > 3)
  852. #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
  853. #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
  854. #endif
  855. #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
  856. #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
  857. #endif
  858. U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
  859. omap24_i2c_read, omap24_i2c_write, NULL,
  860. CONFIG_SYS_OMAP24_I2C_SPEED3,
  861. CONFIG_SYS_OMAP24_I2C_SLAVE3,
  862. 3)
  863. #if (CONFIG_SYS_I2C_BUS_MAX > 4)
  864. #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
  865. #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
  866. #endif
  867. #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
  868. #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
  869. #endif
  870. U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
  871. omap24_i2c_read, omap24_i2c_write, NULL,
  872. CONFIG_SYS_OMAP24_I2C_SPEED4,
  873. CONFIG_SYS_OMAP24_I2C_SLAVE4,
  874. 4)
  875. #endif
  876. #endif
  877. #endif
  878. #else /* CONFIG_DM_I2C */
  879. static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  880. {
  881. struct omap_i2c *priv = dev_get_priv(bus);
  882. int ret;
  883. debug("i2c_xfer: %d messages\n", nmsgs);
  884. for (; nmsgs > 0; nmsgs--, msg++) {
  885. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  886. if (msg->flags & I2C_M_RD) {
  887. ret = __omap24_i2c_read(priv->regs, priv->ip_rev,
  888. priv->waitdelay,
  889. msg->addr, 0, 0, msg->buf,
  890. msg->len);
  891. } else {
  892. ret = __omap24_i2c_write(priv->regs, priv->ip_rev,
  893. priv->waitdelay,
  894. msg->addr, 0, 0, msg->buf,
  895. msg->len);
  896. }
  897. if (ret) {
  898. debug("i2c_write: error sending\n");
  899. return -EREMOTEIO;
  900. }
  901. }
  902. return 0;
  903. }
  904. static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  905. {
  906. struct omap_i2c *priv = dev_get_priv(bus);
  907. priv->speed = speed;
  908. return __omap24_i2c_setspeed(priv->regs, priv->ip_rev, speed,
  909. &priv->waitdelay);
  910. }
  911. static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
  912. uint chip_flags)
  913. {
  914. struct omap_i2c *priv = dev_get_priv(bus);
  915. return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay,
  916. chip_addr);
  917. }
  918. static int omap_i2c_probe(struct udevice *bus)
  919. {
  920. struct omap_i2c *priv = dev_get_priv(bus);
  921. struct omap_i2c_platdata *plat = dev_get_platdata(bus);
  922. priv->speed = plat->speed;
  923. priv->regs = map_physmem(plat->base, sizeof(void *),
  924. MAP_NOCACHE);
  925. priv->ip_rev = plat->ip_rev;
  926. __omap24_i2c_init(priv->regs, priv->ip_rev, priv->speed, 0,
  927. &priv->waitdelay);
  928. return 0;
  929. }
  930. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  931. static int omap_i2c_ofdata_to_platdata(struct udevice *bus)
  932. {
  933. struct omap_i2c_platdata *plat = dev_get_platdata(bus);
  934. plat->base = dev_read_addr(bus);
  935. plat->speed = dev_read_u32_default(bus, "clock-frequency",
  936. I2C_SPEED_STANDARD_RATE);
  937. plat->ip_rev = dev_get_driver_data(bus);
  938. return 0;
  939. }
  940. static const struct udevice_id omap_i2c_ids[] = {
  941. { .compatible = "ti,omap3-i2c", .data = OMAP_I2C_REV_V1 },
  942. { .compatible = "ti,omap4-i2c", .data = OMAP_I2C_REV_V2 },
  943. { }
  944. };
  945. #endif
  946. static const struct dm_i2c_ops omap_i2c_ops = {
  947. .xfer = omap_i2c_xfer,
  948. .probe_chip = omap_i2c_probe_chip,
  949. .set_bus_speed = omap_i2c_set_bus_speed,
  950. };
  951. U_BOOT_DRIVER(i2c_omap) = {
  952. .name = "i2c_omap",
  953. .id = UCLASS_I2C,
  954. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  955. .of_match = omap_i2c_ids,
  956. .ofdata_to_platdata = omap_i2c_ofdata_to_platdata,
  957. .platdata_auto_alloc_size = sizeof(struct omap_i2c_platdata),
  958. #endif
  959. .probe = omap_i2c_probe,
  960. .priv_auto_alloc_size = sizeof(struct omap_i2c),
  961. .ops = &omap_i2c_ops,
  962. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  963. .flags = DM_FLAG_PRE_RELOC,
  964. #endif
  965. };
  966. #endif /* CONFIG_DM_I2C */