mxc_i2c.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * i2c driver for Freescale i.MX series
  4. *
  5. * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  6. * (c) 2011 Marek Vasut <marek.vasut@gmail.com>
  7. *
  8. * Based on i2c-imx.c from linux kernel:
  9. * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de>
  10. * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de>
  11. * Copyright (C) 2007 RightHand Technologies, Inc.
  12. * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  13. *
  14. */
  15. #include <common.h>
  16. #include <log.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/imx-regs.h>
  19. #include <dm/device_compat.h>
  20. #include <linux/delay.h>
  21. #include <linux/errno.h>
  22. #include <asm/mach-imx/mxc_i2c.h>
  23. #include <asm/mach-imx/sys_proto.h>
  24. #include <asm/io.h>
  25. #include <i2c.h>
  26. #include <watchdog.h>
  27. #include <dm.h>
  28. #include <dm/pinctrl.h>
  29. #include <fdtdec.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. #define I2C_QUIRK_FLAG (1 << 0)
  32. #define IMX_I2C_REGSHIFT 2
  33. #define VF610_I2C_REGSHIFT 0
  34. #define I2C_EARLY_INIT_INDEX 0
  35. #ifdef CONFIG_SYS_I2C_IFDR_DIV
  36. #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV
  37. #else
  38. #define I2C_IFDR_DIV_CONSERVATIVE 0x7e
  39. #endif
  40. /* Register index */
  41. #define IADR 0
  42. #define IFDR 1
  43. #define I2CR 2
  44. #define I2SR 3
  45. #define I2DR 4
  46. #define I2CR_IIEN (1 << 6)
  47. #define I2CR_MSTA (1 << 5)
  48. #define I2CR_MTX (1 << 4)
  49. #define I2CR_TX_NO_AK (1 << 3)
  50. #define I2CR_RSTA (1 << 2)
  51. #define I2SR_ICF (1 << 7)
  52. #define I2SR_IBB (1 << 5)
  53. #define I2SR_IAL (1 << 4)
  54. #define I2SR_IIF (1 << 1)
  55. #define I2SR_RX_NO_AK (1 << 0)
  56. #ifdef I2C_QUIRK_REG
  57. #define I2CR_IEN (0 << 7)
  58. #define I2CR_IDIS (1 << 7)
  59. #define I2SR_IIF_CLEAR (1 << 1)
  60. #else
  61. #define I2CR_IEN (1 << 7)
  62. #define I2CR_IDIS (0 << 7)
  63. #define I2SR_IIF_CLEAR (0 << 1)
  64. #endif
  65. #ifdef I2C_QUIRK_REG
  66. static u16 i2c_clk_div[60][2] = {
  67. { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 },
  68. { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 },
  69. { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D },
  70. { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 },
  71. { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 },
  72. { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 },
  73. { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 },
  74. { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 },
  75. { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 },
  76. { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B },
  77. { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 },
  78. { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 },
  79. { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B },
  80. { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A },
  81. { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E },
  82. };
  83. #else
  84. static u16 i2c_clk_div[50][2] = {
  85. { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
  86. { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
  87. { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
  88. { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
  89. { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
  90. { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
  91. { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
  92. { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
  93. { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
  94. { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
  95. { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
  96. { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
  97. { 3072, 0x1E }, { 3840, 0x1F }
  98. };
  99. #endif
  100. #ifndef CONFIG_SYS_MXC_I2C1_SPEED
  101. #define CONFIG_SYS_MXC_I2C1_SPEED 100000
  102. #endif
  103. #ifndef CONFIG_SYS_MXC_I2C2_SPEED
  104. #define CONFIG_SYS_MXC_I2C2_SPEED 100000
  105. #endif
  106. #ifndef CONFIG_SYS_MXC_I2C3_SPEED
  107. #define CONFIG_SYS_MXC_I2C3_SPEED 100000
  108. #endif
  109. #ifndef CONFIG_SYS_MXC_I2C4_SPEED
  110. #define CONFIG_SYS_MXC_I2C4_SPEED 100000
  111. #endif
  112. #ifndef CONFIG_SYS_MXC_I2C1_SLAVE
  113. #define CONFIG_SYS_MXC_I2C1_SLAVE 0
  114. #endif
  115. #ifndef CONFIG_SYS_MXC_I2C2_SLAVE
  116. #define CONFIG_SYS_MXC_I2C2_SLAVE 0
  117. #endif
  118. #ifndef CONFIG_SYS_MXC_I2C3_SLAVE
  119. #define CONFIG_SYS_MXC_I2C3_SLAVE 0
  120. #endif
  121. #ifndef CONFIG_SYS_MXC_I2C4_SLAVE
  122. #define CONFIG_SYS_MXC_I2C4_SLAVE 0
  123. #endif
  124. /*
  125. * Calculate and set proper clock divider
  126. */
  127. static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate)
  128. {
  129. unsigned int i2c_clk_rate;
  130. unsigned int div;
  131. u8 clk_div;
  132. #if defined(CONFIG_MX31)
  133. struct clock_control_regs *sc_regs =
  134. (struct clock_control_regs *)CCM_BASE;
  135. /* start the required I2C clock */
  136. writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET),
  137. &sc_regs->cgr0);
  138. #endif
  139. /* Divider value calculation */
  140. #if CONFIG_IS_ENABLED(CLK)
  141. i2c_clk_rate = clk_get_rate(&i2c_bus->per_clk);
  142. #else
  143. i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
  144. #endif
  145. div = (i2c_clk_rate + rate - 1) / rate;
  146. if (div < i2c_clk_div[0][0])
  147. clk_div = 0;
  148. else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
  149. clk_div = ARRAY_SIZE(i2c_clk_div) - 1;
  150. else
  151. for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++)
  152. ;
  153. /* Store divider value */
  154. return clk_div;
  155. }
  156. /*
  157. * Set I2C Bus speed
  158. */
  159. static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed)
  160. {
  161. ulong base = i2c_bus->base;
  162. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  163. u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed);
  164. u8 idx = i2c_clk_div[clk_idx][1];
  165. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  166. if (!base)
  167. return -EINVAL;
  168. /* Store divider value */
  169. writeb(idx, base + (IFDR << reg_shift));
  170. /* Reset module */
  171. writeb(I2CR_IDIS, base + (I2CR << reg_shift));
  172. writeb(0, base + (I2SR << reg_shift));
  173. return 0;
  174. }
  175. #define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
  176. #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8))
  177. #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8))
  178. static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
  179. {
  180. unsigned sr;
  181. ulong elapsed;
  182. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  183. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  184. ulong base = i2c_bus->base;
  185. ulong start_time = get_timer(0);
  186. for (;;) {
  187. sr = readb(base + (I2SR << reg_shift));
  188. if (sr & I2SR_IAL) {
  189. if (quirk)
  190. writeb(sr | I2SR_IAL, base +
  191. (I2SR << reg_shift));
  192. else
  193. writeb(sr & ~I2SR_IAL, base +
  194. (I2SR << reg_shift));
  195. printf("%s: Arbitration lost sr=%x cr=%x state=%x\n",
  196. __func__, sr, readb(base + (I2CR << reg_shift)),
  197. state);
  198. return -ERESTART;
  199. }
  200. if ((sr & (state >> 8)) == (unsigned char)state)
  201. return sr;
  202. WATCHDOG_RESET();
  203. elapsed = get_timer(start_time);
  204. if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
  205. break;
  206. }
  207. printf("%s: failed sr=%x cr=%x state=%x\n", __func__,
  208. sr, readb(base + (I2CR << reg_shift)), state);
  209. return -ETIMEDOUT;
  210. }
  211. static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte)
  212. {
  213. int ret;
  214. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  215. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  216. ulong base = i2c_bus->base;
  217. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  218. writeb(byte, base + (I2DR << reg_shift));
  219. ret = wait_for_sr_state(i2c_bus, ST_IIF);
  220. if (ret < 0)
  221. return ret;
  222. if (ret & I2SR_RX_NO_AK)
  223. return -EREMOTEIO;
  224. return 0;
  225. }
  226. /*
  227. * Stub implementations for outer i2c slave operations.
  228. */
  229. void __i2c_force_reset_slave(void)
  230. {
  231. }
  232. void i2c_force_reset_slave(void)
  233. __attribute__((weak, alias("__i2c_force_reset_slave")));
  234. /*
  235. * Stop I2C transaction
  236. */
  237. static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus)
  238. {
  239. int ret;
  240. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  241. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  242. ulong base = i2c_bus->base;
  243. unsigned int temp = readb(base + (I2CR << reg_shift));
  244. temp &= ~(I2CR_MSTA | I2CR_MTX);
  245. writeb(temp, base + (I2CR << reg_shift));
  246. ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
  247. if (ret < 0)
  248. printf("%s:trigger stop failed\n", __func__);
  249. }
  250. /*
  251. * Send start signal, chip address and
  252. * write register address
  253. */
  254. static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip,
  255. u32 addr, int alen)
  256. {
  257. unsigned int temp;
  258. int ret;
  259. bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false;
  260. ulong base = i2c_bus->base;
  261. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  262. /* Reset i2c slave */
  263. i2c_force_reset_slave();
  264. /* Enable I2C controller */
  265. if (quirk)
  266. ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS;
  267. else
  268. ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN);
  269. if (ret) {
  270. writeb(I2CR_IEN, base + (I2CR << reg_shift));
  271. /* Wait for controller to be stable */
  272. udelay(50);
  273. }
  274. if (readb(base + (IADR << reg_shift)) == (chip << 1))
  275. writeb((chip << 1) ^ 2, base + (IADR << reg_shift));
  276. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  277. ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE);
  278. if (ret < 0)
  279. return ret;
  280. /* Start I2C transaction */
  281. temp = readb(base + (I2CR << reg_shift));
  282. temp |= I2CR_MSTA;
  283. writeb(temp, base + (I2CR << reg_shift));
  284. ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY);
  285. if (ret < 0)
  286. return ret;
  287. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  288. writeb(temp, base + (I2CR << reg_shift));
  289. if (alen >= 0) {
  290. /* write slave address */
  291. ret = tx_byte(i2c_bus, chip << 1);
  292. if (ret < 0)
  293. return ret;
  294. while (alen--) {
  295. ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff);
  296. if (ret < 0)
  297. return ret;
  298. }
  299. }
  300. return 0;
  301. }
  302. #ifndef CONFIG_DM_I2C
  303. int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  304. {
  305. if (i2c_bus && i2c_bus->idle_bus_fn)
  306. return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data);
  307. return 0;
  308. }
  309. #else
  310. /*
  311. * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt
  312. * "
  313. * scl-gpios: specify the gpio related to SCL pin
  314. * sda-gpios: specify the gpio related to SDA pin
  315. * add pinctrl to configure i2c pins to gpio function for i2c
  316. * bus recovery, call it "gpio" state
  317. * "
  318. *
  319. * The i2c_idle_bus is an implementation following Linux Kernel.
  320. */
  321. int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
  322. {
  323. struct udevice *bus = i2c_bus->bus;
  324. struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus);
  325. struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio;
  326. struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio;
  327. int sda, scl, idle_sclks;
  328. int i, ret = 0;
  329. ulong elapsed, start_time;
  330. if (pinctrl_select_state(bus, "gpio")) {
  331. dev_dbg(bus, "Can not to switch to use gpio pinmux\n");
  332. /*
  333. * GPIO pinctrl for i2c force idle is not a must,
  334. * but it is strongly recommended to be used.
  335. * Because it can help you to recover from bad
  336. * i2c bus state. Do not return failure, because
  337. * it is not a must.
  338. */
  339. return 0;
  340. }
  341. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  342. dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
  343. scl = dm_gpio_get_value(scl_gpio);
  344. sda = dm_gpio_get_value(sda_gpio);
  345. if ((sda & scl) == 1)
  346. goto exit; /* Bus is idle already */
  347. /*
  348. * In most cases it is just enough to generate 8 + 1 SCLK
  349. * clocks to recover I2C slave device from 'stuck' state
  350. * (when for example SW reset was performed, in the middle of
  351. * I2C transmission).
  352. *
  353. * However, there are devices which send data in packets of
  354. * N bytes (N > 1). In such case we do need N * 8 + 1 SCLK
  355. * clocks.
  356. */
  357. idle_sclks = 8 + 1;
  358. if (i2c->max_transaction_bytes > 0)
  359. idle_sclks = i2c->max_transaction_bytes * 8 + 1;
  360. /* Send high and low on the SCL line */
  361. for (i = 0; i < idle_sclks; i++) {
  362. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT);
  363. dm_gpio_set_value(scl_gpio, 0);
  364. udelay(50);
  365. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  366. udelay(50);
  367. }
  368. start_time = get_timer(0);
  369. for (;;) {
  370. dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN);
  371. dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN);
  372. scl = dm_gpio_get_value(scl_gpio);
  373. sda = dm_gpio_get_value(sda_gpio);
  374. if ((sda & scl) == 1)
  375. break;
  376. WATCHDOG_RESET();
  377. elapsed = get_timer(start_time);
  378. if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
  379. ret = -EBUSY;
  380. printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl);
  381. break;
  382. }
  383. }
  384. exit:
  385. pinctrl_select_state(bus, "default");
  386. return ret;
  387. }
  388. #endif
  389. static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip,
  390. u32 addr, int alen)
  391. {
  392. int retry;
  393. int ret;
  394. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  395. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  396. if (!i2c_bus->base)
  397. return -EINVAL;
  398. for (retry = 0; retry < 3; retry++) {
  399. ret = i2c_init_transfer_(i2c_bus, chip, addr, alen);
  400. if (ret >= 0)
  401. return 0;
  402. i2c_imx_stop(i2c_bus);
  403. if (ret == -EREMOTEIO)
  404. return ret;
  405. printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip,
  406. retry);
  407. if (ret != -ERESTART)
  408. /* Disable controller */
  409. writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift));
  410. udelay(100);
  411. if (i2c_idle_bus(i2c_bus) < 0)
  412. break;
  413. }
  414. printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base);
  415. return ret;
  416. }
  417. static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf,
  418. int len)
  419. {
  420. int i, ret = 0;
  421. debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
  422. debug("write_data: ");
  423. /* use rc for counter */
  424. for (i = 0; i < len; ++i)
  425. debug(" 0x%02x", buf[i]);
  426. debug("\n");
  427. for (i = 0; i < len; i++) {
  428. ret = tx_byte(i2c_bus, buf[i]);
  429. if (ret < 0) {
  430. debug("i2c_write_data(): rc=%d\n", ret);
  431. break;
  432. }
  433. }
  434. return ret;
  435. }
  436. /* Will generate a STOP after the last byte if "last" is true, i.e. this is the
  437. * final message of a transaction. If not, it switches the bus back to TX mode
  438. * and does not send a STOP, leaving the bus in a state where a repeated start
  439. * and address can be sent for another message.
  440. */
  441. static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf,
  442. int len, bool last)
  443. {
  444. int ret;
  445. unsigned int temp;
  446. int i;
  447. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  448. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  449. ulong base = i2c_bus->base;
  450. debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len);
  451. /* setup bus to read data */
  452. temp = readb(base + (I2CR << reg_shift));
  453. temp &= ~(I2CR_MTX | I2CR_TX_NO_AK);
  454. if (len == 1)
  455. temp |= I2CR_TX_NO_AK;
  456. writeb(temp, base + (I2CR << reg_shift));
  457. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  458. /* dummy read to clear ICF */
  459. readb(base + (I2DR << reg_shift));
  460. /* read data */
  461. for (i = 0; i < len; i++) {
  462. ret = wait_for_sr_state(i2c_bus, ST_IIF);
  463. if (ret < 0) {
  464. debug("i2c_read_data(): ret=%d\n", ret);
  465. i2c_imx_stop(i2c_bus);
  466. return ret;
  467. }
  468. if (i == (len - 1)) {
  469. /* Final byte has already been received by master! When
  470. * we read it from I2DR, the master will start another
  471. * cycle. We must program it first to send a STOP or
  472. * switch to TX to avoid this.
  473. */
  474. if (last) {
  475. i2c_imx_stop(i2c_bus);
  476. } else {
  477. /* Final read, no stop, switch back to tx */
  478. temp = readb(base + (I2CR << reg_shift));
  479. temp |= I2CR_MTX | I2CR_TX_NO_AK;
  480. writeb(temp, base + (I2CR << reg_shift));
  481. }
  482. } else if (i == (len - 2)) {
  483. /* Master has already recevied penultimate byte. When
  484. * we read it from I2DR, master will start RX of final
  485. * byte. We must set TX_NO_AK now so it does not ACK
  486. * that final byte.
  487. */
  488. temp = readb(base + (I2CR << reg_shift));
  489. temp |= I2CR_TX_NO_AK;
  490. writeb(temp, base + (I2CR << reg_shift));
  491. }
  492. writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift));
  493. buf[i] = readb(base + (I2DR << reg_shift));
  494. }
  495. /* reuse ret for counter*/
  496. for (ret = 0; ret < len; ++ret)
  497. debug(" 0x%02x", buf[ret]);
  498. debug("\n");
  499. /* It is not clear to me that this is necessary */
  500. if (last)
  501. i2c_imx_stop(i2c_bus);
  502. return 0;
  503. }
  504. int __enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  505. {
  506. return 1;
  507. }
  508. int enable_i2c_clk(unsigned char enable, unsigned int i2c_num)
  509. __attribute__((weak, alias("__enable_i2c_clk")));
  510. #ifndef CONFIG_DM_I2C
  511. /*
  512. * Read data from I2C device
  513. *
  514. * The transactions use the syntax defined in the Linux kernel I2C docs.
  515. *
  516. * If alen is > 0, then this function will send a transaction of the form:
  517. * S Chip Wr [A] Addr [A] S Chip Rd [A] [data] A ... NA P
  518. * This is a normal I2C register read: writing the register address, then doing
  519. * a repeated start and reading the data.
  520. *
  521. * If alen == 0, then we get this transaction:
  522. * S Chip Wr [A] S Chip Rd [A] [data] A ... NA P
  523. * This is somewhat unusual, though valid, transaction. It addresses the chip
  524. * in write mode, but doesn't actually write any register address or data, then
  525. * does a repeated start and reads data.
  526. *
  527. * If alen < 0, then we get this transaction:
  528. * S Chip Rd [A] [data] A ... NA P
  529. * The chip is addressed in read mode and then data is read. No register
  530. * address is written first. This is perfectly valid on most devices and
  531. * required on some (usually those that don't act like an array of registers).
  532. */
  533. static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
  534. int alen, u8 *buf, int len)
  535. {
  536. int ret = 0;
  537. u32 temp;
  538. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  539. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  540. ulong base = i2c_bus->base;
  541. ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
  542. if (ret < 0)
  543. return ret;
  544. if (alen >= 0) {
  545. temp = readb(base + (I2CR << reg_shift));
  546. temp |= I2CR_RSTA;
  547. writeb(temp, base + (I2CR << reg_shift));
  548. }
  549. ret = tx_byte(i2c_bus, (chip << 1) | 1);
  550. if (ret < 0) {
  551. i2c_imx_stop(i2c_bus);
  552. return ret;
  553. }
  554. ret = i2c_read_data(i2c_bus, chip, buf, len, true);
  555. i2c_imx_stop(i2c_bus);
  556. return ret;
  557. }
  558. /*
  559. * Write data to I2C device
  560. *
  561. * If alen > 0, we get this transaction:
  562. * S Chip Wr [A] addr [A] data [A] ... [A] P
  563. * An ordinary write register command.
  564. *
  565. * If alen == 0, then we get this:
  566. * S Chip Wr [A] data [A] ... [A] P
  567. * This is a simple I2C write.
  568. *
  569. * If alen < 0, then we get this:
  570. * S data [A] ... [A] P
  571. * This is most likely NOT something that should be used. It doesn't send the
  572. * chip address first, so in effect, the first byte of data will be used as the
  573. * address.
  574. */
  575. static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr,
  576. int alen, const u8 *buf, int len)
  577. {
  578. int ret = 0;
  579. ret = i2c_init_transfer(i2c_bus, chip, addr, alen);
  580. if (ret < 0)
  581. return ret;
  582. ret = i2c_write_data(i2c_bus, chip, buf, len);
  583. i2c_imx_stop(i2c_bus);
  584. return ret;
  585. }
  586. #if !defined(I2C2_BASE_ADDR)
  587. #define I2C2_BASE_ADDR 0
  588. #endif
  589. #if !defined(I2C3_BASE_ADDR)
  590. #define I2C3_BASE_ADDR 0
  591. #endif
  592. #if !defined(I2C4_BASE_ADDR)
  593. #define I2C4_BASE_ADDR 0
  594. #endif
  595. #if !defined(I2C5_BASE_ADDR)
  596. #define I2C5_BASE_ADDR 0
  597. #endif
  598. #if !defined(I2C6_BASE_ADDR)
  599. #define I2C6_BASE_ADDR 0
  600. #endif
  601. #if !defined(I2C7_BASE_ADDR)
  602. #define I2C7_BASE_ADDR 0
  603. #endif
  604. #if !defined(I2C8_BASE_ADDR)
  605. #define I2C8_BASE_ADDR 0
  606. #endif
  607. static struct mxc_i2c_bus mxc_i2c_buses[] = {
  608. #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \
  609. defined(CONFIG_FSL_LAYERSCAPE)
  610. { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG },
  611. { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG },
  612. { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG },
  613. { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG },
  614. { 4, I2C5_BASE_ADDR, I2C_QUIRK_FLAG },
  615. { 5, I2C6_BASE_ADDR, I2C_QUIRK_FLAG },
  616. { 6, I2C7_BASE_ADDR, I2C_QUIRK_FLAG },
  617. { 7, I2C8_BASE_ADDR, I2C_QUIRK_FLAG },
  618. #else
  619. { 0, I2C1_BASE_ADDR, 0 },
  620. { 1, I2C2_BASE_ADDR, 0 },
  621. { 2, I2C3_BASE_ADDR, 0 },
  622. { 3, I2C4_BASE_ADDR, 0 },
  623. { 4, I2C5_BASE_ADDR, 0 },
  624. { 5, I2C6_BASE_ADDR, 0 },
  625. { 6, I2C7_BASE_ADDR, 0 },
  626. { 7, I2C8_BASE_ADDR, 0 },
  627. #endif
  628. };
  629. struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap)
  630. {
  631. return &mxc_i2c_buses[adap->hwadapnr];
  632. }
  633. static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip,
  634. uint addr, int alen, uint8_t *buffer,
  635. int len)
  636. {
  637. return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len);
  638. }
  639. static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip,
  640. uint addr, int alen, uint8_t *buffer,
  641. int len)
  642. {
  643. return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len);
  644. }
  645. /*
  646. * Test if a chip at a given address responds (probe the chip)
  647. */
  648. static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
  649. {
  650. return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0);
  651. }
  652. void bus_i2c_init(int index, int speed, int unused,
  653. int (*idle_bus_fn)(void *p), void *idle_bus_data)
  654. {
  655. int ret;
  656. if (index >= ARRAY_SIZE(mxc_i2c_buses)) {
  657. debug("Error i2c index\n");
  658. return;
  659. }
  660. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  661. if (i2c_fused((ulong)mxc_i2c_buses[index].base)) {
  662. printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
  663. (ulong)mxc_i2c_buses[index].base);
  664. return;
  665. }
  666. }
  667. /*
  668. * Warning: Be careful to allow the assignment to a static
  669. * variable here. This function could be called while U-Boot is
  670. * still running in flash memory. So such assignment is equal
  671. * to write data to flash without erasing.
  672. */
  673. if (idle_bus_fn)
  674. mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn;
  675. if (idle_bus_data)
  676. mxc_i2c_buses[index].idle_bus_data = idle_bus_data;
  677. ret = enable_i2c_clk(1, index);
  678. if (ret < 0) {
  679. debug("I2C-%d clk fail to enable.\n", index);
  680. return;
  681. }
  682. bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed);
  683. }
  684. /*
  685. * Early init I2C for prepare read the clk through I2C.
  686. */
  687. void i2c_early_init_f(void)
  688. {
  689. ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base;
  690. bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data
  691. & I2C_QUIRK_FLAG ? true : false;
  692. int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  693. /* Set I2C divider value */
  694. writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift));
  695. /* Reset module */
  696. writeb(I2CR_IDIS, base + (I2CR << reg_shift));
  697. writeb(0, base + (I2SR << reg_shift));
  698. /* Enable I2C */
  699. writeb(I2CR_IEN, base + (I2CR << reg_shift));
  700. }
  701. /*
  702. * Init I2C Bus
  703. */
  704. static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
  705. {
  706. bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL);
  707. }
  708. /*
  709. * Set I2C Speed
  710. */
  711. static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
  712. {
  713. return bus_i2c_set_bus_speed(i2c_get_base(adap), speed);
  714. }
  715. /*
  716. * Register mxc i2c adapters
  717. */
  718. #ifdef CONFIG_SYS_I2C_MXC_I2C1
  719. U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe,
  720. mxc_i2c_read, mxc_i2c_write,
  721. mxc_i2c_set_bus_speed,
  722. CONFIG_SYS_MXC_I2C1_SPEED,
  723. CONFIG_SYS_MXC_I2C1_SLAVE, 0)
  724. #endif
  725. #ifdef CONFIG_SYS_I2C_MXC_I2C2
  726. U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
  727. mxc_i2c_read, mxc_i2c_write,
  728. mxc_i2c_set_bus_speed,
  729. CONFIG_SYS_MXC_I2C2_SPEED,
  730. CONFIG_SYS_MXC_I2C2_SLAVE, 1)
  731. #endif
  732. #ifdef CONFIG_SYS_I2C_MXC_I2C3
  733. U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
  734. mxc_i2c_read, mxc_i2c_write,
  735. mxc_i2c_set_bus_speed,
  736. CONFIG_SYS_MXC_I2C3_SPEED,
  737. CONFIG_SYS_MXC_I2C3_SLAVE, 2)
  738. #endif
  739. #ifdef CONFIG_SYS_I2C_MXC_I2C4
  740. U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe,
  741. mxc_i2c_read, mxc_i2c_write,
  742. mxc_i2c_set_bus_speed,
  743. CONFIG_SYS_MXC_I2C4_SPEED,
  744. CONFIG_SYS_MXC_I2C4_SLAVE, 3)
  745. #endif
  746. #ifdef CONFIG_SYS_I2C_MXC_I2C5
  747. U_BOOT_I2C_ADAP_COMPLETE(mxc4, mxc_i2c_init, mxc_i2c_probe,
  748. mxc_i2c_read, mxc_i2c_write,
  749. mxc_i2c_set_bus_speed,
  750. CONFIG_SYS_MXC_I2C5_SPEED,
  751. CONFIG_SYS_MXC_I2C5_SLAVE, 4)
  752. #endif
  753. #ifdef CONFIG_SYS_I2C_MXC_I2C6
  754. U_BOOT_I2C_ADAP_COMPLETE(mxc5, mxc_i2c_init, mxc_i2c_probe,
  755. mxc_i2c_read, mxc_i2c_write,
  756. mxc_i2c_set_bus_speed,
  757. CONFIG_SYS_MXC_I2C6_SPEED,
  758. CONFIG_SYS_MXC_I2C6_SLAVE, 5)
  759. #endif
  760. #ifdef CONFIG_SYS_I2C_MXC_I2C7
  761. U_BOOT_I2C_ADAP_COMPLETE(mxc6, mxc_i2c_init, mxc_i2c_probe,
  762. mxc_i2c_read, mxc_i2c_write,
  763. mxc_i2c_set_bus_speed,
  764. CONFIG_SYS_MXC_I2C7_SPEED,
  765. CONFIG_SYS_MXC_I2C7_SLAVE, 6)
  766. #endif
  767. #ifdef CONFIG_SYS_I2C_MXC_I2C8
  768. U_BOOT_I2C_ADAP_COMPLETE(mxc7, mxc_i2c_init, mxc_i2c_probe,
  769. mxc_i2c_read, mxc_i2c_write,
  770. mxc_i2c_set_bus_speed,
  771. CONFIG_SYS_MXC_I2C8_SPEED,
  772. CONFIG_SYS_MXC_I2C8_SLAVE, 7)
  773. #endif
  774. #else
  775. static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  776. {
  777. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  778. return bus_i2c_set_bus_speed(i2c_bus, speed);
  779. }
  780. static int mxc_i2c_probe(struct udevice *bus)
  781. {
  782. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  783. const void *fdt = gd->fdt_blob;
  784. int node = dev_of_offset(bus);
  785. fdt_addr_t addr;
  786. int ret, ret2;
  787. i2c_bus->driver_data = dev_get_driver_data(bus);
  788. addr = dev_read_addr(bus);
  789. if (addr == FDT_ADDR_T_NONE)
  790. return -EINVAL;
  791. if (CONFIG_IS_ENABLED(IMX_MODULE_FUSE)) {
  792. if (i2c_fused((ulong)addr)) {
  793. printf("SoC fuse indicates I2C@0x%lx is unavailable.\n",
  794. (ulong)addr);
  795. return -ENODEV;
  796. }
  797. }
  798. i2c_bus->base = addr;
  799. i2c_bus->index = bus->seq;
  800. i2c_bus->bus = bus;
  801. /* Enable clk */
  802. #if CONFIG_IS_ENABLED(CLK)
  803. ret = clk_get_by_index(bus, 0, &i2c_bus->per_clk);
  804. if (ret) {
  805. printf("Failed to get i2c clk\n");
  806. return ret;
  807. }
  808. ret = clk_enable(&i2c_bus->per_clk);
  809. if (ret) {
  810. printf("Failed to enable i2c clk\n");
  811. return ret;
  812. }
  813. #else
  814. ret = enable_i2c_clk(1, bus->seq);
  815. if (ret < 0)
  816. return ret;
  817. #endif
  818. /*
  819. * See Documentation/devicetree/bindings/i2c/i2c-imx.txt
  820. * Use gpio to force bus idle when necessary.
  821. */
  822. ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio");
  823. if (ret < 0) {
  824. debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base);
  825. } else {
  826. ret = gpio_request_by_name_nodev(offset_to_ofnode(node),
  827. "scl-gpios", 0, &i2c_bus->scl_gpio,
  828. GPIOD_IS_OUT);
  829. ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node),
  830. "sda-gpios", 0, &i2c_bus->sda_gpio,
  831. GPIOD_IS_OUT);
  832. if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) ||
  833. !dm_gpio_is_valid(&i2c_bus->scl_gpio) ||
  834. ret || ret2) {
  835. dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base);
  836. return -EINVAL;
  837. }
  838. }
  839. /*
  840. * Pinmux settings are in board file now, until pinmux is supported,
  841. * we can set pinmux here in probe function.
  842. */
  843. debug("i2c : controller bus %d at %lu , speed %d: ",
  844. bus->seq, i2c_bus->base,
  845. i2c_bus->speed);
  846. return 0;
  847. }
  848. /* Sends: S Addr Wr [A|NA] P */
  849. static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr,
  850. u32 chip_flags)
  851. {
  852. int ret;
  853. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  854. ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0);
  855. if (ret < 0) {
  856. debug("%s failed, ret = %d\n", __func__, ret);
  857. return ret;
  858. }
  859. i2c_imx_stop(i2c_bus);
  860. return 0;
  861. }
  862. static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
  863. {
  864. struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus);
  865. int ret = 0;
  866. ulong base = i2c_bus->base;
  867. int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ?
  868. VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT;
  869. int read_mode;
  870. /* Here address len is set to -1 to not send any address at first.
  871. * Otherwise i2c_init_transfer will send the chip address with write
  872. * mode set. This is wrong if the 1st message is read.
  873. */
  874. ret = i2c_init_transfer(i2c_bus, msg->addr, 0, -1);
  875. if (ret < 0) {
  876. debug("i2c_init_transfer error: %d\n", ret);
  877. return ret;
  878. }
  879. read_mode = -1; /* So it's always different on the first message */
  880. for (; nmsgs > 0; nmsgs--, msg++) {
  881. const int msg_is_read = !!(msg->flags & I2C_M_RD);
  882. debug("i2c_xfer: chip=0x%x, len=0x%x, dir=%c\n", msg->addr,
  883. msg->len, msg_is_read ? 'R' : 'W');
  884. if (msg_is_read != read_mode) {
  885. /* Send repeated start if not 1st message */
  886. if (read_mode != -1) {
  887. debug("i2c_xfer: [RSTART]\n");
  888. ret = readb(base + (I2CR << reg_shift));
  889. ret |= I2CR_RSTA;
  890. writeb(ret, base + (I2CR << reg_shift));
  891. }
  892. debug("i2c_xfer: [ADDR %02x | %c]\n", msg->addr,
  893. msg_is_read ? 'R' : 'W');
  894. ret = tx_byte(i2c_bus, (msg->addr << 1) | msg_is_read);
  895. if (ret < 0) {
  896. debug("i2c_xfer: [STOP]\n");
  897. i2c_imx_stop(i2c_bus);
  898. break;
  899. }
  900. read_mode = msg_is_read;
  901. }
  902. if (msg->flags & I2C_M_RD)
  903. ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
  904. msg->len, nmsgs == 1 ||
  905. (msg->flags & I2C_M_STOP));
  906. else
  907. ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
  908. msg->len);
  909. if (ret < 0)
  910. break;
  911. }
  912. if (ret)
  913. debug("i2c_write: error sending\n");
  914. i2c_imx_stop(i2c_bus);
  915. return ret;
  916. }
  917. static const struct dm_i2c_ops mxc_i2c_ops = {
  918. .xfer = mxc_i2c_xfer,
  919. .probe_chip = mxc_i2c_probe_chip,
  920. .set_bus_speed = mxc_i2c_set_bus_speed,
  921. };
  922. static const struct udevice_id mxc_i2c_ids[] = {
  923. { .compatible = "fsl,imx21-i2c", },
  924. { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, },
  925. {}
  926. };
  927. U_BOOT_DRIVER(i2c_mxc) = {
  928. .name = "i2c_mxc",
  929. .id = UCLASS_I2C,
  930. .of_match = mxc_i2c_ids,
  931. .probe = mxc_i2c_probe,
  932. .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus),
  933. .ops = &mxc_i2c_ops,
  934. .flags = DM_FLAG_PRE_RELOC,
  935. };
  936. #endif