mxs_gpio.c 7.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX28 GPIO control code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <malloc.h>
  11. #include <linux/bitops.h>
  12. #include <linux/errno.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/imx-regs.h>
  16. #if defined(CONFIG_MX23)
  17. #define PINCTRL_BANKS 3
  18. #define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
  19. #define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
  20. #define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
  21. #define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
  22. #define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
  23. #define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
  24. #elif defined(CONFIG_MX28)
  25. #define PINCTRL_BANKS 5
  26. #define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
  27. #define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
  28. #define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
  29. #define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
  30. #define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
  31. #define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
  32. #else
  33. #error "Please select CONFIG_MX23 or CONFIG_MX28"
  34. #endif
  35. #define GPIO_INT_FALL_EDGE 0x0
  36. #define GPIO_INT_LOW_LEV 0x1
  37. #define GPIO_INT_RISE_EDGE 0x2
  38. #define GPIO_INT_HIGH_LEV 0x3
  39. #define GPIO_INT_LEV_MASK (1 << 0)
  40. #define GPIO_INT_POL_MASK (1 << 1)
  41. void mxs_gpio_init(void)
  42. {
  43. int i;
  44. for (i = 0; i < PINCTRL_BANKS; i++) {
  45. writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
  46. writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
  47. /* Use SCT address here to clear the IRQSTAT bits */
  48. writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
  49. }
  50. }
  51. #if !CONFIG_IS_ENABLED(DM_GPIO)
  52. int gpio_get_value(unsigned gpio)
  53. {
  54. uint32_t bank = PAD_BANK(gpio);
  55. uint32_t offset = PINCTRL_DIN(bank);
  56. struct mxs_register_32 *reg =
  57. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  58. return (readl(&reg->reg) >> PAD_PIN(gpio)) & 1;
  59. }
  60. void gpio_set_value(unsigned gpio, int value)
  61. {
  62. uint32_t bank = PAD_BANK(gpio);
  63. uint32_t offset = PINCTRL_DOUT(bank);
  64. struct mxs_register_32 *reg =
  65. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  66. if (value)
  67. writel(1 << PAD_PIN(gpio), &reg->reg_set);
  68. else
  69. writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  70. }
  71. int gpio_direction_input(unsigned gpio)
  72. {
  73. uint32_t bank = PAD_BANK(gpio);
  74. uint32_t offset = PINCTRL_DOE(bank);
  75. struct mxs_register_32 *reg =
  76. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  77. writel(1 << PAD_PIN(gpio), &reg->reg_clr);
  78. return 0;
  79. }
  80. int gpio_direction_output(unsigned gpio, int value)
  81. {
  82. uint32_t bank = PAD_BANK(gpio);
  83. uint32_t offset = PINCTRL_DOE(bank);
  84. struct mxs_register_32 *reg =
  85. (struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
  86. gpio_set_value(gpio, value);
  87. writel(1 << PAD_PIN(gpio), &reg->reg_set);
  88. return 0;
  89. }
  90. int gpio_request(unsigned gpio, const char *label)
  91. {
  92. if (PAD_BANK(gpio) >= PINCTRL_BANKS)
  93. return -1;
  94. return 0;
  95. }
  96. int gpio_free(unsigned gpio)
  97. {
  98. return 0;
  99. }
  100. int name_to_gpio(const char *name)
  101. {
  102. unsigned bank, pin;
  103. char *end;
  104. bank = simple_strtoul(name, &end, 10);
  105. if (!*end || *end != ':')
  106. return bank;
  107. pin = simple_strtoul(end + 1, NULL, 10);
  108. return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
  109. }
  110. #else /* DM_GPIO */
  111. #include <dm.h>
  112. #include <asm/gpio.h>
  113. #include <dt-structs.h>
  114. #include <asm/arch/gpio.h>
  115. #define MXS_MAX_GPIO_PER_BANK 32
  116. #ifdef CONFIG_MX28
  117. #define dtd_fsl_imx_gpio dtd_fsl_imx28_gpio
  118. #else /* CONFIG_MX23 */
  119. #define dtd_fsl_imx_gpio dtd_fsl_imx23_gpio
  120. #endif
  121. DECLARE_GLOBAL_DATA_PTR;
  122. /*
  123. * According to i.MX28 Reference Manual:
  124. * 'i.MX28 Applications Processor Reference Manual, Rev. 1, 2010'
  125. * The i.MX28 has following number of GPIOs available:
  126. * Bank 0: 0-28 -> 29 PINS
  127. * Bank 1: 0-31 -> 32 PINS
  128. * Bank 2: 0-27 -> 28 PINS
  129. * Bank 3: 0-30 -> 31 PINS
  130. * Bank 4: 0-20 -> 21 PINS
  131. */
  132. struct mxs_gpio_platdata {
  133. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  134. struct dtd_fsl_imx_gpio dtplat;
  135. #endif
  136. unsigned int bank;
  137. int gpio_ranges;
  138. };
  139. struct mxs_gpio_priv {
  140. unsigned int bank;
  141. };
  142. static int mxs_gpio_get_value(struct udevice *dev, unsigned offset)
  143. {
  144. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  145. struct mxs_register_32 *reg =
  146. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  147. PINCTRL_DIN(priv->bank));
  148. return (readl(&reg->reg) >> offset) & 1;
  149. }
  150. static int mxs_gpio_set_value(struct udevice *dev, unsigned offset,
  151. int value)
  152. {
  153. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  154. struct mxs_register_32 *reg =
  155. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  156. PINCTRL_DOUT(priv->bank));
  157. if (value)
  158. writel(BIT(offset), &reg->reg_set);
  159. else
  160. writel(BIT(offset), &reg->reg_clr);
  161. return 0;
  162. }
  163. static int mxs_gpio_direction_input(struct udevice *dev, unsigned offset)
  164. {
  165. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  166. struct mxs_register_32 *reg =
  167. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  168. PINCTRL_DOE(priv->bank));
  169. writel(BIT(offset), &reg->reg_clr);
  170. return 0;
  171. }
  172. static int mxs_gpio_direction_output(struct udevice *dev, unsigned offset,
  173. int value)
  174. {
  175. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  176. struct mxs_register_32 *reg =
  177. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  178. PINCTRL_DOE(priv->bank));
  179. mxs_gpio_set_value(dev, offset, value);
  180. writel(BIT(offset), &reg->reg_set);
  181. return 0;
  182. }
  183. static int mxs_gpio_get_function(struct udevice *dev, unsigned offset)
  184. {
  185. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  186. struct mxs_register_32 *reg =
  187. (struct mxs_register_32 *)(MXS_PINCTRL_BASE +
  188. PINCTRL_DOE(priv->bank));
  189. bool is_output = !!(readl(&reg->reg) >> offset);
  190. return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
  191. }
  192. static const struct dm_gpio_ops gpio_mxs_ops = {
  193. .direction_input = mxs_gpio_direction_input,
  194. .direction_output = mxs_gpio_direction_output,
  195. .get_value = mxs_gpio_get_value,
  196. .set_value = mxs_gpio_set_value,
  197. .get_function = mxs_gpio_get_function,
  198. };
  199. static int mxs_gpio_probe(struct udevice *dev)
  200. {
  201. struct mxs_gpio_platdata *plat = dev_get_platdata(dev);
  202. struct mxs_gpio_priv *priv = dev_get_priv(dev);
  203. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  204. char name[16], *str;
  205. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  206. struct dtd_fsl_imx_gpio *dtplat = &plat->dtplat;
  207. priv->bank = (unsigned int)dtplat->reg[0];
  208. uc_priv->gpio_count = dtplat->gpio_ranges[3];
  209. #else
  210. priv->bank = (unsigned int)plat->bank;
  211. uc_priv->gpio_count = plat->gpio_ranges;
  212. #endif
  213. snprintf(name, sizeof(name), "GPIO%d_", priv->bank);
  214. str = strdup(name);
  215. if (!str)
  216. return -ENOMEM;
  217. uc_priv->bank_name = str;
  218. debug("%s: %s: %d pins base: 0x%x\n", __func__, uc_priv->bank_name,
  219. uc_priv->gpio_count, priv->bank);
  220. return 0;
  221. }
  222. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  223. static int mxs_ofdata_to_platdata(struct udevice *dev)
  224. {
  225. struct mxs_gpio_platdata *plat = dev->platdata;
  226. struct fdtdec_phandle_args args;
  227. int node = dev_of_offset(dev);
  228. int ret;
  229. plat->bank = dev_read_addr(dev);
  230. if (plat->bank == FDT_ADDR_T_NONE) {
  231. printf("%s: No 'reg' property defined!\n", __func__);
  232. return -EINVAL;
  233. }
  234. ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
  235. NULL, 3, 0, &args);
  236. if (ret)
  237. printf("%s: 'gpio-ranges' not defined - using default!\n",
  238. __func__);
  239. plat->gpio_ranges = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK;
  240. return 0;
  241. }
  242. static const struct udevice_id mxs_gpio_ids[] = {
  243. { .compatible = "fsl,imx23-gpio" },
  244. { .compatible = "fsl,imx28-gpio" },
  245. { }
  246. };
  247. #endif
  248. U_BOOT_DRIVER(fsl_imx23_gpio) = {
  249. .name = "fsl_imx23_gpio",
  250. .id = UCLASS_GPIO,
  251. .ops = &gpio_mxs_ops,
  252. .probe = mxs_gpio_probe,
  253. .priv_auto_alloc_size = sizeof(struct mxs_gpio_priv),
  254. .platdata_auto_alloc_size = sizeof(struct mxs_gpio_platdata),
  255. #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
  256. .of_match = mxs_gpio_ids,
  257. .ofdata_to_platdata = mxs_ofdata_to_platdata,
  258. #endif
  259. };
  260. U_BOOT_DRIVER_ALIAS(fsl_imx23_gpio, fsl_imx28_gpio)
  261. #endif /* DM_GPIO */