clk-agilex.c 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581
  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4. */
  5. #include <common.h>
  6. #include <log.h>
  7. #include <asm/io.h>
  8. #include <clk-uclass.h>
  9. #include <dm.h>
  10. #include <dm/lists.h>
  11. #include <dm/util.h>
  12. #include <dt-bindings/clock/agilex-clock.h>
  13. #include <linux/bitops.h>
  14. #include <asm/arch/clock_manager.h>
  15. DECLARE_GLOBAL_DATA_PTR;
  16. struct socfpga_clk_platdata {
  17. void __iomem *regs;
  18. };
  19. /*
  20. * function to write the bypass register which requires a poll of the
  21. * busy bit
  22. */
  23. static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val)
  24. {
  25. CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
  26. cm_wait_for_fsm();
  27. }
  28. static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val)
  29. {
  30. CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
  31. cm_wait_for_fsm();
  32. }
  33. /* function to write the ctrl register which requires a poll of the busy bit */
  34. static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val)
  35. {
  36. CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
  37. cm_wait_for_fsm();
  38. }
  39. #define MEMBUS_MAINPLL 0
  40. #define MEMBUS_PERPLL 1
  41. #define MEMBUS_TIMEOUT 1000
  42. #define MEMBUS_ADDR_CLKSLICE 0x27
  43. #define MEMBUS_CLKSLICE_SYNC_MODE_EN 0x80
  44. static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
  45. int timeout)
  46. {
  47. int cnt = 0;
  48. u32 req_status;
  49. if (pll == MEMBUS_MAINPLL)
  50. req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
  51. else
  52. req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
  53. while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {
  54. if (pll == MEMBUS_MAINPLL)
  55. req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);
  56. else
  57. req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);
  58. cnt++;
  59. }
  60. if (cnt >= timeout)
  61. return -ETIMEDOUT;
  62. return 0;
  63. }
  64. static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
  65. u32 addr_offset, u32 wdat, int timeout)
  66. {
  67. u32 addr;
  68. u32 val;
  69. addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
  70. val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |
  71. (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);
  72. if (pll == MEMBUS_MAINPLL)
  73. CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
  74. else
  75. CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
  76. debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);
  77. return membus_wait_for_req(plat, pll, timeout);
  78. }
  79. static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
  80. u32 addr_offset, u32 *rdata, int timeout)
  81. {
  82. u32 addr;
  83. u32 val;
  84. addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);
  85. val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr);
  86. if (pll == MEMBUS_MAINPLL)
  87. CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);
  88. else
  89. CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);
  90. *rdata = 0;
  91. if (membus_wait_for_req(plat, pll, timeout))
  92. return -ETIMEDOUT;
  93. if (pll == MEMBUS_MAINPLL)
  94. *rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT);
  95. else
  96. *rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT);
  97. debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr);
  98. return 0;
  99. }
  100. static u32 calc_vocalib_pll(u32 pllm, u32 pllglob)
  101. {
  102. u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;
  103. mdiv = pllm & CLKMGR_PLLM_MDIV_MASK;
  104. arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
  105. CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
  106. drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >>
  107. CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET;
  108. refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >>
  109. CLKMGR_PLLGLOB_REFCLKDIV_OFFSET;
  110. mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv));
  111. if (!mscnt)
  112. mscnt = 1;
  113. hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) -
  114. CLKMGR_VCOCALIB_HSCNT_CONST;
  115. vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
  116. ((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) &
  117. CLKMGR_VCOCALIB_MSCNT_MASK);
  118. /* Dump all the pll calibration settings for debug purposes */
  119. debug("mdiv : %d\n", mdiv);
  120. debug("arefclkdiv : %d\n", arefclkdiv);
  121. debug("drefclkdiv : %d\n", drefclkdiv);
  122. debug("refclkdiv : %d\n", refclkdiv);
  123. debug("mscnt : %d\n", mscnt);
  124. debug("hscnt : %d\n", hscnt);
  125. debug("vcocalib : 0x%08x\n", vcocalib);
  126. return vcocalib;
  127. }
  128. /*
  129. * Setup clocks while making no assumptions about previous state of the clocks.
  130. */
  131. static void clk_basic_init(struct udevice *dev,
  132. const struct cm_config * const cfg)
  133. {
  134. struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
  135. u32 vcocalib;
  136. u32 rdata;
  137. if (!cfg)
  138. return;
  139. /* Put both PLLs in bypass */
  140. clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
  141. clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
  142. /* Put both PLLs in Reset and Power Down */
  143. CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
  144. CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
  145. CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB,
  146. CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
  147. /* setup main PLL dividers where calculate the vcocalib value */
  148. vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob);
  149. CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
  150. CLKMGR_MAINPLL_PLLGLOB);
  151. CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK);
  152. CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB);
  153. CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0);
  154. CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1);
  155. CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2);
  156. CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3);
  157. CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM);
  158. CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
  159. CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
  160. CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
  161. /* setup peripheral PLL dividers where calculate the vcocalib value */
  162. vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob);
  163. CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,
  164. CLKMGR_PERPLL_PLLGLOB);
  165. CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK);
  166. CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB);
  167. CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0);
  168. CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1);
  169. CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2);
  170. CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3);
  171. CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM);
  172. CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
  173. CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
  174. /* Take both PLL out of reset and power up */
  175. CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,
  176. CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
  177. CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,
  178. CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
  179. /* Membus programming to set mainpll and perripll to
  180. * source synchronous mode
  181. */
  182. membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
  183. MEMBUS_TIMEOUT);
  184. membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE,
  185. (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
  186. MEMBUS_TIMEOUT);
  187. membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, &rdata,
  188. MEMBUS_TIMEOUT);
  189. membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE,
  190. (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),
  191. MEMBUS_TIMEOUT);
  192. cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
  193. /* Configure ping pong counters in altera group */
  194. CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
  195. CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
  196. CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
  197. CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
  198. CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
  199. CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);
  200. CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);
  201. CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);
  202. CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);
  203. CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);
  204. CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |
  205. CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
  206. CLKMGR_MAINPLL_PLLGLOB);
  207. CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |
  208. CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
  209. CLKMGR_PERPLL_PLLGLOB);
  210. /* Take all PLLs out of bypass */
  211. clk_write_bypass_mainpll(plat, 0);
  212. clk_write_bypass_perpll(plat, 0);
  213. /* Clear the loss of lock bits (write 1 to clear) */
  214. CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,
  215. CLKMGR_INTER_PERPLLLOST_MASK |
  216. CLKMGR_INTER_MAINPLLLOST_MASK);
  217. /* Take all ping pong counters out of reset */
  218. CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,
  219. CLKMGR_ALT_EXTCNTRST_ALLCNTRST);
  220. /* Out of boot mode */
  221. clk_write_ctrl(plat,
  222. CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);
  223. }
  224. static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
  225. u32 pllglob_reg, u32 pllm_reg)
  226. {
  227. u64 fref, arefdiv, mdiv, reg, vco;
  228. reg = CM_REG_READL(plat, pllglob_reg);
  229. fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
  230. CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
  231. switch (fref) {
  232. case CLKMGR_VCO_PSRC_EOSC1:
  233. fref = cm_get_osc_clk_hz();
  234. break;
  235. case CLKMGR_VCO_PSRC_INTOSC:
  236. fref = cm_get_intosc_clk_hz();
  237. break;
  238. case CLKMGR_VCO_PSRC_F2S:
  239. fref = cm_get_fpga_clk_hz();
  240. break;
  241. }
  242. arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>
  243. CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;
  244. mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK;
  245. vco = fref / arefdiv;
  246. vco = vco * mdiv;
  247. return vco;
  248. }
  249. static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat)
  250. {
  251. return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,
  252. CLKMGR_MAINPLL_PLLM);
  253. }
  254. static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat)
  255. {
  256. return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,
  257. CLKMGR_PERPLL_PLLM);
  258. }
  259. static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg)
  260. {
  261. u32 clksrc = CM_REG_READL(plat, reg);
  262. return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;
  263. }
  264. static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
  265. u32 main_reg, u32 per_reg)
  266. {
  267. u64 clock;
  268. u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
  269. switch (clklsrc) {
  270. case CLKMGR_CLKSRC_MAIN:
  271. clock = clk_get_main_vco_clk_hz(plat);
  272. clock /= (CM_REG_READL(plat, main_reg) &
  273. CLKMGR_CLKCNT_MSK);
  274. break;
  275. case CLKMGR_CLKSRC_PER:
  276. clock = clk_get_per_vco_clk_hz(plat);
  277. clock /= (CM_REG_READL(plat, per_reg) &
  278. CLKMGR_CLKCNT_MSK);
  279. break;
  280. case CLKMGR_CLKSRC_OSC1:
  281. clock = cm_get_osc_clk_hz();
  282. break;
  283. case CLKMGR_CLKSRC_INTOSC:
  284. clock = cm_get_intosc_clk_hz();
  285. break;
  286. case CLKMGR_CLKSRC_FPGA:
  287. clock = cm_get_fpga_clk_hz();
  288. break;
  289. default:
  290. return 0;
  291. }
  292. return clock;
  293. }
  294. static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat)
  295. {
  296. u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,
  297. CLKMGR_MAINPLL_PLLC0,
  298. CLKMGR_PERPLL_PLLC0);
  299. clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &
  300. CLKMGR_CLKCNT_MSK);
  301. return clock;
  302. }
  303. static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat)
  304. {
  305. return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,
  306. CLKMGR_MAINPLL_PLLC1,
  307. CLKMGR_PERPLL_PLLC1);
  308. }
  309. static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat)
  310. {
  311. u64 clock = clk_get_l3_main_clk_hz(plat);
  312. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  313. CLKMGR_NOCDIV_L4MAIN_OFFSET) &
  314. CLKMGR_NOCDIV_DIVIDER_MASK);
  315. return clock;
  316. }
  317. static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat)
  318. {
  319. u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,
  320. CLKMGR_MAINPLL_PLLC3,
  321. CLKMGR_PERPLL_PLLC3);
  322. clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &
  323. CLKMGR_CLKCNT_MSK);
  324. return clock / 4;
  325. }
  326. static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat)
  327. {
  328. u64 clock = clk_get_l3_main_clk_hz(plat);
  329. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  330. CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
  331. CLKMGR_NOCDIV_DIVIDER_MASK);
  332. return clock;
  333. }
  334. static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat)
  335. {
  336. u64 clock = clk_get_l3_main_clk_hz(plat);
  337. clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>
  338. CLKMGR_NOCDIV_L4MPCLK_OFFSET) &
  339. CLKMGR_NOCDIV_DIVIDER_MASK);
  340. return clock;
  341. }
  342. static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat)
  343. {
  344. if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)
  345. return clk_get_l3_main_clk_hz(plat) / 2;
  346. return clk_get_l3_main_clk_hz(plat) / 4;
  347. }
  348. static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id)
  349. {
  350. bool emacsel_a;
  351. u32 ctl;
  352. u32 ctr_reg;
  353. u32 clock;
  354. u32 div;
  355. u32 reg;
  356. /* Get EMAC clock source */
  357. ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);
  358. if (emac_id == AGILEX_EMAC0_CLK)
  359. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &
  360. CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;
  361. else if (emac_id == AGILEX_EMAC1_CLK)
  362. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &
  363. CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;
  364. else if (emac_id == AGILEX_EMAC2_CLK)
  365. ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &
  366. CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;
  367. else
  368. return 0;
  369. if (ctl) {
  370. /* EMAC B source */
  371. emacsel_a = false;
  372. ctr_reg = CLKMGR_ALTR_EMACBCTR;
  373. } else {
  374. /* EMAC A source */
  375. emacsel_a = true;
  376. ctr_reg = CLKMGR_ALTR_EMACACTR;
  377. }
  378. reg = CM_REG_READL(plat, ctr_reg);
  379. clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)
  380. >> CLKMGR_ALT_EMACCTR_SRC_OFFSET;
  381. div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)
  382. >> CLKMGR_ALT_EMACCTR_CNT_OFFSET;
  383. switch (clock) {
  384. case CLKMGR_CLKSRC_MAIN:
  385. clock = clk_get_main_vco_clk_hz(plat);
  386. if (emacsel_a) {
  387. clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) &
  388. CLKMGR_CLKCNT_MSK);
  389. } else {
  390. clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) &
  391. CLKMGR_CLKCNT_MSK);
  392. }
  393. break;
  394. case CLKMGR_CLKSRC_PER:
  395. clock = clk_get_per_vco_clk_hz(plat);
  396. if (emacsel_a) {
  397. clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) &
  398. CLKMGR_CLKCNT_MSK);
  399. } else {
  400. clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) &
  401. CLKMGR_CLKCNT_MSK);
  402. }
  403. break;
  404. case CLKMGR_CLKSRC_OSC1:
  405. clock = cm_get_osc_clk_hz();
  406. break;
  407. case CLKMGR_CLKSRC_INTOSC:
  408. clock = cm_get_intosc_clk_hz();
  409. break;
  410. case CLKMGR_CLKSRC_FPGA:
  411. clock = cm_get_fpga_clk_hz();
  412. break;
  413. }
  414. clock /= 1 + div;
  415. return clock;
  416. }
  417. static ulong socfpga_clk_get_rate(struct clk *clk)
  418. {
  419. struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);
  420. switch (clk->id) {
  421. case AGILEX_MPU_CLK:
  422. return clk_get_mpu_clk_hz(plat);
  423. case AGILEX_L4_MAIN_CLK:
  424. return clk_get_l4_main_clk_hz(plat);
  425. case AGILEX_L4_SYS_FREE_CLK:
  426. return clk_get_l4_sys_free_clk_hz(plat);
  427. case AGILEX_L4_MP_CLK:
  428. return clk_get_l4_mp_clk_hz(plat);
  429. case AGILEX_L4_SP_CLK:
  430. return clk_get_l4_sp_clk_hz(plat);
  431. case AGILEX_SDMMC_CLK:
  432. return clk_get_sdmmc_clk_hz(plat);
  433. case AGILEX_EMAC0_CLK:
  434. case AGILEX_EMAC1_CLK:
  435. case AGILEX_EMAC2_CLK:
  436. return clk_get_emac_clk_hz(plat, clk->id);
  437. case AGILEX_USB_CLK:
  438. return clk_get_l4_mp_clk_hz(plat);
  439. default:
  440. return -ENXIO;
  441. }
  442. }
  443. static int socfpga_clk_probe(struct udevice *dev)
  444. {
  445. const struct cm_config *cm_default_cfg = cm_get_default_config();
  446. clk_basic_init(dev, cm_default_cfg);
  447. return 0;
  448. }
  449. static int socfpga_clk_ofdata_to_platdata(struct udevice *dev)
  450. {
  451. struct socfpga_clk_platdata *plat = dev_get_platdata(dev);
  452. fdt_addr_t addr;
  453. addr = dev_read_addr(dev);
  454. if (addr == FDT_ADDR_T_NONE)
  455. return -EINVAL;
  456. plat->regs = (void __iomem *)addr;
  457. return 0;
  458. }
  459. static struct clk_ops socfpga_clk_ops = {
  460. .get_rate = socfpga_clk_get_rate,
  461. };
  462. static const struct udevice_id socfpga_clk_match[] = {
  463. { .compatible = "intel,agilex-clkmgr" },
  464. {}
  465. };
  466. U_BOOT_DRIVER(socfpga_agilex_clk) = {
  467. .name = "clk-agilex",
  468. .id = UCLASS_CLK,
  469. .of_match = socfpga_clk_match,
  470. .ops = &socfpga_clk_ops,
  471. .probe = socfpga_clk_probe,
  472. .ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,
  473. .platdata_auto_alloc_size = sizeof(struct socfpga_clk_platdata),
  474. };