aquantia.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Aquantia PHY drivers
  4. *
  5. * Copyright 2014 Freescale Semiconductor, Inc.
  6. * Copyright 2018 NXP
  7. */
  8. #include <config.h>
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <log.h>
  12. #include <net.h>
  13. #include <phy.h>
  14. #include <linux/bitops.h>
  15. #include <linux/delay.h>
  16. #include <u-boot/crc.h>
  17. #include <malloc.h>
  18. #include <asm/byteorder.h>
  19. #include <fs.h>
  20. #define AQUNTIA_10G_CTL 0x20
  21. #define AQUNTIA_VENDOR_P1 0xc400
  22. #define AQUNTIA_SPEED_LSB_MASK 0x2000
  23. #define AQUNTIA_SPEED_MSB_MASK 0x40
  24. #define AQUANTIA_SYSTEM_INTERFACE_SR 0xe812
  25. #define AQUANTIA_SYSTEM_INTERFACE_SR_READY BIT(0)
  26. #define AQUANTIA_VENDOR_PROVISIONING_REG 0xC441
  27. #define AQUANTIA_FIRMWARE_ID 0x20
  28. #define AQUANTIA_RESERVED_STATUS 0xc885
  29. #define AQUANTIA_FIRMWARE_MAJOR_MASK 0xff00
  30. #define AQUANTIA_FIRMWARE_MINOR_MASK 0xff
  31. #define AQUANTIA_FIRMWARE_BUILD_MASK 0xf0
  32. #define AQUANTIA_USX_AUTONEG_CONTROL_ENA 0x0008
  33. #define AQUANTIA_SI_IN_USE_MASK 0x0078
  34. #define AQUANTIA_SI_USXGMII 0x0018
  35. /* registers in MDIO_MMD_VEND1 region */
  36. #define AQUANTIA_VND1_GLOBAL_SC 0x000
  37. #define AQUANTIA_VND1_GLOBAL_SC_LP BIT(0xb)
  38. #define GLOBAL_FIRMWARE_ID 0x20
  39. #define GLOBAL_FAULT 0xc850
  40. #define GLOBAL_RSTATUS_1 0xc885
  41. #define GLOBAL_ALARM_1 0xcc00
  42. #define SYSTEM_READY_BIT 0x40
  43. #define GLOBAL_STANDARD_CONTROL 0x0
  44. #define SOFT_RESET BIT(15)
  45. #define LOW_POWER BIT(11)
  46. #define MAILBOX_CONTROL 0x0200
  47. #define MAILBOX_EXECUTE BIT(15)
  48. #define MAILBOX_WRITE BIT(14)
  49. #define MAILBOX_RESET_CRC BIT(12)
  50. #define MAILBOX_BUSY BIT(8)
  51. #define MAILBOX_CRC 0x0201
  52. #define MAILBOX_ADDR_MSW 0x0202
  53. #define MAILBOX_ADDR_LSW 0x0203
  54. #define MAILBOX_DATA_MSW 0x0204
  55. #define MAILBOX_DATA_LSW 0x0205
  56. #define UP_CONTROL 0xc001
  57. #define UP_RESET BIT(15)
  58. #define UP_RUN_STALL_OVERRIDE BIT(6)
  59. #define UP_RUN_STALL BIT(0)
  60. #define AQUANTIA_PMA_RX_VENDOR_P1 0xe400
  61. #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK GENMASK(1, 0)
  62. /* MDI reversal configured through registers */
  63. #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG BIT(1)
  64. /* MDI reversal enabled */
  65. #define AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV BIT(0)
  66. /*
  67. * global start rate, the protocol associated with this speed is used by default
  68. * on SI.
  69. */
  70. #define AQUANTIA_VND1_GSTART_RATE 0x31a
  71. #define AQUANTIA_VND1_GSTART_RATE_OFF 0
  72. #define AQUANTIA_VND1_GSTART_RATE_100M 1
  73. #define AQUANTIA_VND1_GSTART_RATE_1G 2
  74. #define AQUANTIA_VND1_GSTART_RATE_10G 3
  75. #define AQUANTIA_VND1_GSTART_RATE_2_5G 4
  76. #define AQUANTIA_VND1_GSTART_RATE_5G 5
  77. /* SYSCFG registers for 100M, 1G, 2.5G, 5G, 10G */
  78. #define AQUANTIA_VND1_GSYSCFG_BASE 0x31b
  79. #define AQUANTIA_VND1_GSYSCFG_100M 0
  80. #define AQUANTIA_VND1_GSYSCFG_1G 1
  81. #define AQUANTIA_VND1_GSYSCFG_2_5G 2
  82. #define AQUANTIA_VND1_GSYSCFG_5G 3
  83. #define AQUANTIA_VND1_GSYSCFG_10G 4
  84. #define AQUANTIA_VND1_SMBUS0 0xc485
  85. #define AQUANTIA_VND1_SMBUS1 0xc495
  86. /* addresses of memory segments in the phy */
  87. #define DRAM_BASE_ADDR 0x3FFE0000
  88. #define IRAM_BASE_ADDR 0x40000000
  89. /* firmware image format constants */
  90. #define VERSION_STRING_SIZE 0x40
  91. #define VERSION_STRING_OFFSET 0x0200
  92. #define HEADER_OFFSET 0x300
  93. /* driver private data */
  94. #define AQUANTIA_NA 0
  95. #define AQUANTIA_GEN1 1
  96. #define AQUANTIA_GEN2 2
  97. #define AQUANTIA_GEN3 3
  98. #pragma pack(1)
  99. struct fw_header {
  100. u8 padding[4];
  101. u8 iram_offset[3];
  102. u8 iram_size[3];
  103. u8 dram_offset[3];
  104. u8 dram_size[3];
  105. };
  106. #pragma pack()
  107. #if defined(CONFIG_PHY_AQUANTIA_UPLOAD_FW)
  108. static int aquantia_read_fw(u8 **fw_addr, size_t *fw_length)
  109. {
  110. loff_t length, read;
  111. int ret;
  112. void *addr = NULL;
  113. *fw_addr = NULL;
  114. *fw_length = 0;
  115. debug("Loading Acquantia microcode from %s %s\n",
  116. CONFIG_PHY_AQUANTIA_FW_PART, CONFIG_PHY_AQUANTIA_FW_NAME);
  117. ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
  118. if (ret < 0)
  119. goto cleanup;
  120. ret = fs_size(CONFIG_PHY_AQUANTIA_FW_NAME, &length);
  121. if (ret < 0)
  122. goto cleanup;
  123. addr = malloc(length);
  124. if (!addr) {
  125. ret = -ENOMEM;
  126. goto cleanup;
  127. }
  128. ret = fs_set_blk_dev("mmc", CONFIG_PHY_AQUANTIA_FW_PART, FS_TYPE_ANY);
  129. if (ret < 0)
  130. goto cleanup;
  131. ret = fs_read(CONFIG_PHY_AQUANTIA_FW_NAME, (ulong)addr, 0, length,
  132. &read);
  133. if (ret < 0)
  134. goto cleanup;
  135. *fw_addr = addr;
  136. *fw_length = length;
  137. debug("Found Acquantia microcode.\n");
  138. cleanup:
  139. if (ret < 0) {
  140. printf("loading firmware file %s %s failed with error %d\n",
  141. CONFIG_PHY_AQUANTIA_FW_PART,
  142. CONFIG_PHY_AQUANTIA_FW_NAME, ret);
  143. free(addr);
  144. }
  145. return ret;
  146. }
  147. /* load data into the phy's memory */
  148. static int aquantia_load_memory(struct phy_device *phydev, u32 addr,
  149. const u8 *data, size_t len)
  150. {
  151. size_t pos;
  152. u16 crc = 0, up_crc;
  153. phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL, MAILBOX_RESET_CRC);
  154. phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_MSW, addr >> 16);
  155. phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_ADDR_LSW, addr & 0xfffc);
  156. for (pos = 0; pos < len; pos += min(sizeof(u32), len - pos)) {
  157. u32 word = 0;
  158. memcpy(&word, &data[pos], min(sizeof(u32), len - pos));
  159. phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_MSW,
  160. (word >> 16));
  161. phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_DATA_LSW,
  162. word & 0xffff);
  163. phy_write(phydev, MDIO_MMD_VEND1, MAILBOX_CONTROL,
  164. MAILBOX_EXECUTE | MAILBOX_WRITE);
  165. /* keep a big endian CRC to match the phy processor */
  166. word = cpu_to_be32(word);
  167. crc = crc16_ccitt(crc, (u8 *)&word, sizeof(word));
  168. }
  169. up_crc = phy_read(phydev, MDIO_MMD_VEND1, MAILBOX_CRC);
  170. if (crc != up_crc) {
  171. printf("%s crc mismatch: calculated 0x%04hx phy 0x%04hx\n",
  172. phydev->dev->name, crc, up_crc);
  173. return -EINVAL;
  174. }
  175. return 0;
  176. }
  177. static u32 unpack_u24(const u8 *data)
  178. {
  179. return (data[2] << 16) + (data[1] << 8) + data[0];
  180. }
  181. static int aquantia_upload_firmware(struct phy_device *phydev)
  182. {
  183. int ret;
  184. u8 *addr = NULL;
  185. size_t fw_length = 0;
  186. u16 calculated_crc, read_crc;
  187. char version[VERSION_STRING_SIZE];
  188. u32 primary_offset, iram_offset, iram_size, dram_offset, dram_size;
  189. const struct fw_header *header;
  190. ret = aquantia_read_fw(&addr, &fw_length);
  191. if (ret != 0)
  192. return ret;
  193. read_crc = (addr[fw_length - 2] << 8) | addr[fw_length - 1];
  194. calculated_crc = crc16_ccitt(0, addr, fw_length - 2);
  195. if (read_crc != calculated_crc) {
  196. printf("%s bad firmware crc: file 0x%04x calculated 0x%04x\n",
  197. phydev->dev->name, read_crc, calculated_crc);
  198. ret = -EINVAL;
  199. goto done;
  200. }
  201. /* Find the DRAM and IRAM sections within the firmware file. */
  202. primary_offset = ((addr[9] & 0xf) << 8 | addr[8]) << 12;
  203. header = (struct fw_header *)&addr[primary_offset + HEADER_OFFSET];
  204. iram_offset = primary_offset + unpack_u24(header->iram_offset);
  205. iram_size = unpack_u24(header->iram_size);
  206. dram_offset = primary_offset + unpack_u24(header->dram_offset);
  207. dram_size = unpack_u24(header->dram_size);
  208. debug("primary %d iram offset=%d size=%d dram offset=%d size=%d\n",
  209. primary_offset, iram_offset, iram_size, dram_offset, dram_size);
  210. strlcpy(version, (char *)&addr[dram_offset + VERSION_STRING_OFFSET],
  211. VERSION_STRING_SIZE);
  212. printf("%s loading firmare version '%s'\n", phydev->dev->name, version);
  213. /* stall the microcprocessor */
  214. phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
  215. UP_RUN_STALL | UP_RUN_STALL_OVERRIDE);
  216. debug("loading dram 0x%08x from offset=%d size=%d\n",
  217. DRAM_BASE_ADDR, dram_offset, dram_size);
  218. ret = aquantia_load_memory(phydev, DRAM_BASE_ADDR, &addr[dram_offset],
  219. dram_size);
  220. if (ret != 0)
  221. goto done;
  222. debug("loading iram 0x%08x from offset=%d size=%d\n",
  223. IRAM_BASE_ADDR, iram_offset, iram_size);
  224. ret = aquantia_load_memory(phydev, IRAM_BASE_ADDR, &addr[iram_offset],
  225. iram_size);
  226. if (ret != 0)
  227. goto done;
  228. /* make sure soft reset and low power mode are clear */
  229. phy_write(phydev, MDIO_MMD_VEND1, GLOBAL_STANDARD_CONTROL, 0);
  230. /* Release the microprocessor. UP_RESET must be held for 100 usec. */
  231. phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL,
  232. UP_RUN_STALL | UP_RUN_STALL_OVERRIDE | UP_RESET);
  233. udelay(100);
  234. phy_write(phydev, MDIO_MMD_VEND1, UP_CONTROL, UP_RUN_STALL_OVERRIDE);
  235. printf("%s firmare loading done.\n", phydev->dev->name);
  236. done:
  237. free(addr);
  238. return ret;
  239. }
  240. #else
  241. static int aquantia_upload_firmware(struct phy_device *phydev)
  242. {
  243. printf("ERROR %s firmware loading disabled.\n", phydev->dev->name);
  244. return -1;
  245. }
  246. #endif
  247. struct {
  248. u16 syscfg;
  249. int cnt;
  250. u16 start_rate;
  251. } aquantia_syscfg[PHY_INTERFACE_MODE_COUNT] = {
  252. [PHY_INTERFACE_MODE_SGMII] = {0x04b, AQUANTIA_VND1_GSYSCFG_1G,
  253. AQUANTIA_VND1_GSTART_RATE_1G},
  254. [PHY_INTERFACE_MODE_SGMII_2500] = {0x144, AQUANTIA_VND1_GSYSCFG_2_5G,
  255. AQUANTIA_VND1_GSTART_RATE_2_5G},
  256. [PHY_INTERFACE_MODE_XFI] = {0x100, AQUANTIA_VND1_GSYSCFG_10G,
  257. AQUANTIA_VND1_GSTART_RATE_10G},
  258. [PHY_INTERFACE_MODE_USXGMII] = {0x080, AQUANTIA_VND1_GSYSCFG_10G,
  259. AQUANTIA_VND1_GSTART_RATE_10G},
  260. };
  261. static int aquantia_set_proto(struct phy_device *phydev,
  262. phy_interface_t interface)
  263. {
  264. int i;
  265. if (!aquantia_syscfg[interface].cnt)
  266. return 0;
  267. /* set the default rate to enable the SI link */
  268. phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
  269. aquantia_syscfg[interface].start_rate);
  270. /* set selected protocol for all relevant line side link speeds */
  271. for (i = 0; i <= aquantia_syscfg[interface].cnt; i++)
  272. phy_write(phydev, MDIO_MMD_VEND1,
  273. AQUANTIA_VND1_GSYSCFG_BASE + i,
  274. aquantia_syscfg[interface].syscfg);
  275. return 0;
  276. }
  277. static int aquantia_dts_config(struct phy_device *phydev)
  278. {
  279. #ifdef CONFIG_DM_ETH
  280. ofnode node = phydev->node;
  281. u32 prop;
  282. u16 reg;
  283. /* this code only works on gen2 and gen3 PHYs */
  284. if (phydev->drv->data != AQUANTIA_GEN2 &&
  285. phydev->drv->data != AQUANTIA_GEN3)
  286. return -ENOTSUPP;
  287. if (!ofnode_valid(node))
  288. return 0;
  289. if (!ofnode_read_u32(node, "mdi-reversal", &prop)) {
  290. debug("mdi-reversal = %d\n", (int)prop);
  291. reg = phy_read(phydev, MDIO_MMD_PMAPMD,
  292. AQUANTIA_PMA_RX_VENDOR_P1);
  293. reg &= ~AQUANTIA_PMA_RX_VENDOR_P1_MDI_MSK;
  294. reg |= AQUANTIA_PMA_RX_VENDOR_P1_MDI_CFG;
  295. reg |= prop ? AQUANTIA_PMA_RX_VENDOR_P1_MDI_REV : 0;
  296. phy_write(phydev, MDIO_MMD_PMAPMD, AQUANTIA_PMA_RX_VENDOR_P1,
  297. reg);
  298. }
  299. if (!ofnode_read_u32(node, "smb-addr", &prop)) {
  300. debug("smb-addr = %x\n", (int)prop);
  301. /*
  302. * there are two addresses here, normally just one bus would
  303. * be in use so we're setting both regs using the same DT
  304. * property.
  305. */
  306. phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS0,
  307. (u16)(prop << 1));
  308. phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_SMBUS1,
  309. (u16)(prop << 1));
  310. }
  311. #endif
  312. return 0;
  313. }
  314. static bool aquantia_link_is_up(struct phy_device *phydev)
  315. {
  316. u16 reg, regmask;
  317. int devad, regnum;
  318. /*
  319. * On Gen 2 and 3 we have a bit that indicates that both system and
  320. * line side are ready for data, use that if possible.
  321. */
  322. if (phydev->drv->data == AQUANTIA_GEN2 ||
  323. phydev->drv->data == AQUANTIA_GEN3) {
  324. devad = MDIO_MMD_PHYXS;
  325. regnum = AQUANTIA_SYSTEM_INTERFACE_SR;
  326. regmask = AQUANTIA_SYSTEM_INTERFACE_SR_READY;
  327. } else {
  328. devad = MDIO_MMD_AN;
  329. regnum = MDIO_STAT1;
  330. regmask = MDIO_AN_STAT1_COMPLETE;
  331. }
  332. /* the register should be latched, do a double read */
  333. phy_read(phydev, devad, regnum);
  334. reg = phy_read(phydev, devad, regnum);
  335. return !!(reg & regmask);
  336. }
  337. int aquantia_config(struct phy_device *phydev)
  338. {
  339. int interface = phydev->interface;
  340. u32 val, id, rstatus, fault;
  341. u32 reg_val1 = 0;
  342. int num_retries = 5;
  343. int usx_an = 0;
  344. /*
  345. * check if the system is out of reset and init sequence completed.
  346. * chip-wide reset for gen1 quad phys takes longer
  347. */
  348. while (--num_retries) {
  349. rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_ALARM_1);
  350. if (rstatus & SYSTEM_READY_BIT)
  351. break;
  352. mdelay(10);
  353. }
  354. id = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FIRMWARE_ID);
  355. rstatus = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_RSTATUS_1);
  356. fault = phy_read(phydev, MDIO_MMD_VEND1, GLOBAL_FAULT);
  357. if (id != 0)
  358. debug("%s running firmware version %X.%X.%X\n",
  359. phydev->dev->name, (id >> 8), id & 0xff,
  360. (rstatus >> 4) & 0xf);
  361. if (fault != 0)
  362. printf("%s fault 0x%04x detected\n", phydev->dev->name, fault);
  363. if (id == 0 || fault != 0) {
  364. int ret;
  365. ret = aquantia_upload_firmware(phydev);
  366. if (ret != 0)
  367. return ret;
  368. }
  369. /*
  370. * for backward compatibility convert XGMII into either XFI or USX based
  371. * on FW config
  372. */
  373. if (interface == PHY_INTERFACE_MODE_XGMII) {
  374. debug("use XFI or USXGMII SI protos, XGMII is not valid\n");
  375. reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
  376. AQUANTIA_SYSTEM_INTERFACE_SR);
  377. if ((reg_val1 & AQUANTIA_SI_IN_USE_MASK) == AQUANTIA_SI_USXGMII)
  378. interface = PHY_INTERFACE_MODE_USXGMII;
  379. else
  380. interface = PHY_INTERFACE_MODE_XFI;
  381. }
  382. /*
  383. * if link is up already we can just use it, otherwise configure
  384. * the protocols in the PHY. If link is down set the system
  385. * interface protocol to use based on phydev->interface
  386. */
  387. if (!aquantia_link_is_up(phydev) &&
  388. (phydev->drv->data == AQUANTIA_GEN2 ||
  389. phydev->drv->data == AQUANTIA_GEN3)) {
  390. /* set PHY in low power mode so we can configure protocols */
  391. phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC,
  392. AQUANTIA_VND1_GLOBAL_SC_LP);
  393. mdelay(10);
  394. /* configure protocol based on phydev->interface */
  395. aquantia_set_proto(phydev, interface);
  396. /* apply custom configuration based on DT */
  397. aquantia_dts_config(phydev);
  398. /* wake PHY back up */
  399. phy_write(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
  400. mdelay(10);
  401. }
  402. val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
  403. switch (interface) {
  404. case PHY_INTERFACE_MODE_SGMII:
  405. /* 1000BASE-T mode */
  406. phydev->advertising = SUPPORTED_1000baseT_Full;
  407. phydev->supported = phydev->advertising;
  408. val = (val & ~AQUNTIA_SPEED_LSB_MASK) | AQUNTIA_SPEED_MSB_MASK;
  409. phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
  410. break;
  411. case PHY_INTERFACE_MODE_USXGMII:
  412. usx_an = 1;
  413. /* FALLTHROUGH */
  414. case PHY_INTERFACE_MODE_XFI:
  415. /* 10GBASE-T mode */
  416. phydev->advertising = SUPPORTED_10000baseT_Full;
  417. phydev->supported = phydev->advertising;
  418. if (!(val & AQUNTIA_SPEED_LSB_MASK) ||
  419. !(val & AQUNTIA_SPEED_MSB_MASK))
  420. phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR,
  421. AQUNTIA_SPEED_LSB_MASK |
  422. AQUNTIA_SPEED_MSB_MASK);
  423. /* If SI is USXGMII then start USXGMII autoneg */
  424. reg_val1 = phy_read(phydev, MDIO_MMD_PHYXS,
  425. AQUANTIA_VENDOR_PROVISIONING_REG);
  426. if (usx_an) {
  427. reg_val1 |= AQUANTIA_USX_AUTONEG_CONTROL_ENA;
  428. debug("%s: system interface USXGMII\n",
  429. phydev->dev->name);
  430. } else {
  431. reg_val1 &= ~AQUANTIA_USX_AUTONEG_CONTROL_ENA;
  432. debug("%s: system interface XFI\n",
  433. phydev->dev->name);
  434. }
  435. phy_write(phydev, MDIO_MMD_PHYXS,
  436. AQUANTIA_VENDOR_PROVISIONING_REG, reg_val1);
  437. break;
  438. case PHY_INTERFACE_MODE_SGMII_2500:
  439. /* 2.5GBASE-T mode */
  440. phydev->advertising = SUPPORTED_1000baseT_Full;
  441. phydev->supported = phydev->advertising;
  442. phy_write(phydev, MDIO_MMD_AN, AQUNTIA_10G_CTL, 1);
  443. phy_write(phydev, MDIO_MMD_AN, AQUNTIA_VENDOR_P1, 0x9440);
  444. break;
  445. case PHY_INTERFACE_MODE_MII:
  446. /* 100BASE-TX mode */
  447. phydev->advertising = SUPPORTED_100baseT_Full;
  448. phydev->supported = phydev->advertising;
  449. val = (val & ~AQUNTIA_SPEED_MSB_MASK) | AQUNTIA_SPEED_LSB_MASK;
  450. phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val);
  451. break;
  452. };
  453. val = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_RESERVED_STATUS);
  454. reg_val1 = phy_read(phydev, MDIO_MMD_VEND1, AQUANTIA_FIRMWARE_ID);
  455. debug("%s: %s Firmware Version %x.%x.%x\n", phydev->dev->name,
  456. phydev->drv->name,
  457. (reg_val1 & AQUANTIA_FIRMWARE_MAJOR_MASK) >> 8,
  458. reg_val1 & AQUANTIA_FIRMWARE_MINOR_MASK,
  459. (val & AQUANTIA_FIRMWARE_BUILD_MASK) >> 4);
  460. return 0;
  461. }
  462. int aquantia_startup(struct phy_device *phydev)
  463. {
  464. u32 reg, speed;
  465. int i = 0;
  466. phydev->duplex = DUPLEX_FULL;
  467. /* if the AN is still in progress, wait till timeout. */
  468. if (!aquantia_link_is_up(phydev)) {
  469. printf("%s Waiting for PHY auto negotiation to complete",
  470. phydev->dev->name);
  471. do {
  472. udelay(1000);
  473. if ((i++ % 500) == 0)
  474. printf(".");
  475. } while (!aquantia_link_is_up(phydev) &&
  476. i < (4 * PHY_ANEG_TIMEOUT));
  477. if (i > PHY_ANEG_TIMEOUT)
  478. printf(" TIMEOUT !\n");
  479. }
  480. /* Read twice because link state is latched and a
  481. * read moves the current state into the register */
  482. phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
  483. reg = phy_read(phydev, MDIO_MMD_AN, MDIO_STAT1);
  484. if (reg < 0 || !(reg & MDIO_STAT1_LSTATUS))
  485. phydev->link = 0;
  486. else
  487. phydev->link = 1;
  488. speed = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR);
  489. if (speed & AQUNTIA_SPEED_MSB_MASK) {
  490. if (speed & AQUNTIA_SPEED_LSB_MASK)
  491. phydev->speed = SPEED_10000;
  492. else
  493. phydev->speed = SPEED_1000;
  494. } else {
  495. if (speed & AQUNTIA_SPEED_LSB_MASK)
  496. phydev->speed = SPEED_100;
  497. else
  498. phydev->speed = SPEED_10;
  499. }
  500. return 0;
  501. }
  502. struct phy_driver aq1202_driver = {
  503. .name = "Aquantia AQ1202",
  504. .uid = 0x3a1b445,
  505. .mask = 0xfffffff0,
  506. .features = PHY_10G_FEATURES,
  507. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
  508. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  509. MDIO_MMD_VEND1),
  510. .config = &aquantia_config,
  511. .startup = &aquantia_startup,
  512. .shutdown = &gen10g_shutdown,
  513. };
  514. struct phy_driver aq2104_driver = {
  515. .name = "Aquantia AQ2104",
  516. .uid = 0x3a1b460,
  517. .mask = 0xfffffff0,
  518. .features = PHY_10G_FEATURES,
  519. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
  520. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  521. MDIO_MMD_VEND1),
  522. .config = &aquantia_config,
  523. .startup = &aquantia_startup,
  524. .shutdown = &gen10g_shutdown,
  525. };
  526. struct phy_driver aqr105_driver = {
  527. .name = "Aquantia AQR105",
  528. .uid = 0x3a1b4a2,
  529. .mask = 0xfffffff0,
  530. .features = PHY_10G_FEATURES,
  531. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
  532. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  533. MDIO_MMD_VEND1),
  534. .config = &aquantia_config,
  535. .startup = &aquantia_startup,
  536. .shutdown = &gen10g_shutdown,
  537. .data = AQUANTIA_GEN1,
  538. };
  539. struct phy_driver aqr106_driver = {
  540. .name = "Aquantia AQR106",
  541. .uid = 0x3a1b4d0,
  542. .mask = 0xfffffff0,
  543. .features = PHY_10G_FEATURES,
  544. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
  545. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  546. MDIO_MMD_VEND1),
  547. .config = &aquantia_config,
  548. .startup = &aquantia_startup,
  549. .shutdown = &gen10g_shutdown,
  550. };
  551. struct phy_driver aqr107_driver = {
  552. .name = "Aquantia AQR107",
  553. .uid = 0x3a1b4e0,
  554. .mask = 0xfffffff0,
  555. .features = PHY_10G_FEATURES,
  556. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
  557. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  558. MDIO_MMD_VEND1),
  559. .config = &aquantia_config,
  560. .startup = &aquantia_startup,
  561. .shutdown = &gen10g_shutdown,
  562. .data = AQUANTIA_GEN2,
  563. };
  564. struct phy_driver aqr112_driver = {
  565. .name = "Aquantia AQR112",
  566. .uid = 0x3a1b660,
  567. .mask = 0xfffffff0,
  568. .features = PHY_10G_FEATURES,
  569. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
  570. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  571. MDIO_MMD_VEND1),
  572. .config = &aquantia_config,
  573. .startup = &aquantia_startup,
  574. .shutdown = &gen10g_shutdown,
  575. .data = AQUANTIA_GEN3,
  576. };
  577. struct phy_driver aqr113c_driver = {
  578. .name = "Aquantia AQR113C",
  579. .uid = 0x31c31c12,
  580. .mask = 0xfffffff0,
  581. .features = PHY_10G_FEATURES,
  582. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
  583. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  584. MDIO_MMD_VEND1),
  585. .config = &aquantia_config,
  586. .startup = &aquantia_startup,
  587. .shutdown = &gen10g_shutdown,
  588. .data = AQUANTIA_GEN3,
  589. };
  590. struct phy_driver aqr405_driver = {
  591. .name = "Aquantia AQR405",
  592. .uid = 0x3a1b4b2,
  593. .mask = 0xfffffff0,
  594. .features = PHY_10G_FEATURES,
  595. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS|
  596. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  597. MDIO_MMD_VEND1),
  598. .config = &aquantia_config,
  599. .startup = &aquantia_startup,
  600. .shutdown = &gen10g_shutdown,
  601. .data = AQUANTIA_GEN1,
  602. };
  603. struct phy_driver aqr412_driver = {
  604. .name = "Aquantia AQR412",
  605. .uid = 0x3a1b710,
  606. .mask = 0xfffffff0,
  607. .features = PHY_10G_FEATURES,
  608. .mmds = (MDIO_MMD_PMAPMD | MDIO_MMD_PCS |
  609. MDIO_MMD_PHYXS | MDIO_MMD_AN |
  610. MDIO_MMD_VEND1),
  611. .config = &aquantia_config,
  612. .startup = &aquantia_startup,
  613. .shutdown = &gen10g_shutdown,
  614. .data = AQUANTIA_GEN3,
  615. };
  616. int phy_aquantia_init(void)
  617. {
  618. phy_register(&aq1202_driver);
  619. phy_register(&aq2104_driver);
  620. phy_register(&aqr105_driver);
  621. phy_register(&aqr106_driver);
  622. phy_register(&aqr107_driver);
  623. phy_register(&aqr112_driver);
  624. phy_register(&aqr113c_driver);
  625. phy_register(&aqr405_driver);
  626. phy_register(&aqr412_driver);
  627. return 0;
  628. }