fsl-lx2160a.dtsi 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP lx2160a SOC common device tree source
  4. *
  5. * Copyright 2018-2020 NXP
  6. *
  7. */
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. / {
  10. compatible = "fsl,lx2160a";
  11. interrupt-parent = <&gic>;
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. memory@80000000 {
  15. device_type = "memory";
  16. reg = <0x00000000 0x80000000 0 0x80000000>;
  17. /* DRAM space - 1, size : 2 GB DRAM */
  18. };
  19. sysclk: sysclk {
  20. compatible = "fixed-clock";
  21. #clock-cells = <0>;
  22. clock-frequency = <100000000>;
  23. clock-output-names = "sysclk";
  24. };
  25. clockgen: clocking@1300000 {
  26. compatible = "fsl,ls2080a-clockgen";
  27. reg = <0 0x1300000 0 0xa0000>;
  28. #clock-cells = <2>;
  29. clocks = <&sysclk>;
  30. };
  31. gic: interrupt-controller@6000000 {
  32. compatible = "arm,gic-v3";
  33. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  34. <0x0 0x06200000 0 0x100000>; /* GICR */
  35. #interrupt-cells = <3>;
  36. interrupt-controller;
  37. interrupts = <1 9 0x4>;
  38. };
  39. gic_lpi_base: syscon@0x80000000 {
  40. compatible = "gic-lpi-base";
  41. reg = <0x0 0x80000000 0x0 0x200000>;
  42. max-gic-redistributors = <16>;
  43. };
  44. timer {
  45. compatible = "arm,armv8-timer";
  46. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  47. <1 14 0x8>, /* Physical NS PPI, active-low */
  48. <1 11 0x8>, /* Virtual PPI, active-low */
  49. <1 10 0x8>; /* Hypervisor PPI, active-low */
  50. };
  51. fspi: flexspi@20c0000 {
  52. compatible = "nxp,lx2160a-fspi";
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. reg = <0x0 0x20c0000 0x0 0x10000>,
  56. <0x0 0x20000000 0x0 0x10000000>;
  57. reg-names = "fspi_base", "fspi_mmap";
  58. clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  59. clock-names = "fspi_en", "fspi";
  60. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  61. status = "disabled";
  62. };
  63. i2c0: i2c@2000000 {
  64. compatible = "fsl,vf610-i2c";
  65. #address-cells = <1>;
  66. #size-cells = <0>;
  67. reg = <0x0 0x2000000 0x0 0x10000>;
  68. interrupts = <0 34 4>;
  69. scl-gpio = <&gpio2 15 0>;
  70. status = "disabled";
  71. };
  72. i2c1: i2c@2010000 {
  73. compatible = "fsl,vf610-i2c";
  74. #address-cells = <1>;
  75. #size-cells = <0>;
  76. reg = <0x0 0x2010000 0x0 0x10000>;
  77. interrupts = <0 34 4>;
  78. status = "disabled";
  79. };
  80. i2c2: i2c@2020000 {
  81. compatible = "fsl,vf610-i2c";
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. reg = <0x0 0x2020000 0x0 0x10000>;
  85. interrupts = <0 35 4>;
  86. status = "disabled";
  87. };
  88. i2c3: i2c@2030000 {
  89. compatible = "fsl,vf610-i2c";
  90. #address-cells = <1>;
  91. #size-cells = <0>;
  92. reg = <0x0 0x2030000 0x0 0x10000>;
  93. interrupts = <0 35 4>;
  94. status = "disabled";
  95. };
  96. i2c4: i2c@2040000 {
  97. compatible = "fsl,vf610-i2c";
  98. #address-cells = <1>;
  99. #size-cells = <0>;
  100. reg = <0x0 0x2040000 0x0 0x10000>;
  101. interrupts = <0 74 4>;
  102. scl-gpio = <&gpio2 16 0>;
  103. status = "disabled";
  104. };
  105. i2c5: i2c@2050000 {
  106. compatible = "fsl,vf610-i2c";
  107. #address-cells = <1>;
  108. #size-cells = <0>;
  109. reg = <0x0 0x2050000 0x0 0x10000>;
  110. interrupts = <0 74 4>;
  111. status = "disabled";
  112. };
  113. i2c6: i2c@2060000 {
  114. compatible = "fsl,vf610-i2c";
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. reg = <0x0 0x2060000 0x0 0x10000>;
  118. interrupts = <0 75 4>;
  119. status = "disabled";
  120. };
  121. i2c7: i2c@2070000 {
  122. compatible = "fsl,vf610-i2c";
  123. #address-cells = <1>;
  124. #size-cells = <0>;
  125. reg = <0x0 0x2070000 0x0 0x10000>;
  126. interrupts = <0 75 4>;
  127. status = "disabled";
  128. };
  129. uart0: serial@21c0000 {
  130. compatible = "arm,pl011";
  131. reg = <0x0 0x21c0000 0x0 0x1000>;
  132. clocks = <&clockgen 4 0>;
  133. status = "disabled";
  134. };
  135. uart1: serial@21d0000 {
  136. compatible = "arm,pl011";
  137. reg = <0x0 0x21d0000 0x0 0x1000>;
  138. clocks = <&clockgen 4 0>;
  139. status = "disabled";
  140. };
  141. uart2: serial@21e0000 {
  142. compatible = "arm,pl011";
  143. reg = <0x0 0x21e0000 0x0 0x1000>;
  144. clocks = <&clockgen 4 0>;
  145. status = "disabled";
  146. };
  147. uart3: serial@21f0000 {
  148. compatible = "arm,pl011";
  149. reg = <0x0 0x21f0000 0x0 0x1000>;
  150. clocks = <&clockgen 4 0>;
  151. status = "disabled";
  152. };
  153. dspi0: dspi@2100000 {
  154. compatible = "fsl,vf610-dspi";
  155. #address-cells = <1>;
  156. #size-cells = <0>;
  157. reg = <0x0 0x2100000 0x0 0x10000>;
  158. interrupts = <0 26 0x4>; /* Level high type */
  159. num-cs = <6>;
  160. };
  161. dspi1: dspi@2110000 {
  162. compatible = "fsl,vf610-dspi";
  163. #address-cells = <1>;
  164. #size-cells = <0>;
  165. reg = <0x0 0x2110000 0x0 0x10000>;
  166. interrupts = <0 26 0x4>; /* Level high type */
  167. num-cs = <6>;
  168. };
  169. dspi2: dspi@2120000 {
  170. compatible = "fsl,vf610-dspi";
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. reg = <0x0 0x2120000 0x0 0x10000>;
  174. interrupts = <0 241 0x4>; /* Level high type */
  175. num-cs = <6>;
  176. };
  177. gpio0: gpio@2300000 {
  178. compatible = "fsl,qoriq-gpio";
  179. reg = <0x0 0x2300000 0x0 0x10000>;
  180. interrupts = <0 36 4>;
  181. gpio-controller;
  182. little-endian;
  183. #gpio-cells = <2>;
  184. interrupt-controller;
  185. #interrupt-cells = <2>;
  186. };
  187. gpio1: gpio@2310000 {
  188. compatible = "fsl,qoriq-gpio";
  189. reg = <0x0 0x2310000 0x0 0x10000>;
  190. interrupts = <0 36 4>;
  191. gpio-controller;
  192. little-endian;
  193. #gpio-cells = <2>;
  194. interrupt-controller;
  195. #interrupt-cells = <2>;
  196. };
  197. gpio2: gpio@2320000 {
  198. compatible = "fsl,qoriq-gpio";
  199. reg = <0x0 0x2320000 0x0 0x10000>;
  200. interrupts = <0 37 4>;
  201. gpio-controller;
  202. little-endian;
  203. #gpio-cells = <2>;
  204. interrupt-controller;
  205. #interrupt-cells = <2>;
  206. };
  207. gpio3: gpio@2330000 {
  208. compatible = "fsl,qoriq-gpio";
  209. reg = <0x0 0x2330000 0x0 0x10000>;
  210. interrupts = <0 37 4>;
  211. gpio-controller;
  212. little-endian;
  213. #gpio-cells = <2>;
  214. interrupt-controller;
  215. #interrupt-cells = <2>;
  216. };
  217. watchdog@23a0000 {
  218. compatible = "arm,sbsa-gwdt";
  219. reg = <0x0 0x23a0000 0 0x1000>,
  220. <0x0 0x2390000 0 0x1000>;
  221. timeout-sec = <30>;
  222. };
  223. usb0: usb3@3100000 {
  224. compatible = "fsl,layerscape-dwc3";
  225. reg = <0x0 0x3100000 0x0 0x10000>;
  226. interrupts = <0 80 0x4>; /* Level high type */
  227. dr_mode = "host";
  228. };
  229. usb1: usb3@3110000 {
  230. compatible = "fsl,layerscape-dwc3";
  231. reg = <0x0 0x3110000 0x0 0x10000>;
  232. interrupts = <0 81 0x4>; /* Level high type */
  233. dr_mode = "host";
  234. };
  235. esdhc0: esdhc@2140000 {
  236. compatible = "fsl,esdhc";
  237. reg = <0x0 0x2140000 0x0 0x10000>;
  238. interrupts = <0 28 0x4>; /* Level high type */
  239. clocks = <&clockgen 4 1>;
  240. voltage-ranges = <1800 1800 3300 3300>;
  241. sdhci,auto-cmd12;
  242. little-endian;
  243. bus-width = <4>;
  244. status = "disabled";
  245. };
  246. esdhc1: esdhc@2150000 {
  247. compatible = "fsl,esdhc";
  248. reg = <0x0 0x2150000 0x0 0x10000>;
  249. interrupts = <0 63 0x4>; /* Level high type */
  250. clocks = <&clockgen 4 1>;
  251. voltage-ranges = <1800 1800 3300 3300>;
  252. sdhci,auto-cmd12;
  253. non-removable;
  254. little-endian;
  255. bus-width = <4>;
  256. status = "disabled";
  257. };
  258. sata0: sata@3200000 {
  259. compatible = "fsl,ls2080a-ahci";
  260. reg = <0x0 0x3200000 0x0 0x10000>;
  261. interrupts = <0 133 4>;
  262. clocks = <&clockgen 4 3>;
  263. status = "disabled";
  264. };
  265. sata1: sata@3210000 {
  266. compatible = "fsl,ls2080a-ahci";
  267. reg = <0x0 0x3210000 0x0 0x10000>;
  268. interrupts = <0 136 4>;
  269. clocks = <&clockgen 4 3>;
  270. status = "disabled";
  271. };
  272. sata2: sata@3220000 {
  273. compatible = "fsl,ls2080a-ahci";
  274. reg = <0x0 0x3220000 0x0 0x10000>;
  275. interrupts = <0 97 4>;
  276. clocks = <&clockgen 4 3>;
  277. status = "disabled";
  278. };
  279. sata3: sata@3230000 {
  280. compatible = "fsl,ls2080a-ahci";
  281. reg = <0x0 0x3230000 0x0 0x10000>;
  282. interrupts = <0 100 4>;
  283. clocks = <&clockgen 4 3>;
  284. status = "disabled";
  285. };
  286. pcie@3400000 {
  287. compatible = "fsl,lx2160a-pcie";
  288. reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
  289. 0x00 0x03480000 0x0 0x40000 /* LUT registers */
  290. 0x00 0x034c0000 0x0 0x40000 /* PF control registers */
  291. 0x80 0x00000000 0x0 0x2000>; /* configuration space */
  292. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  293. #address-cells = <3>;
  294. #size-cells = <2>;
  295. device_type = "pci";
  296. bus-range = <0x0 0xff>;
  297. ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
  298. 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  299. };
  300. pcie@3500000 {
  301. compatible = "fsl,lx2160a-pcie";
  302. reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
  303. 0x00 0x03580000 0x0 0x40000 /* LUT registers */
  304. 0x00 0x035c0000 0x0 0x40000 /* PF control registers */
  305. 0x88 0x00000000 0x0 0x2000>; /* configuration space */
  306. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  307. #address-cells = <3>;
  308. #size-cells = <2>;
  309. device_type = "pci";
  310. num-lanes = <2>;
  311. bus-range = <0x0 0xff>;
  312. ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
  313. 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  314. };
  315. pcie@3600000 {
  316. compatible = "fsl,lx2160a-pcie";
  317. reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
  318. 0x00 0x03680000 0x0 0x40000 /* LUT registers */
  319. 0x00 0x036c0000 0x0 0x40000 /* PF control registers */
  320. 0x90 0x00000000 0x0 0x2000>; /* configuration space */
  321. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  322. #address-cells = <3>;
  323. #size-cells = <2>;
  324. device_type = "pci";
  325. bus-range = <0x0 0xff>;
  326. ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000 /* downstream I/O */
  327. 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  328. };
  329. pcie@3700000 {
  330. compatible = "fsl,lx2160a-pcie";
  331. reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
  332. 0x00 0x03780000 0x0 0x40000 /* LUT registers */
  333. 0x00 0x037c0000 0x0 0x40000 /* PF control registers */
  334. 0x98 0x00000000 0x0 0x2000>; /* configuration space */
  335. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  336. #address-cells = <3>;
  337. #size-cells = <2>;
  338. device_type = "pci";
  339. bus-range = <0x0 0xff>;
  340. ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000 /* downstream I/O */
  341. 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  342. };
  343. pcie@3800000 {
  344. compatible = "fsl,lx2160a-pcie";
  345. reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
  346. 0x00 0x03880000 0x0 0x40000 /* LUT registers */
  347. 0x00 0x038c0000 0x0 0x40000 /* PF control registers */
  348. 0xa0 0x00000000 0x0 0x2000>; /* configuration space */
  349. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  350. #address-cells = <3>;
  351. #size-cells = <2>;
  352. device_type = "pci";
  353. bus-range = <0x0 0xff>;
  354. ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000 /* downstream I/O */
  355. 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  356. };
  357. pcie@3900000 {
  358. compatible = "fsl,lx2160a-pcie";
  359. reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
  360. 0x00 0x03980000 0x0 0x40000 /* LUT registers */
  361. 0x00 0x039c0000 0x0 0x40000 /* PF control registers */
  362. 0xa8 0x00000000 0x0 0x2000>; /* configuration space */
  363. reg-names = "ccsr", "lut", "pf_ctrl", "config";
  364. #address-cells = <3>;
  365. #size-cells = <2>;
  366. device_type = "pci";
  367. bus-range = <0x0 0xff>;
  368. ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000 /* downstream I/O */
  369. 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  370. };
  371. fsl_mc: fsl-mc@80c000000 {
  372. compatible = "fsl,qoriq-mc", "simple-mfd";
  373. reg = <0x00000008 0x0c000000 0 0x40>,
  374. <0x00000000 0x08340000 0 0x40000>;
  375. #address-cells = <3>;
  376. #size-cells = <1>;
  377. /*
  378. * Region type 0x0 - MC portals
  379. * Region type 0x1 - QBMAN portals
  380. */
  381. ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
  382. 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
  383. dpmacs {
  384. compatible = "simple-mfd";
  385. #address-cells = <1>;
  386. #size-cells = <0>;
  387. dpmac1: dpmac@1 {
  388. compatible = "fsl,qoriq-mc-dpmac";
  389. reg = <0x1>;
  390. status = "disabled";
  391. };
  392. dpmac2: dpmac@2 {
  393. compatible = "fsl,qoriq-mc-dpmac";
  394. reg = <0x2>;
  395. status = "disabled";
  396. };
  397. dpmac3: dpmac@3 {
  398. compatible = "fsl,qoriq-mc-dpmac";
  399. reg = <0x3>;
  400. status = "disabled";
  401. };
  402. dpmac4: dpmac@4 {
  403. compatible = "fsl,qoriq-mc-dpmac";
  404. reg = <0x4>;
  405. status = "disabled";
  406. };
  407. dpmac5: dpmac@5 {
  408. compatible = "fsl,qoriq-mc-dpmac";
  409. reg = <0x5>;
  410. status = "disabled";
  411. };
  412. dpmac6: dpmac@6 {
  413. compatible = "fsl,qoriq-mc-dpmac";
  414. reg = <0x6>;
  415. status = "disabled";
  416. };
  417. dpmac7: dpmac@7 {
  418. compatible = "fsl,qoriq-mc-dpmac";
  419. reg = <0x7>;
  420. status = "disabled";
  421. };
  422. dpmac8: dpmac@8 {
  423. compatible = "fsl,qoriq-mc-dpmac";
  424. reg = <0x8>;
  425. status = "disabled";
  426. };
  427. dpmac9: dpmac@9 {
  428. compatible = "fsl,qoriq-mc-dpmac";
  429. reg = <0x9>;
  430. status = "disabled";
  431. };
  432. dpmac10: dpmac@a {
  433. compatible = "fsl,qoriq-mc-dpmac";
  434. reg = <0xa>;
  435. status = "disabled";
  436. };
  437. dpmac11: dpmac@b {
  438. compatible = "fsl,qoriq-mc-dpmac";
  439. reg = <0xb>;
  440. status = "disabled";
  441. };
  442. dpmac12: dpmac@c {
  443. compatible = "fsl,qoriq-mc-dpmac";
  444. reg = <0xc>;
  445. status = "disabled";
  446. };
  447. dpmac13: dpmac@d {
  448. compatible = "fsl,qoriq-mc-dpmac";
  449. reg = <0xd>;
  450. status = "disabled";
  451. };
  452. dpmac14: dpmac@e {
  453. compatible = "fsl,qoriq-mc-dpmac";
  454. reg = <0xe>;
  455. status = "disabled";
  456. };
  457. dpmac15: dpmac@f {
  458. compatible = "fsl,qoriq-mc-dpmac";
  459. reg = <0xf>;
  460. status = "disabled";
  461. };
  462. dpmac16: dpmac@10 {
  463. compatible = "fsl,qoriq-mc-dpmac";
  464. reg = <0x10>;
  465. status = "disabled";
  466. };
  467. dpmac17: dpmac@11 {
  468. compatible = "fsl,qoriq-mc-dpmac";
  469. reg = <0x11>;
  470. status = "disabled";
  471. };
  472. dpmac18: dpmac@12 {
  473. compatible = "fsl,qoriq-mc-dpmac";
  474. reg = <0x12>;
  475. status = "disabled";
  476. };
  477. };
  478. };
  479. /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
  480. emdio1: mdio@8b96000 {
  481. compatible = "fsl,ls-mdio";
  482. reg = <0x0 0x8b96000 0x0 0x1000>;
  483. interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  484. #address-cells = <1>;
  485. #size-cells = <0>;
  486. status = "disabled";
  487. };
  488. /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
  489. emdio2: mdio@8b97000 {
  490. compatible = "fsl,ls-mdio";
  491. reg = <0x0 0x8b97000 0x0 0x1000>;
  492. interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
  493. #address-cells = <1>;
  494. #size-cells = <0>;
  495. status = "disabled";
  496. };
  497. firmware {
  498. optee {
  499. compatible = "linaro,optee-tz";
  500. method = "smc";
  501. };
  502. };
  503. };