fsl-ls2080a.dtsi 7.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Freescale ls2080a SOC common device tree source
  4. *
  5. * Copyright 2013-2015 Freescale Semiconductor, Inc.
  6. */
  7. / {
  8. compatible = "fsl,ls2080a";
  9. interrupt-parent = <&gic>;
  10. #address-cells = <2>;
  11. #size-cells = <2>;
  12. memory@80000000 {
  13. device_type = "memory";
  14. reg = <0x00000000 0x80000000 0 0x80000000>;
  15. /* DRAM space - 1, size : 2 GB DRAM */
  16. };
  17. gic: interrupt-controller@6000000 {
  18. compatible = "arm,gic-v3";
  19. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  20. <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  21. #interrupt-cells = <3>;
  22. interrupt-controller;
  23. interrupts = <1 9 0x4>;
  24. };
  25. gic_lpi_base: syscon@0x80000000 {
  26. compatible = "gic-lpi-base";
  27. reg = <0x0 0x80000000 0x0 0x100000>;
  28. max-gic-redistributors = <8>;
  29. };
  30. timer {
  31. compatible = "arm,armv8-timer";
  32. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  33. <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  34. <1 11 0x8>, /* Virtual PPI, active-low */
  35. <1 10 0x8>; /* Hypervisor PPI, active-low */
  36. };
  37. serial0: serial@21c0500 {
  38. device_type = "serial";
  39. compatible = "fsl,ns16550", "ns16550a";
  40. reg = <0x0 0x21c0500 0x0 0x100>;
  41. clock-frequency = <0>; /* Updated by bootloader */
  42. interrupts = <0 32 0x1>; /* edge triggered */
  43. };
  44. serial1: serial@21c0600 {
  45. device_type = "serial";
  46. compatible = "fsl,ns16550", "ns16550a";
  47. reg = <0x0 0x21c0600 0x0 0x100>;
  48. clock-frequency = <0>; /* Updated by bootloader */
  49. interrupts = <0 32 0x1>; /* edge triggered */
  50. };
  51. i2c0: i2c@2000000 {
  52. status = "disabled";
  53. compatible = "fsl,vf610-i2c";
  54. #address-cells = <1>;
  55. #size-cells = <0>;
  56. reg = <0x0 0x2000000 0x0 0x10000>;
  57. interrupts = <0 34 0x4>; /* Level high type */
  58. };
  59. i2c1: i2c@2010000 {
  60. status = "disabled";
  61. compatible = "fsl,vf610-i2c";
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. reg = <0x0 0x2010000 0x0 0x10000>;
  65. interrupts = <0 34 0x4>; /* Level high type */
  66. };
  67. i2c2: i2c@2020000 {
  68. status = "disabled";
  69. compatible = "fsl,vf610-i2c";
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. reg = <0x0 0x2020000 0x0 0x10000>;
  73. interrupts = <0 35 0x4>; /* Level high type */
  74. };
  75. i2c3: i2c@2030000 {
  76. status = "disabled";
  77. compatible = "fsl,vf610-i2c";
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. reg = <0x0 0x2030000 0x0 0x10000>;
  81. interrupts = <0 35 0x4>; /* Level high type */
  82. };
  83. dspi: dspi@2100000 {
  84. compatible = "fsl,vf610-dspi";
  85. #address-cells = <1>;
  86. #size-cells = <0>;
  87. reg = <0x0 0x2100000 0x0 0x10000>;
  88. interrupts = <0 26 0x4>; /* Level high type */
  89. num-cs = <6>;
  90. };
  91. qspi: quadspi@1550000 {
  92. compatible = "fsl,ls2080a-qspi";
  93. #address-cells = <1>;
  94. #size-cells = <0>;
  95. reg = <0x0 0x20c0000 0x0 0x10000>,
  96. <0x0 0x20000000 0x0 0x10000000>;
  97. reg-names = "QuadSPI", "QuadSPI-memory";
  98. status = "disabled";
  99. };
  100. esdhc: esdhc@0 {
  101. compatible = "fsl,esdhc";
  102. reg = <0x0 0x2140000 0x0 0x10000>;
  103. interrupts = <0 28 0x4>; /* Level high type */
  104. little-endian;
  105. bus-width = <4>;
  106. };
  107. usb0: usb3@3100000 {
  108. compatible = "fsl,layerscape-dwc3";
  109. reg = <0x0 0x3100000 0x0 0x10000>;
  110. interrupts = <0 80 0x4>; /* Level high type */
  111. dr_mode = "host";
  112. };
  113. usb1: usb3@3110000 {
  114. compatible = "fsl,layerscape-dwc3";
  115. reg = <0x0 0x3110000 0x0 0x10000>;
  116. interrupts = <0 81 0x4>; /* Level high type */
  117. dr_mode = "host";
  118. };
  119. pcie@3400000 {
  120. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  121. reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
  122. 0x00 0x03480000 0x0 0x80000 /* lut registers */
  123. 0x10 0x00000000 0x0 0x20000>; /* configuration space */
  124. reg-names = "dbi", "lut", "config";
  125. #address-cells = <3>;
  126. #size-cells = <2>;
  127. device_type = "pci";
  128. num-lanes = <4>;
  129. bus-range = <0x0 0xff>;
  130. ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
  131. 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  132. };
  133. pcie@3500000 {
  134. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  135. reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
  136. 0x00 0x03580000 0x0 0x80000 /* lut registers */
  137. 0x12 0x00000000 0x0 0x20000>; /* configuration space */
  138. reg-names = "dbi", "lut", "config";
  139. #address-cells = <3>;
  140. #size-cells = <2>;
  141. device_type = "pci";
  142. num-lanes = <4>;
  143. bus-range = <0x0 0xff>;
  144. ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
  145. 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  146. };
  147. pcie@3600000 {
  148. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  149. reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
  150. 0x00 0x03680000 0x0 0x80000 /* lut registers */
  151. 0x14 0x00000000 0x0 0x20000>; /* configuration space */
  152. reg-names = "dbi", "lut", "config";
  153. #address-cells = <3>;
  154. #size-cells = <2>;
  155. device_type = "pci";
  156. num-lanes = <8>;
  157. bus-range = <0x0 0xff>;
  158. ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
  159. 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  160. };
  161. pcie@3700000 {
  162. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  163. reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
  164. 0x00 0x03780000 0x0 0x80000 /* lut registers */
  165. 0x16 0x00000000 0x0 0x20000>; /* configuration space */
  166. reg-names = "dbi", "lut", "config";
  167. #address-cells = <3>;
  168. #size-cells = <2>;
  169. device_type = "pci";
  170. num-lanes = <4>;
  171. bus-range = <0x0 0xff>;
  172. ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
  173. 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  174. };
  175. sata: sata@3200000 {
  176. compatible = "fsl,ls2080a-ahci";
  177. reg = <0x0 0x3200000 0x0 0x10000>;
  178. interrupts = <0 133 0x4>; /* Level high type */
  179. status = "disabled";
  180. };
  181. fsl_mc: fsl-mc@80c000000 {
  182. compatible = "fsl,qoriq-mc", "simple-mfd";
  183. reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
  184. <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
  185. #address-cells = <3>;
  186. #size-cells = <1>;
  187. /*
  188. * Region type 0x0 - MC portals
  189. * Region type 0x1 - QBMAN portals
  190. */
  191. ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
  192. 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
  193. dpmacs {
  194. compatible = "simple-mfd";
  195. #address-cells = <1>;
  196. #size-cells = <0>;
  197. dpmac1: dpmac@1 {
  198. compatible = "fsl,qoriq-mc-dpmac";
  199. reg = <0x1>;
  200. status = "disabled";
  201. };
  202. dpmac2: dpmac@2 {
  203. compatible = "fsl,qoriq-mc-dpmac";
  204. reg = <0x2>;
  205. status = "disabled";
  206. };
  207. dpmac3: dpmac@3 {
  208. compatible = "fsl,qoriq-mc-dpmac";
  209. reg = <0x3>;
  210. status = "disabled";
  211. };
  212. dpmac4: dpmac@4 {
  213. compatible = "fsl,qoriq-mc-dpmac";
  214. reg = <0x4>;
  215. status = "disabled";
  216. };
  217. dpmac5: dpmac@5 {
  218. compatible = "fsl,qoriq-mc-dpmac";
  219. reg = <0x5>;
  220. status = "disabled";
  221. };
  222. dpmac6: dpmac@6 {
  223. compatible = "fsl,qoriq-mc-dpmac";
  224. reg = <0x6>;
  225. status = "disabled";
  226. };
  227. dpmac7: dpmac@7 {
  228. compatible = "fsl,qoriq-mc-dpmac";
  229. reg = <0x7>;
  230. status = "disabled";
  231. };
  232. dpmac8: dpmac@8 {
  233. compatible = "fsl,qoriq-mc-dpmac";
  234. reg = <0x8>;
  235. status = "disabled";
  236. };
  237. };
  238. };
  239. emdio1: mdio@8B96000 {
  240. compatible = "fsl,ls-mdio";
  241. reg = <0x0 0x8B96000 0x0 0x1000>;
  242. #address-cells = <1>;
  243. #size-cells = <0>;
  244. status = "disabled";
  245. };
  246. emdio2: mdio@8B97000 {
  247. compatible = "fsl,ls-mdio";
  248. reg = <0x0 0x8B97000 0x0 0x1000>;
  249. #address-cells = <1>;
  250. #size-cells = <0>;
  251. status = "disabled";
  252. };
  253. };