fsl-ls1088a.dtsi 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP ls1088a SOC common device tree source
  4. *
  5. * Copyright 2017 NXP
  6. */
  7. / {
  8. compatible = "fsl,ls1088a";
  9. interrupt-parent = <&gic>;
  10. #address-cells = <2>;
  11. #size-cells = <2>;
  12. memory@80000000 {
  13. device_type = "memory";
  14. reg = <0x00000000 0x80000000 0 0x80000000>;
  15. /* DRAM space - 1, size : 2 GB DRAM */
  16. };
  17. gic: interrupt-controller@6000000 {
  18. compatible = "arm,gic-v3";
  19. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  20. <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
  21. #interrupt-cells = <3>;
  22. interrupt-controller;
  23. interrupts = <1 9 0x4>;
  24. };
  25. gic_lpi_base: syscon@0x80000000 {
  26. compatible = "gic-lpi-base";
  27. reg = <0x0 0x80000000 0x0 0x100000>;
  28. max-gic-redistributors = <8>;
  29. };
  30. timer {
  31. compatible = "arm,armv8-timer";
  32. interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
  33. <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
  34. <1 11 0x8>, /* Virtual PPI, active-low */
  35. <1 10 0x8>; /* Hypervisor PPI, active-low */
  36. };
  37. i2c0: i2c@2000000 {
  38. compatible = "fsl,vf610-i2c";
  39. #address-cells = <1>;
  40. #size-cells = <0>;
  41. reg = <0x0 0x2000000 0x0 0x10000>;
  42. interrupts = <0 34 4>;
  43. };
  44. i2c1: i2c@2010000 {
  45. compatible = "fsl,vf610-i2c";
  46. #address-cells = <1>;
  47. #size-cells = <0>;
  48. reg = <0x0 0x2010000 0x0 0x10000>;
  49. interrupts = <0 34 4>;
  50. };
  51. i2c2: i2c@2020000 {
  52. compatible = "fsl,vf610-i2c";
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. reg = <0x0 0x2020000 0x0 0x10000>;
  56. interrupts = <0 35 4>;
  57. };
  58. i2c3: i2c@2030000 {
  59. compatible = "fsl,vf610-i2c";
  60. #address-cells = <1>;
  61. #size-cells = <0>;
  62. reg = <0x0 0x2030000 0x0 0x10000>;
  63. interrupts = <0 35 4>;
  64. };
  65. serial0: serial@21c0500 {
  66. device_type = "serial";
  67. compatible = "fsl,ns16550", "ns16550a";
  68. reg = <0x0 0x21c0500 0x0 0x100>;
  69. clock-frequency = <0>; /* Updated by bootloader */
  70. interrupts = <0 32 0x1>; /* edge triggered */
  71. };
  72. serial1: serial@21c0600 {
  73. device_type = "serial";
  74. compatible = "fsl,ns16550", "ns16550a";
  75. reg = <0x0 0x21c0600 0x0 0x100>;
  76. clock-frequency = <0>; /* Updated by bootloader */
  77. interrupts = <0 32 0x1>; /* edge triggered */
  78. };
  79. dspi: dspi@2100000 {
  80. compatible = "fsl,vf610-dspi";
  81. #address-cells = <1>;
  82. #size-cells = <0>;
  83. reg = <0x0 0x2100000 0x0 0x10000>;
  84. interrupts = <0 26 0x4>; /* Level high type */
  85. num-cs = <6>;
  86. };
  87. qspi: quadspi@1550000 {
  88. compatible = "fsl,ls1088a-qspi";
  89. #address-cells = <1>;
  90. #size-cells = <0>;
  91. reg = <0x0 0x20c0000 0x0 0x10000>,
  92. <0x0 0x20000000 0x0 0x10000000>;
  93. reg-names = "QuadSPI", "QuadSPI-memory";
  94. num-cs = <4>;
  95. };
  96. esdhc: esdhc@2140000 {
  97. compatible = "fsl,esdhc";
  98. reg = <0x0 0x2140000 0x0 0x10000>;
  99. interrupts = <0 28 0x4>; /* Level high type */
  100. little-endian;
  101. bus-width = <4>;
  102. };
  103. ifc: ifc@1530000 {
  104. compatible = "fsl,ifc", "simple-bus";
  105. reg = <0x0 0x2240000 0x0 0x20000>;
  106. interrupts = <0 21 0x4>; /* Level high type */
  107. };
  108. usb0: usb3@3100000 {
  109. compatible = "fsl,layerscape-dwc3";
  110. reg = <0x0 0x3100000 0x0 0x10000>;
  111. interrupts = <0 80 0x4>; /* Level high type */
  112. dr_mode = "host";
  113. };
  114. usb1: usb3@3110000 {
  115. compatible = "fsl,layerscape-dwc3";
  116. reg = <0x0 0x3110000 0x0 0x10000>;
  117. interrupts = <0 81 0x4>; /* Level high type */
  118. dr_mode = "host";
  119. };
  120. pcie@3400000 {
  121. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  122. reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
  123. 0x00 0x03480000 0x0 0x80000 /* lut registers */
  124. 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
  125. 0x20 0x00000000 0x0 0x20000>; /* configuration space */
  126. reg-names = "dbi", "lut", "ctrl", "config";
  127. #address-cells = <3>;
  128. #size-cells = <2>;
  129. device_type = "pci";
  130. num-lanes = <4>;
  131. bus-range = <0x0 0xff>;
  132. ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
  133. 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  134. };
  135. pcie@3500000 {
  136. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  137. reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
  138. 0x00 0x03580000 0x0 0x80000 /* lut registers */
  139. 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
  140. 0x28 0x00000000 0x0 0x20000>; /* configuration space */
  141. reg-names = "dbi", "lut", "ctrl", "config";
  142. #address-cells = <3>;
  143. #size-cells = <2>;
  144. device_type = "pci";
  145. num-lanes = <4>;
  146. bus-range = <0x0 0xff>;
  147. ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
  148. 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  149. };
  150. pcie@3600000 {
  151. compatible = "fsl,ls-pcie", "snps,dw-pcie";
  152. reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
  153. 0x00 0x03680000 0x0 0x80000 /* lut registers */
  154. 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
  155. 0x30 0x00000000 0x0 0x20000>; /* configuration space */
  156. reg-names = "dbi", "lut", "ctrl", "config";
  157. #address-cells = <3>;
  158. #size-cells = <2>;
  159. device_type = "pci";
  160. num-lanes = <8>;
  161. bus-range = <0x0 0xff>;
  162. ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
  163. 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  164. };
  165. sata: sata@3200000 {
  166. compatible = "fsl,ls1088a-ahci";
  167. reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
  168. 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
  169. reg-names = "sata-base", "ecc-addr";
  170. interrupts = <0 133 4>;
  171. status = "disabled";
  172. };
  173. psci {
  174. compatible = "arm,psci-0.2";
  175. method = "smc";
  176. };
  177. fsl_mc: fsl-mc@80c000000 {
  178. compatible = "fsl,qoriq-mc", "simple-mfd";
  179. reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
  180. <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
  181. #address-cells = <3>;
  182. #size-cells = <1>;
  183. /*
  184. * Region type 0x0 - MC portals
  185. * Region type 0x1 - QBMAN portals
  186. */
  187. ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
  188. 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
  189. dpmacs {
  190. compatible = "simple-mfd";
  191. #address-cells = <1>;
  192. #size-cells = <0>;
  193. dpmac1: dpmac@1 {
  194. compatible = "fsl,qoriq-mc-dpmac";
  195. reg = <0x1>;
  196. status = "disabled";
  197. };
  198. dpmac2: dpmac@2 {
  199. compatible = "fsl,qoriq-mc-dpmac";
  200. reg = <0x2>;
  201. status = "disabled";
  202. };
  203. dpmac3: dpmac@3 {
  204. compatible = "fsl,qoriq-mc-dpmac";
  205. reg = <0x3>;
  206. status = "disabled";
  207. };
  208. dpmac4: dpmac@4 {
  209. compatible = "fsl,qoriq-mc-dpmac";
  210. reg = <0x4>;
  211. status = "disabled";
  212. };
  213. dpmac5: dpmac@5 {
  214. compatible = "fsl,qoriq-mc-dpmac";
  215. reg = <0x5>;
  216. status = "disabled";
  217. };
  218. dpmac6: dpmac@6 {
  219. compatible = "fsl,qoriq-mc-dpmac";
  220. reg = <0x6>;
  221. status = "disabled";
  222. };
  223. dpmac7: dpmac@7 {
  224. compatible = "fsl,qoriq-mc-dpmac";
  225. reg = <0x7>;
  226. status = "disabled";
  227. };
  228. dpmac8: dpmac@8 {
  229. compatible = "fsl,qoriq-mc-dpmac";
  230. reg = <0x8>;
  231. status = "disabled";
  232. };
  233. dpmac9: dpmac@9 {
  234. compatible = "fsl,qoriq-mc-dpmac";
  235. reg = <0x9>;
  236. status = "disabled";
  237. };
  238. dpmac10: dpmac@a {
  239. compatible = "fsl,qoriq-mc-dpmac";
  240. reg = <0xa>;
  241. status = "disabled";
  242. };
  243. };
  244. };
  245. emdio1: mdio@8B96000 {
  246. compatible = "fsl,ls-mdio";
  247. reg = <0x0 0x8B96000 0x0 0x1000>;
  248. #address-cells = <1>;
  249. #size-cells = <0>;
  250. status = "disabled";
  251. };
  252. emdio2: mdio@8B97000 {
  253. compatible = "fsl,ls-mdio";
  254. reg = <0x0 0x8B97000 0x0 0x1000>;
  255. #address-cells = <1>;
  256. #size-cells = <0>;
  257. status = "disabled";
  258. };
  259. };