fsl-ls1028a.dtsi 9.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * NXP ls1028a SOC common device tree source
  4. *
  5. * Copyright 2019 NXP
  6. *
  7. */
  8. #include <dt-bindings/interrupt-controller/arm-gic.h>
  9. / {
  10. compatible = "fsl,ls1028a";
  11. interrupt-parent = <&gic>;
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. sysclk: sysclk {
  15. compatible = "fixed-clock";
  16. #clock-cells = <0>;
  17. clock-frequency = <100000000>;
  18. clock-output-names = "sysclk";
  19. };
  20. clockgen: clocking@1300000 {
  21. compatible = "fsl,ls1028a-clockgen";
  22. reg = <0x0 0x1300000 0x0 0xa0000>;
  23. #clock-cells = <2>;
  24. clocks = <&sysclk>;
  25. };
  26. memory@01080000 {
  27. device_type = "memory";
  28. reg = <0x00000000 0x01080000 0 0x80000000>;
  29. /* DRAM space - 1, size : 2 GB DRAM */
  30. };
  31. gic: interrupt-controller@6000000 {
  32. compatible = "arm,gic-v3";
  33. reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
  34. <0x0 0x06040000 0 0x40000>;
  35. #interrupt-cells = <3>;
  36. interrupt-controller;
  37. interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
  38. IRQ_TYPE_LEVEL_LOW)>;
  39. };
  40. gic_lpi_base: syscon@0x80000000 {
  41. compatible = "gic-lpi-base";
  42. reg = <0x0 0x80000000 0x0 0x100000>;
  43. max-gic-redistributors = <2>;
  44. };
  45. timer {
  46. compatible = "arm,armv8-timer";
  47. interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  48. IRQ_TYPE_LEVEL_LOW)>,
  49. <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  50. IRQ_TYPE_LEVEL_LOW)>,
  51. <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  52. IRQ_TYPE_LEVEL_LOW)>,
  53. <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  54. IRQ_TYPE_LEVEL_LOW)>;
  55. };
  56. fspi: flexspi@20c0000 {
  57. compatible = "nxp,lx2160a-fspi";
  58. #address-cells = <1>;
  59. #size-cells = <0>;
  60. reg = <0x0 0x20c0000 0x0 0x10000>,
  61. <0x0 0x20000000 0x0 0x10000000>;
  62. reg-names = "fspi_base", "fspi_mmap";
  63. clocks = <&clockgen 4 3>, <&clockgen 4 3>;
  64. clock-names = "fspi_en", "fspi";
  65. interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
  66. status = "disabled";
  67. };
  68. serial0: serial@21c0500 {
  69. device_type = "serial";
  70. compatible = "fsl,ns16550", "ns16550a";
  71. reg = <0x0 0x21c0500 0x0 0x100>;
  72. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  73. status = "disabled";
  74. };
  75. serial1: serial@21c0600 {
  76. device_type = "serial";
  77. compatible = "fsl,ns16550", "ns16550a";
  78. reg = <0x0 0x21c0600 0x0 0x100>;
  79. interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
  80. status = "disabled";
  81. };
  82. pcie@3400000 {
  83. compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  84. reg = <0x00 0x03400000 0x0 0x80000
  85. 0x00 0x03480000 0x0 0x40000 /* lut registers */
  86. 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
  87. 0x80 0x00000000 0x0 0x20000>; /* configuration space */
  88. reg-names = "dbi", "lut", "ctrl", "config";
  89. #address-cells = <3>;
  90. #size-cells = <2>;
  91. device_type = "pci";
  92. num-lanes = <4>;
  93. bus-range = <0x0 0xff>;
  94. ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
  95. 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  96. };
  97. pcie@3500000 {
  98. compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
  99. reg = <0x00 0x03500000 0x0 0x80000
  100. 0x00 0x03580000 0x0 0x40000 /* lut registers */
  101. 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
  102. 0x88 0x00000000 0x0 0x20000>; /* configuration space */
  103. reg-names = "dbi", "lut", "ctrl", "config";
  104. #address-cells = <3>;
  105. #size-cells = <2>;
  106. device_type = "pci";
  107. num-lanes = <4>;
  108. bus-range = <0x0 0xff>;
  109. ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
  110. 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
  111. };
  112. pcie@1f0000000 {
  113. compatible = "pci-host-ecam-generic";
  114. /* ECAM bus 0, HW has more space reserved but not populated */
  115. bus-range = <0x0 0x0>;
  116. reg = <0x01 0xf0000000 0x0 0x100000>;
  117. #address-cells = <3>;
  118. #size-cells = <2>;
  119. device_type = "pci";
  120. ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>;
  121. enetc0: pci@0,0 {
  122. reg = <0x000000 0 0 0 0>;
  123. status = "disabled";
  124. };
  125. enetc1: pci@0,1 {
  126. reg = <0x000100 0 0 0 0>;
  127. status = "disabled";
  128. };
  129. enetc2: pci@0,2 {
  130. reg = <0x000200 0 0 0 0>;
  131. status = "okay";
  132. phy-mode = "internal";
  133. };
  134. mdio0: pci@0,3 {
  135. #address-cells=<0>;
  136. #size-cells=<1>;
  137. reg = <0x000300 0 0 0 0>;
  138. status = "disabled";
  139. };
  140. enetc6: pci@0,6 {
  141. reg = <0x000600 0 0 0 0>;
  142. status = "okay";
  143. phy-mode = "internal";
  144. };
  145. };
  146. i2c0: i2c@2000000 {
  147. compatible = "fsl,vf610-i2c";
  148. #address-cells = <1>;
  149. #size-cells = <0>;
  150. reg = <0x0 0x2000000 0x0 0x10000>;
  151. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  152. clock-names = "i2c";
  153. clocks = <&clockgen 4 0>;
  154. status = "disabled";
  155. };
  156. i2c1: i2c@2010000 {
  157. compatible = "fsl,vf610-i2c";
  158. #address-cells = <1>;
  159. #size-cells = <0>;
  160. reg = <0x0 0x2010000 0x0 0x10000>;
  161. interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
  162. clock-names = "i2c";
  163. clocks = <&clockgen 4 0>;
  164. status = "disabled";
  165. };
  166. i2c2: i2c@2020000 {
  167. compatible = "fsl,vf610-i2c";
  168. #address-cells = <1>;
  169. #size-cells = <0>;
  170. reg = <0x0 0x2020000 0x0 0x10000>;
  171. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  172. clock-names = "i2c";
  173. clocks = <&clockgen 4 0>;
  174. status = "disabled";
  175. };
  176. i2c3: i2c@2030000 {
  177. compatible = "fsl,vf610-i2c";
  178. #address-cells = <1>;
  179. #size-cells = <0>;
  180. reg = <0x0 0x2030000 0x0 0x10000>;
  181. interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
  182. clock-names = "i2c";
  183. clocks = <&clockgen 4 0>;
  184. status = "disabled";
  185. };
  186. i2c4: i2c@2040000 {
  187. compatible = "fsl,vf610-i2c";
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. reg = <0x0 0x2040000 0x0 0x10000>;
  191. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  192. clock-names = "i2c";
  193. clocks = <&clockgen 4 0>;
  194. status = "disabled";
  195. };
  196. i2c5: i2c@2050000 {
  197. compatible = "fsl,vf610-i2c";
  198. #address-cells = <1>;
  199. #size-cells = <0>;
  200. reg = <0x0 0x2050000 0x0 0x10000>;
  201. interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
  202. clock-names = "i2c";
  203. clocks = <&clockgen 4 0>;
  204. status = "disabled";
  205. };
  206. i2c6: i2c@2060000 {
  207. compatible = "fsl,vf610-i2c";
  208. #address-cells = <1>;
  209. #size-cells = <0>;
  210. reg = <0x0 0x2060000 0x0 0x10000>;
  211. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  212. clock-names = "i2c";
  213. clocks = <&clockgen 4 0>;
  214. status = "disabled";
  215. };
  216. i2c7: i2c@2070000 {
  217. compatible = "fsl,vf610-i2c";
  218. #address-cells = <1>;
  219. #size-cells = <0>;
  220. reg = <0x0 0x2070000 0x0 0x10000>;
  221. interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
  222. clock-names = "i2c";
  223. clocks = <&clockgen 4 0>;
  224. status = "disabled";
  225. };
  226. lpuart0: serial@2260000 {
  227. compatible = "fsl,ls1021a-lpuart";
  228. reg = <0x0 0x2260000 0x0 0x1000>;
  229. interrupts = <0 232 0x4>;
  230. clocks = <&sysclk>;
  231. clock-names = "ipg";
  232. little-endian;
  233. status = "disabled";
  234. };
  235. lpuart1: serial@2270000 {
  236. compatible = "fsl,ls1021a-lpuart";
  237. reg = <0x0 0x2270000 0x0 0x1000>;
  238. interrupts = <0 233 0x4>;
  239. clocks = <&sysclk>;
  240. clock-names = "ipg";
  241. little-endian;
  242. status = "disabled";
  243. };
  244. lpuart2: serial@2280000 {
  245. compatible = "fsl,ls1021a-lpuart";
  246. reg = <0x0 0x2280000 0x0 0x1000>;
  247. interrupts = <0 234 0x4>;
  248. clocks = <&sysclk>;
  249. clock-names = "ipg";
  250. little-endian;
  251. status = "disabled";
  252. };
  253. lpuart3: serial@2290000 {
  254. compatible = "fsl,ls1021a-lpuart";
  255. reg = <0x0 0x2290000 0x0 0x1000>;
  256. interrupts = <0 235 0x4>;
  257. clocks = <&sysclk>;
  258. clock-names = "ipg";
  259. little-endian;
  260. status = "disabled";
  261. };
  262. lpuart4: serial@22a0000 {
  263. compatible = "fsl,ls1021a-lpuart";
  264. reg = <0x0 0x22a0000 0x0 0x1000>;
  265. interrupts = <0 236 0x4>;
  266. clocks = <&sysclk>;
  267. clock-names = "ipg";
  268. little-endian;
  269. status = "disabled";
  270. };
  271. lpuart5: serial@22b0000 {
  272. compatible = "fsl,ls1021a-lpuart";
  273. reg = <0x0 0x22b0000 0x0 0x1000>;
  274. interrupts = <0 237 0x4>;
  275. clocks = <&sysclk>;
  276. clock-names = "ipg";
  277. little-endian;
  278. status = "disabled";
  279. };
  280. usb1: usb3@3100000 {
  281. compatible = "fsl,layerscape-dwc3";
  282. reg = <0x0 0x3100000 0x0 0x10000>;
  283. interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  284. dr_mode = "host";
  285. status = "disabled";
  286. };
  287. usb2: usb3@3110000 {
  288. compatible = "fsl,layerscape-dwc3";
  289. reg = <0x0 0x3110000 0x0 0x10000>;
  290. interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
  291. dr_mode = "host";
  292. status = "disabled";
  293. };
  294. dspi0: dspi@2100000 {
  295. compatible = "fsl,vf610-dspi";
  296. #address-cells = <1>;
  297. #size-cells = <0>;
  298. reg = <0x0 0x2100000 0x0 0x10000>;
  299. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  300. clock-names = "dspi";
  301. clocks = <&clockgen 4 0>;
  302. num-cs = <5>;
  303. litte-endian;
  304. status = "disabled";
  305. };
  306. dspi1: dspi@2110000 {
  307. compatible = "fsl,vf610-dspi";
  308. #address-cells = <1>;
  309. #size-cells = <0>;
  310. reg = <0x0 0x2110000 0x0 0x10000>;
  311. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  312. clock-names = "dspi";
  313. clocks = <&clockgen 4 0>;
  314. num-cs = <5>;
  315. little-endian;
  316. status = "disabled";
  317. };
  318. dspi2: dspi@2120000 {
  319. compatible = "fsl,vf610-dspi";
  320. #address-cells = <1>;
  321. #size-cells = <0>;
  322. reg = <0x0 0x2120000 0x0 0x10000>;
  323. interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
  324. clock-names = "dspi";
  325. clocks = <&clockgen 4 0>;
  326. num-cs = <5>;
  327. little-endian;
  328. status = "disabled";
  329. };
  330. esdhc0: esdhc@2140000 {
  331. compatible = "fsl,esdhc";
  332. reg = <0x0 0x2140000 0x0 0x10000>;
  333. interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
  334. big-endian;
  335. bus-width = <4>;
  336. status = "disabled";
  337. };
  338. esdhc1: esdhc@2150000 {
  339. compatible = "fsl,esdhc";
  340. reg = <0x0 0x2150000 0x0 0x10000>;
  341. interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
  342. big-endian;
  343. non-removable;
  344. bus-width = <4>;
  345. status = "disabled";
  346. };
  347. sata: sata@3200000 {
  348. compatible = "fsl,ls1028a-ahci";
  349. reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
  350. 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
  351. reg-names = "sata-base", "ecc-addr";
  352. interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
  353. status = "disabled";
  354. };
  355. cluster1_core0_watchdog: wdt@c000000 {
  356. compatible = "arm,sp805-wdt";
  357. reg = <0x0 0xc000000 0x0 0x1000>;
  358. };
  359. };