xhci.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB HOST XHCI Controller stack
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. /**
  16. * This file gives the xhci stack for usb3.0 looking into
  17. * xhci specification Rev1.0 (5/21/10).
  18. * The quirk devices support hasn't been given yet.
  19. */
  20. #include <common.h>
  21. #include <cpu_func.h>
  22. #include <dm.h>
  23. #include <log.h>
  24. #include <asm/byteorder.h>
  25. #include <usb.h>
  26. #include <malloc.h>
  27. #include <watchdog.h>
  28. #include <asm/cache.h>
  29. #include <asm/unaligned.h>
  30. #include <linux/bitops.h>
  31. #include <linux/bug.h>
  32. #include <linux/delay.h>
  33. #include <linux/errno.h>
  34. #include <usb/xhci.h>
  35. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  36. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  37. #endif
  38. static struct descriptor {
  39. struct usb_hub_descriptor hub;
  40. struct usb_device_descriptor device;
  41. struct usb_config_descriptor config;
  42. struct usb_interface_descriptor interface;
  43. struct usb_endpoint_descriptor endpoint;
  44. struct usb_ss_ep_comp_descriptor ep_companion;
  45. } __attribute__ ((packed)) descriptor = {
  46. {
  47. 0xc, /* bDescLength */
  48. 0x2a, /* bDescriptorType: hub descriptor */
  49. 2, /* bNrPorts -- runtime modified */
  50. cpu_to_le16(0x8), /* wHubCharacteristics */
  51. 10, /* bPwrOn2PwrGood */
  52. 0, /* bHubCntrCurrent */
  53. { /* Device removable */
  54. } /* at most 7 ports! XXX */
  55. },
  56. {
  57. 0x12, /* bLength */
  58. 1, /* bDescriptorType: UDESC_DEVICE */
  59. cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
  60. 9, /* bDeviceClass: UDCLASS_HUB */
  61. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  62. 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
  63. 9, /* bMaxPacketSize: 512 bytes 2^9 */
  64. 0x0000, /* idVendor */
  65. 0x0000, /* idProduct */
  66. cpu_to_le16(0x0100), /* bcdDevice */
  67. 1, /* iManufacturer */
  68. 2, /* iProduct */
  69. 0, /* iSerialNumber */
  70. 1 /* bNumConfigurations: 1 */
  71. },
  72. {
  73. 0x9,
  74. 2, /* bDescriptorType: UDESC_CONFIG */
  75. cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
  76. 1, /* bNumInterface */
  77. 1, /* bConfigurationValue */
  78. 0, /* iConfiguration */
  79. 0x40, /* bmAttributes: UC_SELF_POWER */
  80. 0 /* bMaxPower */
  81. },
  82. {
  83. 0x9, /* bLength */
  84. 4, /* bDescriptorType: UDESC_INTERFACE */
  85. 0, /* bInterfaceNumber */
  86. 0, /* bAlternateSetting */
  87. 1, /* bNumEndpoints */
  88. 9, /* bInterfaceClass: UICLASS_HUB */
  89. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  90. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  91. 0 /* iInterface */
  92. },
  93. {
  94. 0x7, /* bLength */
  95. 5, /* bDescriptorType: UDESC_ENDPOINT */
  96. 0x81, /* bEndpointAddress: IN endpoint 1 */
  97. 3, /* bmAttributes: UE_INTERRUPT */
  98. 8, /* wMaxPacketSize */
  99. 255 /* bInterval */
  100. },
  101. {
  102. 0x06, /* ss_bLength */
  103. 0x30, /* ss_bDescriptorType: SS EP Companion */
  104. 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
  105. /* ss_bmAttributes: 1 packet per service interval */
  106. 0x00,
  107. /* ss_wBytesPerInterval: 15 bits for max 15 ports */
  108. cpu_to_le16(0x02),
  109. },
  110. };
  111. #if !CONFIG_IS_ENABLED(DM_USB)
  112. static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  113. #endif
  114. struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
  115. {
  116. #if CONFIG_IS_ENABLED(DM_USB)
  117. struct udevice *dev;
  118. /* Find the USB controller */
  119. for (dev = udev->dev;
  120. device_get_uclass_id(dev) != UCLASS_USB;
  121. dev = dev->parent)
  122. ;
  123. return dev_get_priv(dev);
  124. #else
  125. return udev->controller;
  126. #endif
  127. }
  128. /**
  129. * Waits for as per specified amount of time
  130. * for the "result" to match with "done"
  131. *
  132. * @param ptr pointer to the register to be read
  133. * @param mask mask for the value read
  134. * @param done value to be campared with result
  135. * @param usec time to wait till
  136. * @return 0 if handshake is success else < 0 on failure
  137. */
  138. static int handshake(uint32_t volatile *ptr, uint32_t mask,
  139. uint32_t done, int usec)
  140. {
  141. uint32_t result;
  142. do {
  143. result = xhci_readl(ptr);
  144. if (result == ~(uint32_t)0)
  145. return -ENODEV;
  146. result &= mask;
  147. if (result == done)
  148. return 0;
  149. usec--;
  150. udelay(1);
  151. } while (usec > 0);
  152. return -ETIMEDOUT;
  153. }
  154. /**
  155. * Set the run bit and wait for the host to be running.
  156. *
  157. * @param hcor pointer to host controller operation registers
  158. * @return status of the Handshake
  159. */
  160. static int xhci_start(struct xhci_hcor *hcor)
  161. {
  162. u32 temp;
  163. int ret;
  164. puts("Starting the controller\n");
  165. temp = xhci_readl(&hcor->or_usbcmd);
  166. temp |= (CMD_RUN);
  167. xhci_writel(&hcor->or_usbcmd, temp);
  168. /*
  169. * Wait for the HCHalted Status bit to be 0 to indicate the host is
  170. * running.
  171. */
  172. ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
  173. if (ret)
  174. debug("Host took too long to start, "
  175. "waited %u microseconds.\n",
  176. XHCI_MAX_HALT_USEC);
  177. return ret;
  178. }
  179. #if CONFIG_IS_ENABLED(DM_USB)
  180. /**
  181. * Resets XHCI Hardware
  182. *
  183. * @param ctrl pointer to host controller
  184. * @return 0 if OK, or a negative error code.
  185. */
  186. static int xhci_reset_hw(struct xhci_ctrl *ctrl)
  187. {
  188. int ret;
  189. ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset);
  190. if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
  191. dev_err(ctrl->dev, "failed to get reset\n");
  192. return ret;
  193. }
  194. if (reset_valid(&ctrl->reset)) {
  195. ret = reset_assert(&ctrl->reset);
  196. if (ret)
  197. return ret;
  198. ret = reset_deassert(&ctrl->reset);
  199. if (ret)
  200. return ret;
  201. }
  202. return 0;
  203. }
  204. #endif
  205. /**
  206. * Resets the XHCI Controller
  207. *
  208. * @param hcor pointer to host controller operation registers
  209. * @return -EBUSY if XHCI Controller is not halted else status of handshake
  210. */
  211. static int xhci_reset(struct xhci_hcor *hcor)
  212. {
  213. u32 cmd;
  214. u32 state;
  215. int ret;
  216. /* Halting the Host first */
  217. debug("// Halt the HC: %p\n", hcor);
  218. state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
  219. if (!state) {
  220. cmd = xhci_readl(&hcor->or_usbcmd);
  221. cmd &= ~CMD_RUN;
  222. xhci_writel(&hcor->or_usbcmd, cmd);
  223. }
  224. ret = handshake(&hcor->or_usbsts,
  225. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  226. if (ret) {
  227. printf("Host not halted after %u microseconds.\n",
  228. XHCI_MAX_HALT_USEC);
  229. return -EBUSY;
  230. }
  231. debug("// Reset the HC\n");
  232. cmd = xhci_readl(&hcor->or_usbcmd);
  233. cmd |= CMD_RESET;
  234. xhci_writel(&hcor->or_usbcmd, cmd);
  235. ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
  236. if (ret)
  237. return ret;
  238. /*
  239. * xHCI cannot write to any doorbells or operational registers other
  240. * than status until the "Controller Not Ready" flag is cleared.
  241. */
  242. return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
  243. }
  244. /**
  245. * Used for passing endpoint bitmasks between the core and HCDs.
  246. * Find the index for an endpoint given its descriptor.
  247. * Use the return value to right shift 1 for the bitmask.
  248. *
  249. * Index = (epnum * 2) + direction - 1,
  250. * where direction = 0 for OUT, 1 for IN.
  251. * For control endpoints, the IN index is used (OUT index is unused), so
  252. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  253. *
  254. * @param desc USB enpdoint Descriptor
  255. * @return index of the Endpoint
  256. */
  257. static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
  258. {
  259. unsigned int index;
  260. if (usb_endpoint_xfer_control(desc))
  261. index = (unsigned int)(usb_endpoint_num(desc) * 2);
  262. else
  263. index = (unsigned int)((usb_endpoint_num(desc) * 2) -
  264. (usb_endpoint_dir_in(desc) ? 0 : 1));
  265. return index;
  266. }
  267. /*
  268. * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
  269. * microframes, rounded down to nearest power of 2.
  270. */
  271. static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
  272. unsigned int min_exponent,
  273. unsigned int max_exponent)
  274. {
  275. unsigned int interval;
  276. interval = fls(desc_interval) - 1;
  277. interval = clamp_val(interval, min_exponent, max_exponent);
  278. if ((1 << interval) != desc_interval)
  279. debug("rounding interval to %d microframes, "\
  280. "ep desc says %d microframes\n",
  281. 1 << interval, desc_interval);
  282. return interval;
  283. }
  284. static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
  285. struct usb_endpoint_descriptor *endpt_desc)
  286. {
  287. if (endpt_desc->bInterval == 0)
  288. return 0;
  289. return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
  290. }
  291. static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
  292. struct usb_endpoint_descriptor *endpt_desc)
  293. {
  294. return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
  295. }
  296. /*
  297. * Convert interval expressed as 2^(bInterval - 1) == interval into
  298. * straight exponent value 2^n == interval.
  299. */
  300. static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
  301. struct usb_endpoint_descriptor *endpt_desc)
  302. {
  303. unsigned int interval;
  304. interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
  305. if (interval != endpt_desc->bInterval - 1)
  306. debug("ep %#x - rounding interval to %d %sframes\n",
  307. endpt_desc->bEndpointAddress, 1 << interval,
  308. udev->speed == USB_SPEED_FULL ? "" : "micro");
  309. if (udev->speed == USB_SPEED_FULL) {
  310. /*
  311. * Full speed isoc endpoints specify interval in frames,
  312. * not microframes. We are using microframes everywhere,
  313. * so adjust accordingly.
  314. */
  315. interval += 3; /* 1 frame = 2^3 uframes */
  316. }
  317. return interval;
  318. }
  319. /*
  320. * Return the polling or NAK interval.
  321. *
  322. * The polling interval is expressed in "microframes". If xHCI's Interval field
  323. * is set to N, it will service the endpoint every 2^(Interval)*125us.
  324. *
  325. * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
  326. * is set to 0.
  327. */
  328. static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
  329. struct usb_endpoint_descriptor *endpt_desc)
  330. {
  331. unsigned int interval = 0;
  332. switch (udev->speed) {
  333. case USB_SPEED_HIGH:
  334. /* Max NAK rate */
  335. if (usb_endpoint_xfer_control(endpt_desc) ||
  336. usb_endpoint_xfer_bulk(endpt_desc)) {
  337. interval = xhci_parse_microframe_interval(udev,
  338. endpt_desc);
  339. break;
  340. }
  341. /* Fall through - SS and HS isoc/int have same decoding */
  342. case USB_SPEED_SUPER:
  343. if (usb_endpoint_xfer_int(endpt_desc) ||
  344. usb_endpoint_xfer_isoc(endpt_desc)) {
  345. interval = xhci_parse_exponent_interval(udev,
  346. endpt_desc);
  347. }
  348. break;
  349. case USB_SPEED_FULL:
  350. if (usb_endpoint_xfer_isoc(endpt_desc)) {
  351. interval = xhci_parse_exponent_interval(udev,
  352. endpt_desc);
  353. break;
  354. }
  355. /*
  356. * Fall through for interrupt endpoint interval decoding
  357. * since it uses the same rules as low speed interrupt
  358. * endpoints.
  359. */
  360. case USB_SPEED_LOW:
  361. if (usb_endpoint_xfer_int(endpt_desc) ||
  362. usb_endpoint_xfer_isoc(endpt_desc)) {
  363. interval = xhci_parse_frame_interval(udev, endpt_desc);
  364. }
  365. break;
  366. default:
  367. BUG();
  368. }
  369. return interval;
  370. }
  371. /*
  372. * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
  373. * High speed endpoint descriptors can define "the number of additional
  374. * transaction opportunities per microframe", but that goes in the Max Burst
  375. * endpoint context field.
  376. */
  377. static u32 xhci_get_endpoint_mult(struct usb_device *udev,
  378. struct usb_endpoint_descriptor *endpt_desc,
  379. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  380. {
  381. if (udev->speed < USB_SPEED_SUPER ||
  382. !usb_endpoint_xfer_isoc(endpt_desc))
  383. return 0;
  384. return ss_ep_comp_desc->bmAttributes;
  385. }
  386. static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
  387. struct usb_endpoint_descriptor *endpt_desc,
  388. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  389. {
  390. /* Super speed and Plus have max burst in ep companion desc */
  391. if (udev->speed >= USB_SPEED_SUPER)
  392. return ss_ep_comp_desc->bMaxBurst;
  393. if (udev->speed == USB_SPEED_HIGH &&
  394. (usb_endpoint_xfer_isoc(endpt_desc) ||
  395. usb_endpoint_xfer_int(endpt_desc)))
  396. return usb_endpoint_maxp_mult(endpt_desc) - 1;
  397. return 0;
  398. }
  399. /*
  400. * Return the maximum endpoint service interval time (ESIT) payload.
  401. * Basically, this is the maxpacket size, multiplied by the burst size
  402. * and mult size.
  403. */
  404. static u32 xhci_get_max_esit_payload(struct usb_device *udev,
  405. struct usb_endpoint_descriptor *endpt_desc,
  406. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  407. {
  408. int max_burst;
  409. int max_packet;
  410. /* Only applies for interrupt or isochronous endpoints */
  411. if (usb_endpoint_xfer_control(endpt_desc) ||
  412. usb_endpoint_xfer_bulk(endpt_desc))
  413. return 0;
  414. /* SuperSpeed Isoc ep with less than 48k per esit */
  415. if (udev->speed >= USB_SPEED_SUPER)
  416. return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
  417. max_packet = usb_endpoint_maxp(endpt_desc);
  418. max_burst = usb_endpoint_maxp_mult(endpt_desc);
  419. /* A 0 in max burst means 1 transfer per ESIT */
  420. return max_packet * max_burst;
  421. }
  422. /**
  423. * Issue a configure endpoint command or evaluate context command
  424. * and wait for it to finish.
  425. *
  426. * @param udev pointer to the Device Data Structure
  427. * @param ctx_change flag to indicate the Context has changed or NOT
  428. * @return 0 on success, -1 on failure
  429. */
  430. static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
  431. {
  432. struct xhci_container_ctx *in_ctx;
  433. struct xhci_virt_device *virt_dev;
  434. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  435. union xhci_trb *event;
  436. virt_dev = ctrl->devs[udev->slot_id];
  437. in_ctx = virt_dev->in_ctx;
  438. xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
  439. xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
  440. ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
  441. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  442. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
  443. != udev->slot_id);
  444. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  445. case COMP_SUCCESS:
  446. debug("Successful %s command\n",
  447. ctx_change ? "Evaluate Context" : "Configure Endpoint");
  448. break;
  449. default:
  450. printf("ERROR: %s command returned completion code %d.\n",
  451. ctx_change ? "Evaluate Context" : "Configure Endpoint",
  452. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  453. return -EINVAL;
  454. }
  455. xhci_acknowledge_event(ctrl);
  456. return 0;
  457. }
  458. /**
  459. * Configure the endpoint, programming the device contexts.
  460. *
  461. * @param udev pointer to the USB device structure
  462. * @return returns the status of the xhci_configure_endpoints
  463. */
  464. static int xhci_set_configuration(struct usb_device *udev)
  465. {
  466. struct xhci_container_ctx *in_ctx;
  467. struct xhci_container_ctx *out_ctx;
  468. struct xhci_input_control_ctx *ctrl_ctx;
  469. struct xhci_slot_ctx *slot_ctx;
  470. struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
  471. int cur_ep;
  472. int max_ep_flag = 0;
  473. int ep_index;
  474. unsigned int dir;
  475. unsigned int ep_type;
  476. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  477. int num_of_ep;
  478. int ep_flag = 0;
  479. u64 trb_64 = 0;
  480. int slot_id = udev->slot_id;
  481. struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
  482. struct usb_interface *ifdesc;
  483. u32 max_esit_payload;
  484. unsigned int interval;
  485. unsigned int mult;
  486. unsigned int max_burst;
  487. unsigned int avg_trb_len;
  488. unsigned int err_count = 0;
  489. out_ctx = virt_dev->out_ctx;
  490. in_ctx = virt_dev->in_ctx;
  491. num_of_ep = udev->config.if_desc[0].no_of_ep;
  492. ifdesc = &udev->config.if_desc[0];
  493. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  494. /* Initialize the input context control */
  495. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  496. ctrl_ctx->drop_flags = 0;
  497. /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
  498. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  499. ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
  500. ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
  501. if (max_ep_flag < ep_flag)
  502. max_ep_flag = ep_flag;
  503. }
  504. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  505. /* slot context */
  506. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  507. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  508. slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK));
  509. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
  510. xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
  511. /* filling up ep contexts */
  512. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  513. struct usb_endpoint_descriptor *endpt_desc = NULL;
  514. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
  515. endpt_desc = &ifdesc->ep_desc[cur_ep];
  516. ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
  517. trb_64 = 0;
  518. /*
  519. * Get values to fill the endpoint context, mostly from ep
  520. * descriptor. The average TRB buffer lengt for bulk endpoints
  521. * is unclear as we have no clue on scatter gather list entry
  522. * size. For Isoc and Int, set it to max available.
  523. * See xHCI 1.1 spec 4.14.1.1 for details.
  524. */
  525. max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
  526. ss_ep_comp_desc);
  527. interval = xhci_get_endpoint_interval(udev, endpt_desc);
  528. mult = xhci_get_endpoint_mult(udev, endpt_desc,
  529. ss_ep_comp_desc);
  530. max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
  531. ss_ep_comp_desc);
  532. avg_trb_len = max_esit_payload;
  533. ep_index = xhci_get_ep_index(endpt_desc);
  534. ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  535. /* Allocate the ep rings */
  536. virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
  537. if (!virt_dev->eps[ep_index].ring)
  538. return -ENOMEM;
  539. /*NOTE: ep_desc[0] actually represents EP1 and so on */
  540. dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
  541. ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
  542. ep_ctx[ep_index]->ep_info =
  543. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
  544. EP_INTERVAL(interval) | EP_MULT(mult));
  545. ep_ctx[ep_index]->ep_info2 = cpu_to_le32(EP_TYPE(ep_type));
  546. ep_ctx[ep_index]->ep_info2 |=
  547. cpu_to_le32(MAX_PACKET
  548. (get_unaligned(&endpt_desc->wMaxPacketSize)));
  549. /* Allow 3 retries for everything but isoc, set CErr = 3 */
  550. if (!usb_endpoint_xfer_isoc(endpt_desc))
  551. err_count = 3;
  552. ep_ctx[ep_index]->ep_info2 |=
  553. cpu_to_le32(MAX_BURST(max_burst) |
  554. ERROR_COUNT(err_count));
  555. trb_64 = virt_to_phys(virt_dev->eps[ep_index].ring->enqueue);
  556. ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
  557. virt_dev->eps[ep_index].ring->cycle_state);
  558. /*
  559. * xHCI spec 6.2.3:
  560. * 'Average TRB Length' should be 8 for control endpoints.
  561. */
  562. if (usb_endpoint_xfer_control(endpt_desc))
  563. avg_trb_len = 8;
  564. ep_ctx[ep_index]->tx_info =
  565. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
  566. EP_AVG_TRB_LENGTH(avg_trb_len));
  567. /*
  568. * The MediaTek xHCI defines some extra SW parameters which
  569. * are put into reserved DWs in Slot and Endpoint Contexts
  570. * for synchronous endpoints.
  571. */
  572. if (ctrl->quirks & XHCI_MTK_HOST) {
  573. ep_ctx[ep_index]->reserved[0] =
  574. cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
  575. }
  576. }
  577. return xhci_configure_endpoints(udev, false);
  578. }
  579. /**
  580. * Issue an Address Device command (which will issue a SetAddress request to
  581. * the device).
  582. *
  583. * @param udev pointer to the Device Data Structure
  584. * @return 0 if successful else error code on failure
  585. */
  586. static int xhci_address_device(struct usb_device *udev, int root_portnr)
  587. {
  588. int ret = 0;
  589. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  590. struct xhci_slot_ctx *slot_ctx;
  591. struct xhci_input_control_ctx *ctrl_ctx;
  592. struct xhci_virt_device *virt_dev;
  593. int slot_id = udev->slot_id;
  594. union xhci_trb *event;
  595. virt_dev = ctrl->devs[slot_id];
  596. /*
  597. * This is the first Set Address since device plug-in
  598. * so setting up the slot context.
  599. */
  600. debug("Setting up addressable devices %p\n", ctrl->dcbaa);
  601. xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
  602. ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
  603. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
  604. ctrl_ctx->drop_flags = 0;
  605. xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
  606. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  607. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
  608. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  609. case COMP_CTX_STATE:
  610. case COMP_EBADSLT:
  611. printf("Setup ERROR: address device command for slot %d.\n",
  612. slot_id);
  613. ret = -EINVAL;
  614. break;
  615. case COMP_TX_ERR:
  616. puts("Device not responding to set address.\n");
  617. ret = -EPROTO;
  618. break;
  619. case COMP_DEV_ERR:
  620. puts("ERROR: Incompatible device"
  621. "for address device command.\n");
  622. ret = -ENODEV;
  623. break;
  624. case COMP_SUCCESS:
  625. debug("Successful Address Device command\n");
  626. udev->status = 0;
  627. break;
  628. default:
  629. printf("ERROR: unexpected command completion code 0x%x.\n",
  630. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  631. ret = -EINVAL;
  632. break;
  633. }
  634. xhci_acknowledge_event(ctrl);
  635. if (ret < 0)
  636. /*
  637. * TODO: Unsuccessful Address Device command shall leave the
  638. * slot in default state. So, issue Disable Slot command now.
  639. */
  640. return ret;
  641. xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
  642. virt_dev->out_ctx->size);
  643. slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
  644. debug("xHC internal address is: %d\n",
  645. le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
  646. return 0;
  647. }
  648. /**
  649. * Issue Enable slot command to the controller to allocate
  650. * device slot and assign the slot id. It fails if the xHC
  651. * ran out of device slots, the Enable Slot command timed out,
  652. * or allocating memory failed.
  653. *
  654. * @param udev pointer to the Device Data Structure
  655. * @return Returns 0 on succes else return error code on failure
  656. */
  657. static int _xhci_alloc_device(struct usb_device *udev)
  658. {
  659. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  660. union xhci_trb *event;
  661. int ret;
  662. /*
  663. * Root hub will be first device to be initailized.
  664. * If this device is root-hub, don't do any xHC related
  665. * stuff.
  666. */
  667. if (ctrl->rootdev == 0) {
  668. udev->speed = USB_SPEED_SUPER;
  669. return 0;
  670. }
  671. xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
  672. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  673. BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
  674. != COMP_SUCCESS);
  675. udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
  676. xhci_acknowledge_event(ctrl);
  677. ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
  678. if (ret < 0) {
  679. /*
  680. * TODO: Unsuccessful Address Device command shall leave
  681. * the slot in default. So, issue Disable Slot command now.
  682. */
  683. puts("Could not allocate xHCI USB device data structures\n");
  684. return ret;
  685. }
  686. return 0;
  687. }
  688. #if !CONFIG_IS_ENABLED(DM_USB)
  689. int usb_alloc_device(struct usb_device *udev)
  690. {
  691. return _xhci_alloc_device(udev);
  692. }
  693. #endif
  694. /*
  695. * Full speed devices may have a max packet size greater than 8 bytes, but the
  696. * USB core doesn't know that until it reads the first 8 bytes of the
  697. * descriptor. If the usb_device's max packet size changes after that point,
  698. * we need to issue an evaluate context command and wait on it.
  699. *
  700. * @param udev pointer to the Device Data Structure
  701. * @return returns the status of the xhci_configure_endpoints
  702. */
  703. int xhci_check_maxpacket(struct usb_device *udev)
  704. {
  705. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  706. unsigned int slot_id = udev->slot_id;
  707. int ep_index = 0; /* control endpoint */
  708. struct xhci_container_ctx *in_ctx;
  709. struct xhci_container_ctx *out_ctx;
  710. struct xhci_input_control_ctx *ctrl_ctx;
  711. struct xhci_ep_ctx *ep_ctx;
  712. int max_packet_size;
  713. int hw_max_packet_size;
  714. int ret = 0;
  715. out_ctx = ctrl->devs[slot_id]->out_ctx;
  716. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  717. ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
  718. hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
  719. max_packet_size = udev->epmaxpacketin[0];
  720. if (hw_max_packet_size != max_packet_size) {
  721. debug("Max Packet Size for ep 0 changed.\n");
  722. debug("Max packet size in usb_device = %d\n", max_packet_size);
  723. debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
  724. debug("Issuing evaluate context command.\n");
  725. /* Set up the modified control endpoint 0 */
  726. xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
  727. ctrl->devs[slot_id]->out_ctx, ep_index);
  728. in_ctx = ctrl->devs[slot_id]->in_ctx;
  729. ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  730. ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET(MAX_PACKET_MASK));
  731. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
  732. /*
  733. * Set up the input context flags for the command
  734. * FIXME: This won't work if a non-default control endpoint
  735. * changes max packet sizes.
  736. */
  737. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  738. ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
  739. ctrl_ctx->drop_flags = 0;
  740. ret = xhci_configure_endpoints(udev, true);
  741. }
  742. return ret;
  743. }
  744. /**
  745. * Clears the Change bits of the Port Status Register
  746. *
  747. * @param wValue request value
  748. * @param wIndex request index
  749. * @param addr address of posrt status register
  750. * @param port_status state of port status register
  751. * @return none
  752. */
  753. static void xhci_clear_port_change_bit(u16 wValue,
  754. u16 wIndex, volatile uint32_t *addr, u32 port_status)
  755. {
  756. char *port_change_bit;
  757. u32 status;
  758. switch (wValue) {
  759. case USB_PORT_FEAT_C_RESET:
  760. status = PORT_RC;
  761. port_change_bit = "reset";
  762. break;
  763. case USB_PORT_FEAT_C_CONNECTION:
  764. status = PORT_CSC;
  765. port_change_bit = "connect";
  766. break;
  767. case USB_PORT_FEAT_C_OVER_CURRENT:
  768. status = PORT_OCC;
  769. port_change_bit = "over-current";
  770. break;
  771. case USB_PORT_FEAT_C_ENABLE:
  772. status = PORT_PEC;
  773. port_change_bit = "enable/disable";
  774. break;
  775. case USB_PORT_FEAT_C_SUSPEND:
  776. status = PORT_PLC;
  777. port_change_bit = "suspend/resume";
  778. break;
  779. default:
  780. /* Should never happen */
  781. return;
  782. }
  783. /* Change bits are all write 1 to clear */
  784. xhci_writel(addr, port_status | status);
  785. port_status = xhci_readl(addr);
  786. debug("clear port %s change, actual port %d status = 0x%x\n",
  787. port_change_bit, wIndex, port_status);
  788. }
  789. /**
  790. * Save Read Only (RO) bits and save read/write bits where
  791. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  792. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  793. *
  794. * @param state state of the Port Status and Control Regsiter
  795. * @return a value that would result in the port being in the
  796. * same state, if the value was written to the port
  797. * status control register.
  798. */
  799. static u32 xhci_port_state_to_neutral(u32 state)
  800. {
  801. /* Save read-only status and port state */
  802. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  803. }
  804. /**
  805. * Submits the Requests to the XHCI Host Controller
  806. *
  807. * @param udev pointer to the USB device structure
  808. * @param pipe contains the DIR_IN or OUT , devnum
  809. * @param buffer buffer to be read/written based on the request
  810. * @return returns 0 if successful else -1 on failure
  811. */
  812. static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
  813. void *buffer, struct devrequest *req)
  814. {
  815. uint8_t tmpbuf[4];
  816. u16 typeReq;
  817. void *srcptr = NULL;
  818. int len, srclen;
  819. uint32_t reg;
  820. volatile uint32_t *status_reg;
  821. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  822. struct xhci_hccr *hccr = ctrl->hccr;
  823. struct xhci_hcor *hcor = ctrl->hcor;
  824. int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
  825. if ((req->requesttype & USB_RT_PORT) &&
  826. le16_to_cpu(req->index) > max_ports) {
  827. printf("The request port(%d) exceeds maximum port number\n",
  828. le16_to_cpu(req->index) - 1);
  829. return -EINVAL;
  830. }
  831. status_reg = (volatile uint32_t *)
  832. (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
  833. srclen = 0;
  834. typeReq = req->request | req->requesttype << 8;
  835. switch (typeReq) {
  836. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  837. switch (le16_to_cpu(req->value) >> 8) {
  838. case USB_DT_DEVICE:
  839. debug("USB_DT_DEVICE request\n");
  840. srcptr = &descriptor.device;
  841. srclen = 0x12;
  842. break;
  843. case USB_DT_CONFIG:
  844. debug("USB_DT_CONFIG config\n");
  845. srcptr = &descriptor.config;
  846. srclen = 0x19;
  847. break;
  848. case USB_DT_STRING:
  849. debug("USB_DT_STRING config\n");
  850. switch (le16_to_cpu(req->value) & 0xff) {
  851. case 0: /* Language */
  852. srcptr = "\4\3\11\4";
  853. srclen = 4;
  854. break;
  855. case 1: /* Vendor String */
  856. srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
  857. srclen = 14;
  858. break;
  859. case 2: /* Product Name */
  860. srcptr = "\52\3X\0H\0C\0I\0 "
  861. "\0H\0o\0s\0t\0 "
  862. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  863. srclen = 42;
  864. break;
  865. default:
  866. printf("unknown value DT_STRING %x\n",
  867. le16_to_cpu(req->value));
  868. goto unknown;
  869. }
  870. break;
  871. default:
  872. printf("unknown value %x\n", le16_to_cpu(req->value));
  873. goto unknown;
  874. }
  875. break;
  876. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  877. switch (le16_to_cpu(req->value) >> 8) {
  878. case USB_DT_HUB:
  879. case USB_DT_SS_HUB:
  880. debug("USB_DT_HUB config\n");
  881. srcptr = &descriptor.hub;
  882. srclen = 0x8;
  883. break;
  884. default:
  885. printf("unknown value %x\n", le16_to_cpu(req->value));
  886. goto unknown;
  887. }
  888. break;
  889. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  890. debug("USB_REQ_SET_ADDRESS\n");
  891. ctrl->rootdev = le16_to_cpu(req->value);
  892. break;
  893. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  894. /* Do nothing */
  895. break;
  896. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  897. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  898. tmpbuf[1] = 0;
  899. srcptr = tmpbuf;
  900. srclen = 2;
  901. break;
  902. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  903. memset(tmpbuf, 0, 4);
  904. reg = xhci_readl(status_reg);
  905. if (reg & PORT_CONNECT) {
  906. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  907. switch (reg & DEV_SPEED_MASK) {
  908. case XDEV_FS:
  909. debug("SPEED = FULLSPEED\n");
  910. break;
  911. case XDEV_LS:
  912. debug("SPEED = LOWSPEED\n");
  913. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  914. break;
  915. case XDEV_HS:
  916. debug("SPEED = HIGHSPEED\n");
  917. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  918. break;
  919. case XDEV_SS:
  920. debug("SPEED = SUPERSPEED\n");
  921. tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
  922. break;
  923. }
  924. }
  925. if (reg & PORT_PE)
  926. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  927. if ((reg & PORT_PLS_MASK) == XDEV_U3)
  928. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  929. if (reg & PORT_OC)
  930. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  931. if (reg & PORT_RESET)
  932. tmpbuf[0] |= USB_PORT_STAT_RESET;
  933. if (reg & PORT_POWER)
  934. /*
  935. * XXX: This Port power bit (for USB 3.0 hub)
  936. * we are faking in USB 2.0 hub port status;
  937. * since there's a change in bit positions in
  938. * two:
  939. * USB 2.0 port status PP is at position[8]
  940. * USB 3.0 port status PP is at position[9]
  941. * So, we are still keeping it at position [8]
  942. */
  943. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  944. if (reg & PORT_CSC)
  945. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  946. if (reg & PORT_PEC)
  947. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  948. if (reg & PORT_OCC)
  949. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  950. if (reg & PORT_RC)
  951. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  952. srcptr = tmpbuf;
  953. srclen = 4;
  954. break;
  955. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  956. reg = xhci_readl(status_reg);
  957. reg = xhci_port_state_to_neutral(reg);
  958. switch (le16_to_cpu(req->value)) {
  959. case USB_PORT_FEAT_ENABLE:
  960. reg |= PORT_PE;
  961. xhci_writel(status_reg, reg);
  962. break;
  963. case USB_PORT_FEAT_POWER:
  964. reg |= PORT_POWER;
  965. xhci_writel(status_reg, reg);
  966. break;
  967. case USB_PORT_FEAT_RESET:
  968. reg |= PORT_RESET;
  969. xhci_writel(status_reg, reg);
  970. break;
  971. default:
  972. printf("unknown feature %x\n", le16_to_cpu(req->value));
  973. goto unknown;
  974. }
  975. break;
  976. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  977. reg = xhci_readl(status_reg);
  978. reg = xhci_port_state_to_neutral(reg);
  979. switch (le16_to_cpu(req->value)) {
  980. case USB_PORT_FEAT_ENABLE:
  981. reg &= ~PORT_PE;
  982. break;
  983. case USB_PORT_FEAT_POWER:
  984. reg &= ~PORT_POWER;
  985. break;
  986. case USB_PORT_FEAT_C_RESET:
  987. case USB_PORT_FEAT_C_CONNECTION:
  988. case USB_PORT_FEAT_C_OVER_CURRENT:
  989. case USB_PORT_FEAT_C_ENABLE:
  990. xhci_clear_port_change_bit((le16_to_cpu(req->value)),
  991. le16_to_cpu(req->index),
  992. status_reg, reg);
  993. break;
  994. default:
  995. printf("unknown feature %x\n", le16_to_cpu(req->value));
  996. goto unknown;
  997. }
  998. xhci_writel(status_reg, reg);
  999. break;
  1000. default:
  1001. puts("Unknown request\n");
  1002. goto unknown;
  1003. }
  1004. debug("scrlen = %d\n req->length = %d\n",
  1005. srclen, le16_to_cpu(req->length));
  1006. len = min(srclen, (int)le16_to_cpu(req->length));
  1007. if (srcptr != NULL && len > 0)
  1008. memcpy(buffer, srcptr, len);
  1009. else
  1010. debug("Len is 0\n");
  1011. udev->act_len = len;
  1012. udev->status = 0;
  1013. return 0;
  1014. unknown:
  1015. udev->act_len = 0;
  1016. udev->status = USB_ST_STALLED;
  1017. return -ENODEV;
  1018. }
  1019. /**
  1020. * Submits the INT request to XHCI Host cotroller
  1021. *
  1022. * @param udev pointer to the USB device
  1023. * @param pipe contains the DIR_IN or OUT , devnum
  1024. * @param buffer buffer to be read/written based on the request
  1025. * @param length length of the buffer
  1026. * @param interval interval of the interrupt
  1027. * @return 0
  1028. */
  1029. static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
  1030. void *buffer, int length, int interval,
  1031. bool nonblock)
  1032. {
  1033. if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
  1034. printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
  1035. return -EINVAL;
  1036. }
  1037. /*
  1038. * xHCI uses normal TRBs for both bulk and interrupt. When the
  1039. * interrupt endpoint is to be serviced, the xHC will consume
  1040. * (at most) one TD. A TD (comprised of sg list entries) can
  1041. * take several service intervals to transmit.
  1042. */
  1043. return xhci_bulk_tx(udev, pipe, length, buffer);
  1044. }
  1045. /**
  1046. * submit the BULK type of request to the USB Device
  1047. *
  1048. * @param udev pointer to the USB device
  1049. * @param pipe contains the DIR_IN or OUT , devnum
  1050. * @param buffer buffer to be read/written based on the request
  1051. * @param length length of the buffer
  1052. * @return returns 0 if successful else -1 on failure
  1053. */
  1054. static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
  1055. void *buffer, int length)
  1056. {
  1057. if (usb_pipetype(pipe) != PIPE_BULK) {
  1058. printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  1059. return -EINVAL;
  1060. }
  1061. return xhci_bulk_tx(udev, pipe, length, buffer);
  1062. }
  1063. /**
  1064. * submit the control type of request to the Root hub/Device based on the devnum
  1065. *
  1066. * @param udev pointer to the USB device
  1067. * @param pipe contains the DIR_IN or OUT , devnum
  1068. * @param buffer buffer to be read/written based on the request
  1069. * @param length length of the buffer
  1070. * @param setup Request type
  1071. * @param root_portnr Root port number that this device is on
  1072. * @return returns 0 if successful else -1 on failure
  1073. */
  1074. static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1075. void *buffer, int length,
  1076. struct devrequest *setup, int root_portnr)
  1077. {
  1078. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  1079. int ret = 0;
  1080. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  1081. printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
  1082. return -EINVAL;
  1083. }
  1084. if (usb_pipedevice(pipe) == ctrl->rootdev)
  1085. return xhci_submit_root(udev, pipe, buffer, setup);
  1086. if (setup->request == USB_REQ_SET_ADDRESS &&
  1087. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  1088. return xhci_address_device(udev, root_portnr);
  1089. if (setup->request == USB_REQ_SET_CONFIGURATION &&
  1090. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  1091. ret = xhci_set_configuration(udev);
  1092. if (ret) {
  1093. puts("Failed to configure xHCI endpoint\n");
  1094. return ret;
  1095. }
  1096. }
  1097. return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
  1098. }
  1099. static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
  1100. {
  1101. struct xhci_hccr *hccr;
  1102. struct xhci_hcor *hcor;
  1103. uint32_t val;
  1104. uint32_t val2;
  1105. uint32_t reg;
  1106. hccr = ctrl->hccr;
  1107. hcor = ctrl->hcor;
  1108. /*
  1109. * Program the Number of Device Slots Enabled field in the CONFIG
  1110. * register with the max value of slots the HC can handle.
  1111. */
  1112. val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
  1113. val2 = xhci_readl(&hcor->or_config);
  1114. val |= (val2 & ~HCS_SLOTS_MASK);
  1115. xhci_writel(&hcor->or_config, val);
  1116. /* initializing xhci data structures */
  1117. if (xhci_mem_init(ctrl, hccr, hcor) < 0)
  1118. return -ENOMEM;
  1119. reg = xhci_readl(&hccr->cr_hcsparams1);
  1120. descriptor.hub.bNbrPorts = HCS_MAX_PORTS(reg);
  1121. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  1122. /* Port Indicators */
  1123. reg = xhci_readl(&hccr->cr_hccparams);
  1124. if (HCS_INDICATOR(reg))
  1125. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1126. | 0x80, &descriptor.hub.wHubCharacteristics);
  1127. /* Port Power Control */
  1128. if (HCC_PPC(reg))
  1129. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1130. | 0x01, &descriptor.hub.wHubCharacteristics);
  1131. if (xhci_start(hcor)) {
  1132. xhci_reset(hcor);
  1133. return -ENODEV;
  1134. }
  1135. /* Zero'ing IRQ control register and IRQ pending register */
  1136. xhci_writel(&ctrl->ir_set->irq_control, 0x0);
  1137. xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
  1138. reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
  1139. printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
  1140. ctrl->hci_version = reg;
  1141. return 0;
  1142. }
  1143. static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
  1144. {
  1145. u32 temp;
  1146. xhci_reset(ctrl->hcor);
  1147. debug("// Disabling event ring interrupts\n");
  1148. temp = xhci_readl(&ctrl->hcor->or_usbsts);
  1149. xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
  1150. temp = xhci_readl(&ctrl->ir_set->irq_pending);
  1151. xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
  1152. return 0;
  1153. }
  1154. #if !CONFIG_IS_ENABLED(DM_USB)
  1155. int submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1156. void *buffer, int length, struct devrequest *setup)
  1157. {
  1158. struct usb_device *hop = udev;
  1159. if (hop->parent)
  1160. while (hop->parent->parent)
  1161. hop = hop->parent;
  1162. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1163. hop->portnr);
  1164. }
  1165. int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1166. int length)
  1167. {
  1168. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1169. }
  1170. int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1171. int length, int interval, bool nonblock)
  1172. {
  1173. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
  1174. nonblock);
  1175. }
  1176. /**
  1177. * Intialises the XHCI host controller
  1178. * and allocates the necessary data structures
  1179. *
  1180. * @param index index to the host controller data structure
  1181. * @return pointer to the intialised controller
  1182. */
  1183. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1184. {
  1185. struct xhci_hccr *hccr;
  1186. struct xhci_hcor *hcor;
  1187. struct xhci_ctrl *ctrl;
  1188. int ret;
  1189. *controller = NULL;
  1190. if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
  1191. return -ENODEV;
  1192. if (xhci_reset(hcor) != 0)
  1193. return -ENODEV;
  1194. ctrl = &xhcic[index];
  1195. ctrl->hccr = hccr;
  1196. ctrl->hcor = hcor;
  1197. ret = xhci_lowlevel_init(ctrl);
  1198. if (ret) {
  1199. ctrl->hccr = NULL;
  1200. ctrl->hcor = NULL;
  1201. } else {
  1202. *controller = &xhcic[index];
  1203. }
  1204. return ret;
  1205. }
  1206. /**
  1207. * Stops the XHCI host controller
  1208. * and cleans up all the related data structures
  1209. *
  1210. * @param index index to the host controller data structure
  1211. * @return none
  1212. */
  1213. int usb_lowlevel_stop(int index)
  1214. {
  1215. struct xhci_ctrl *ctrl = (xhcic + index);
  1216. if (ctrl->hcor) {
  1217. xhci_lowlevel_stop(ctrl);
  1218. xhci_hcd_stop(index);
  1219. xhci_cleanup(ctrl);
  1220. }
  1221. return 0;
  1222. }
  1223. #endif /* CONFIG_IS_ENABLED(DM_USB) */
  1224. #if CONFIG_IS_ENABLED(DM_USB)
  1225. static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1226. unsigned long pipe, void *buffer, int length,
  1227. struct devrequest *setup)
  1228. {
  1229. struct usb_device *uhop;
  1230. struct udevice *hub;
  1231. int root_portnr = 0;
  1232. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1233. dev->name, udev, udev->dev->name, udev->portnr);
  1234. hub = udev->dev;
  1235. if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
  1236. /* Figure out our port number on the root hub */
  1237. if (usb_hub_is_root_hub(hub)) {
  1238. root_portnr = udev->portnr;
  1239. } else {
  1240. while (!usb_hub_is_root_hub(hub->parent))
  1241. hub = hub->parent;
  1242. uhop = dev_get_parent_priv(hub);
  1243. root_portnr = uhop->portnr;
  1244. }
  1245. }
  1246. /*
  1247. struct usb_device *hop = udev;
  1248. if (hop->parent)
  1249. while (hop->parent->parent)
  1250. hop = hop->parent;
  1251. */
  1252. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1253. root_portnr);
  1254. }
  1255. static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1256. unsigned long pipe, void *buffer, int length)
  1257. {
  1258. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1259. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1260. }
  1261. static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1262. unsigned long pipe, void *buffer, int length,
  1263. int interval, bool nonblock)
  1264. {
  1265. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1266. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
  1267. nonblock);
  1268. }
  1269. static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
  1270. {
  1271. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1272. return _xhci_alloc_device(udev);
  1273. }
  1274. static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
  1275. {
  1276. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1277. struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
  1278. struct xhci_virt_device *virt_dev;
  1279. struct xhci_input_control_ctx *ctrl_ctx;
  1280. struct xhci_container_ctx *out_ctx;
  1281. struct xhci_container_ctx *in_ctx;
  1282. struct xhci_slot_ctx *slot_ctx;
  1283. int slot_id = udev->slot_id;
  1284. unsigned think_time;
  1285. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1286. /* Ignore root hubs */
  1287. if (usb_hub_is_root_hub(udev->dev))
  1288. return 0;
  1289. virt_dev = ctrl->devs[slot_id];
  1290. BUG_ON(!virt_dev);
  1291. out_ctx = virt_dev->out_ctx;
  1292. in_ctx = virt_dev->in_ctx;
  1293. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  1294. /* Initialize the input context control */
  1295. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  1296. ctrl_ctx->drop_flags = 0;
  1297. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  1298. /* slot context */
  1299. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  1300. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  1301. /* Update hub related fields */
  1302. slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
  1303. /*
  1304. * refer to section 6.2.2: MTT should be 0 for full speed hub,
  1305. * but it may be already set to 1 when setup an xHCI virtual
  1306. * device, so clear it anyway.
  1307. */
  1308. if (hub->tt.multi)
  1309. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  1310. else if (udev->speed == USB_SPEED_FULL)
  1311. slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
  1312. slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
  1313. /*
  1314. * Set TT think time - convert from ns to FS bit times.
  1315. * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
  1316. *
  1317. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  1318. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  1319. *
  1320. * This field shall be 0 if the device is not a high-spped hub.
  1321. */
  1322. think_time = hub->tt.think_time;
  1323. if (think_time != 0)
  1324. think_time = (think_time / 666) - 1;
  1325. if (udev->speed == USB_SPEED_HIGH)
  1326. slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
  1327. slot_ctx->dev_state = 0;
  1328. return xhci_configure_endpoints(udev, false);
  1329. }
  1330. static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
  1331. {
  1332. /*
  1333. * xHCD allocates one segment which includes 64 TRBs for each endpoint
  1334. * and the last TRB in this segment is configured as a link TRB to form
  1335. * a TRB ring. Each TRB can transfer up to 64K bytes, however data
  1336. * buffers referenced by transfer TRBs shall not span 64KB boundaries.
  1337. * Hence the maximum number of TRBs we can use in one transfer is 62.
  1338. */
  1339. *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
  1340. return 0;
  1341. }
  1342. int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
  1343. struct xhci_hcor *hcor)
  1344. {
  1345. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1346. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1347. int ret;
  1348. debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
  1349. ctrl, hccr, hcor);
  1350. ctrl->dev = dev;
  1351. ret = xhci_reset_hw(ctrl);
  1352. if (ret)
  1353. goto err;
  1354. /*
  1355. * XHCI needs to issue a Address device command to setup
  1356. * proper device context structures, before it can interact
  1357. * with the device. So a get_descriptor will fail before any
  1358. * of that is done for XHCI unlike EHCI.
  1359. */
  1360. priv->desc_before_addr = false;
  1361. ret = xhci_reset(hcor);
  1362. if (ret)
  1363. goto err;
  1364. ctrl->hccr = hccr;
  1365. ctrl->hcor = hcor;
  1366. ret = xhci_lowlevel_init(ctrl);
  1367. if (ret)
  1368. goto err;
  1369. return 0;
  1370. err:
  1371. free(ctrl);
  1372. debug("%s: failed, ret=%d\n", __func__, ret);
  1373. return ret;
  1374. }
  1375. int xhci_deregister(struct udevice *dev)
  1376. {
  1377. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1378. xhci_lowlevel_stop(ctrl);
  1379. xhci_cleanup(ctrl);
  1380. return 0;
  1381. }
  1382. struct dm_usb_ops xhci_usb_ops = {
  1383. .control = xhci_submit_control_msg,
  1384. .bulk = xhci_submit_bulk_msg,
  1385. .interrupt = xhci_submit_int_msg,
  1386. .alloc_device = xhci_alloc_device,
  1387. .update_hub_device = xhci_update_hub_device,
  1388. .get_max_xfer_size = xhci_get_max_xfer_size,
  1389. };
  1390. #endif