board.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  4. * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  5. *
  6. * (C) Copyright 2007-2011
  7. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  8. * Tom Cubie <tangliang@allwinnertech.com>
  9. *
  10. * Some board init for the Allwinner A10-evb board.
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <mmc.h>
  15. #include <axp_pmic.h>
  16. #include <generic-phy.h>
  17. #include <phy-sun4i-usb.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/display.h>
  21. #include <asm/arch/dram.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/mmc.h>
  24. #include <asm/arch/spl.h>
  25. #include <asm/arch/usb_phy.h>
  26. #ifndef CONFIG_ARM64
  27. #include <asm/armv7.h>
  28. #endif
  29. #include <asm/gpio.h>
  30. #include <asm/io.h>
  31. #include <crc.h>
  32. #include <environment.h>
  33. #include <linux/libfdt.h>
  34. #include <nand.h>
  35. #include <net.h>
  36. #include <spl.h>
  37. #include <sy8106a.h>
  38. #include <asm/setup.h>
  39. #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
  40. /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
  41. int soft_i2c_gpio_sda;
  42. int soft_i2c_gpio_scl;
  43. static int soft_i2c_board_init(void)
  44. {
  45. int ret;
  46. soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
  47. if (soft_i2c_gpio_sda < 0) {
  48. printf("Error invalid soft i2c sda pin: '%s', err %d\n",
  49. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
  50. return soft_i2c_gpio_sda;
  51. }
  52. ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
  53. if (ret) {
  54. printf("Error requesting soft i2c sda pin: '%s', err %d\n",
  55. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
  56. return ret;
  57. }
  58. soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
  59. if (soft_i2c_gpio_scl < 0) {
  60. printf("Error invalid soft i2c scl pin: '%s', err %d\n",
  61. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
  62. return soft_i2c_gpio_scl;
  63. }
  64. ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
  65. if (ret) {
  66. printf("Error requesting soft i2c scl pin: '%s', err %d\n",
  67. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
  68. return ret;
  69. }
  70. return 0;
  71. }
  72. #else
  73. static int soft_i2c_board_init(void) { return 0; }
  74. #endif
  75. DECLARE_GLOBAL_DATA_PTR;
  76. void i2c_init_board(void)
  77. {
  78. #ifdef CONFIG_I2C0_ENABLE
  79. #if defined(CONFIG_MACH_SUN4I) || \
  80. defined(CONFIG_MACH_SUN5I) || \
  81. defined(CONFIG_MACH_SUN7I) || \
  82. defined(CONFIG_MACH_SUN8I_R40)
  83. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
  84. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
  85. clock_twi_onoff(0, 1);
  86. #elif defined(CONFIG_MACH_SUN6I)
  87. sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
  88. sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
  89. clock_twi_onoff(0, 1);
  90. #elif defined(CONFIG_MACH_SUN8I)
  91. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
  92. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
  93. clock_twi_onoff(0, 1);
  94. #endif
  95. #endif
  96. #ifdef CONFIG_I2C1_ENABLE
  97. #if defined(CONFIG_MACH_SUN4I) || \
  98. defined(CONFIG_MACH_SUN7I) || \
  99. defined(CONFIG_MACH_SUN8I_R40)
  100. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
  101. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
  102. clock_twi_onoff(1, 1);
  103. #elif defined(CONFIG_MACH_SUN5I)
  104. sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
  105. sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
  106. clock_twi_onoff(1, 1);
  107. #elif defined(CONFIG_MACH_SUN6I)
  108. sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
  109. sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
  110. clock_twi_onoff(1, 1);
  111. #elif defined(CONFIG_MACH_SUN8I)
  112. sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
  113. sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
  114. clock_twi_onoff(1, 1);
  115. #endif
  116. #endif
  117. #ifdef CONFIG_I2C2_ENABLE
  118. #if defined(CONFIG_MACH_SUN4I) || \
  119. defined(CONFIG_MACH_SUN7I) || \
  120. defined(CONFIG_MACH_SUN8I_R40)
  121. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
  122. sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
  123. clock_twi_onoff(2, 1);
  124. #elif defined(CONFIG_MACH_SUN5I)
  125. sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
  126. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
  127. clock_twi_onoff(2, 1);
  128. #elif defined(CONFIG_MACH_SUN6I)
  129. sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
  130. sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
  131. clock_twi_onoff(2, 1);
  132. #elif defined(CONFIG_MACH_SUN8I)
  133. sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
  134. sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
  135. clock_twi_onoff(2, 1);
  136. #endif
  137. #endif
  138. #ifdef CONFIG_I2C3_ENABLE
  139. #if defined(CONFIG_MACH_SUN6I)
  140. sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
  141. sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
  142. clock_twi_onoff(3, 1);
  143. #elif defined(CONFIG_MACH_SUN7I) || \
  144. defined(CONFIG_MACH_SUN8I_R40)
  145. sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
  146. sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
  147. clock_twi_onoff(3, 1);
  148. #endif
  149. #endif
  150. #ifdef CONFIG_I2C4_ENABLE
  151. #if defined(CONFIG_MACH_SUN7I) || \
  152. defined(CONFIG_MACH_SUN8I_R40)
  153. sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
  154. sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
  155. clock_twi_onoff(4, 1);
  156. #endif
  157. #endif
  158. #ifdef CONFIG_R_I2C_ENABLE
  159. clock_twi_onoff(5, 1);
  160. sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
  161. sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
  162. #endif
  163. }
  164. #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
  165. enum env_location env_get_location(enum env_operation op, int prio)
  166. {
  167. switch (prio) {
  168. case 0:
  169. return ENVL_FAT;
  170. case 1:
  171. return ENVL_MMC;
  172. default:
  173. return ENVL_UNKNOWN;
  174. }
  175. }
  176. #endif
  177. /* add board specific code here */
  178. int board_init(void)
  179. {
  180. __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
  181. gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  182. #ifndef CONFIG_ARM64
  183. asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  184. debug("id_pfr1: 0x%08x\n", id_pfr1);
  185. /* Generic Timer Extension available? */
  186. if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
  187. uint32_t freq;
  188. debug("Setting CNTFRQ\n");
  189. /*
  190. * CNTFRQ is a secure register, so we will crash if we try to
  191. * write this from the non-secure world (read is OK, though).
  192. * In case some bootcode has already set the correct value,
  193. * we avoid the risk of writing to it.
  194. */
  195. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
  196. if (freq != COUNTER_FREQUENCY) {
  197. debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
  198. freq, COUNTER_FREQUENCY);
  199. #ifdef CONFIG_NON_SECURE
  200. printf("arch timer frequency is wrong, but cannot adjust it\n");
  201. #else
  202. asm volatile("mcr p15, 0, %0, c14, c0, 0"
  203. : : "r"(COUNTER_FREQUENCY));
  204. #endif
  205. }
  206. }
  207. #endif /* !CONFIG_ARM64 */
  208. ret = axp_gpio_init();
  209. if (ret)
  210. return ret;
  211. #ifdef CONFIG_SATAPWR
  212. satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
  213. gpio_request(satapwr_pin, "satapwr");
  214. gpio_direction_output(satapwr_pin, 1);
  215. /* Give attached sata device time to power-up to avoid link timeouts */
  216. mdelay(500);
  217. #endif
  218. #ifdef CONFIG_MACPWR
  219. macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
  220. gpio_request(macpwr_pin, "macpwr");
  221. gpio_direction_output(macpwr_pin, 1);
  222. #endif
  223. #ifdef CONFIG_DM_I2C
  224. /*
  225. * Temporary workaround for enabling I2C clocks until proper sunxi DM
  226. * clk, reset and pinctrl drivers land.
  227. */
  228. i2c_init_board();
  229. #endif
  230. /* Uses dm gpio code so do this here and not in i2c_init_board() */
  231. return soft_i2c_board_init();
  232. }
  233. int dram_init(void)
  234. {
  235. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
  236. return 0;
  237. }
  238. #if defined(CONFIG_NAND_SUNXI)
  239. static void nand_pinmux_setup(void)
  240. {
  241. unsigned int pin;
  242. for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
  243. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  244. #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
  245. for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
  246. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  247. #endif
  248. /* sun4i / sun7i do have a PC23, but it is not used for nand,
  249. * only sun7i has a PC24 */
  250. #ifdef CONFIG_MACH_SUN7I
  251. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
  252. #endif
  253. }
  254. static void nand_clock_setup(void)
  255. {
  256. struct sunxi_ccm_reg *const ccm =
  257. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  258. setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
  259. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
  260. defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
  261. setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
  262. #endif
  263. setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
  264. }
  265. void board_nand_init(void)
  266. {
  267. nand_pinmux_setup();
  268. nand_clock_setup();
  269. #ifndef CONFIG_SPL_BUILD
  270. sunxi_nand_init();
  271. #endif
  272. }
  273. #endif
  274. #ifdef CONFIG_MMC
  275. static void mmc_pinmux_setup(int sdc)
  276. {
  277. unsigned int pin;
  278. __maybe_unused int pins;
  279. switch (sdc) {
  280. case 0:
  281. /* SDC0: PF0-PF5 */
  282. for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
  283. sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
  284. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  285. sunxi_gpio_set_drv(pin, 2);
  286. }
  287. break;
  288. case 1:
  289. pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
  290. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  291. defined(CONFIG_MACH_SUN8I_R40)
  292. if (pins == SUNXI_GPIO_H) {
  293. /* SDC1: PH22-PH-27 */
  294. for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  295. sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
  296. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  297. sunxi_gpio_set_drv(pin, 2);
  298. }
  299. } else {
  300. /* SDC1: PG0-PG5 */
  301. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  302. sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
  303. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  304. sunxi_gpio_set_drv(pin, 2);
  305. }
  306. }
  307. #elif defined(CONFIG_MACH_SUN5I)
  308. /* SDC1: PG3-PG8 */
  309. for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
  310. sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
  311. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  312. sunxi_gpio_set_drv(pin, 2);
  313. }
  314. #elif defined(CONFIG_MACH_SUN6I)
  315. /* SDC1: PG0-PG5 */
  316. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  317. sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
  318. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  319. sunxi_gpio_set_drv(pin, 2);
  320. }
  321. #elif defined(CONFIG_MACH_SUN8I)
  322. if (pins == SUNXI_GPIO_D) {
  323. /* SDC1: PD2-PD7 */
  324. for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
  325. sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
  326. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  327. sunxi_gpio_set_drv(pin, 2);
  328. }
  329. } else {
  330. /* SDC1: PG0-PG5 */
  331. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  332. sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
  333. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  334. sunxi_gpio_set_drv(pin, 2);
  335. }
  336. }
  337. #endif
  338. break;
  339. case 2:
  340. pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
  341. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  342. /* SDC2: PC6-PC11 */
  343. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
  344. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  345. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  346. sunxi_gpio_set_drv(pin, 2);
  347. }
  348. #elif defined(CONFIG_MACH_SUN5I)
  349. if (pins == SUNXI_GPIO_E) {
  350. /* SDC2: PE4-PE9 */
  351. for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
  352. sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
  353. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  354. sunxi_gpio_set_drv(pin, 2);
  355. }
  356. } else {
  357. /* SDC2: PC6-PC15 */
  358. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  359. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  360. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  361. sunxi_gpio_set_drv(pin, 2);
  362. }
  363. }
  364. #elif defined(CONFIG_MACH_SUN6I)
  365. if (pins == SUNXI_GPIO_A) {
  366. /* SDC2: PA9-PA14 */
  367. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  368. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
  369. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  370. sunxi_gpio_set_drv(pin, 2);
  371. }
  372. } else {
  373. /* SDC2: PC6-PC15, PC24 */
  374. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  375. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  376. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  377. sunxi_gpio_set_drv(pin, 2);
  378. }
  379. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  380. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  381. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  382. }
  383. #elif defined(CONFIG_MACH_SUN8I_R40)
  384. /* SDC2: PC6-PC15, PC24 */
  385. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  386. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  387. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  388. sunxi_gpio_set_drv(pin, 2);
  389. }
  390. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  391. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  392. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  393. #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
  394. /* SDC2: PC5-PC6, PC8-PC16 */
  395. for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
  396. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  397. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  398. sunxi_gpio_set_drv(pin, 2);
  399. }
  400. for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
  401. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  402. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  403. sunxi_gpio_set_drv(pin, 2);
  404. }
  405. #elif defined(CONFIG_MACH_SUN9I)
  406. /* SDC2: PC6-PC16 */
  407. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
  408. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  409. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  410. sunxi_gpio_set_drv(pin, 2);
  411. }
  412. #endif
  413. break;
  414. case 3:
  415. pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
  416. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  417. defined(CONFIG_MACH_SUN8I_R40)
  418. /* SDC3: PI4-PI9 */
  419. for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
  420. sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
  421. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  422. sunxi_gpio_set_drv(pin, 2);
  423. }
  424. #elif defined(CONFIG_MACH_SUN6I)
  425. if (pins == SUNXI_GPIO_A) {
  426. /* SDC3: PA9-PA14 */
  427. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  428. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
  429. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  430. sunxi_gpio_set_drv(pin, 2);
  431. }
  432. } else {
  433. /* SDC3: PC6-PC15, PC24 */
  434. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  435. sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
  436. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  437. sunxi_gpio_set_drv(pin, 2);
  438. }
  439. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
  440. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  441. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  442. }
  443. #endif
  444. break;
  445. default:
  446. printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
  447. break;
  448. }
  449. }
  450. int board_mmc_init(bd_t *bis)
  451. {
  452. __maybe_unused struct mmc *mmc0, *mmc1;
  453. __maybe_unused char buf[512];
  454. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  455. mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
  456. if (!mmc0)
  457. return -1;
  458. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  459. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  460. mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  461. if (!mmc1)
  462. return -1;
  463. #endif
  464. return 0;
  465. }
  466. #endif
  467. #ifdef CONFIG_SPL_BUILD
  468. void sunxi_board_init(void)
  469. {
  470. int power_failed = 0;
  471. #ifdef CONFIG_SY8106A_POWER
  472. power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
  473. #endif
  474. #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
  475. defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  476. defined CONFIG_AXP818_POWER
  477. power_failed = axp_init();
  478. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  479. defined CONFIG_AXP818_POWER
  480. power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
  481. #endif
  482. power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
  483. power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
  484. #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
  485. power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
  486. #endif
  487. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  488. defined CONFIG_AXP818_POWER
  489. power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
  490. #endif
  491. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  492. defined CONFIG_AXP818_POWER
  493. power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
  494. #endif
  495. power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
  496. #if !defined(CONFIG_AXP152_POWER)
  497. power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
  498. #endif
  499. #ifdef CONFIG_AXP209_POWER
  500. power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
  501. #endif
  502. #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
  503. defined(CONFIG_AXP818_POWER)
  504. power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
  505. power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
  506. #if !defined CONFIG_AXP809_POWER
  507. power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
  508. power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
  509. #endif
  510. power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
  511. power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
  512. power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
  513. #endif
  514. #ifdef CONFIG_AXP818_POWER
  515. power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
  516. power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
  517. power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
  518. #endif
  519. #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
  520. power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
  521. #endif
  522. #endif
  523. printf("DRAM:");
  524. gd->ram_size = sunxi_dram_init();
  525. printf(" %d MiB\n", (int)(gd->ram_size >> 20));
  526. if (!gd->ram_size)
  527. hang();
  528. /*
  529. * Only clock up the CPU to full speed if we are reasonably
  530. * assured it's being powered with suitable core voltage
  531. */
  532. if (!power_failed)
  533. clock_set_pll1(CONFIG_SYS_CLK_FREQ);
  534. else
  535. printf("Failed to set core voltage! Can't set CPU frequency\n");
  536. }
  537. #endif
  538. #ifdef CONFIG_USB_GADGET
  539. int g_dnl_board_usb_cable_connected(void)
  540. {
  541. struct udevice *dev;
  542. struct phy phy;
  543. int ret;
  544. ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev);
  545. if (ret) {
  546. pr_err("%s: Cannot find USB device\n", __func__);
  547. return ret;
  548. }
  549. ret = generic_phy_get_by_name(dev, "usb", &phy);
  550. if (ret) {
  551. pr_err("failed to get %s USB PHY\n", dev->name);
  552. return ret;
  553. }
  554. ret = generic_phy_init(&phy);
  555. if (ret) {
  556. pr_err("failed to init %s USB PHY\n", dev->name);
  557. return ret;
  558. }
  559. ret = sun4i_usb_phy_vbus_detect(&phy);
  560. if (ret == 1) {
  561. pr_err("A charger is plugged into the OTG\n");
  562. return -ENODEV;
  563. }
  564. return ret;
  565. }
  566. #endif
  567. #ifdef CONFIG_SERIAL_TAG
  568. void get_board_serial(struct tag_serialnr *serialnr)
  569. {
  570. char *serial_string;
  571. unsigned long long serial;
  572. serial_string = env_get("serial#");
  573. if (serial_string) {
  574. serial = simple_strtoull(serial_string, NULL, 16);
  575. serialnr->high = (unsigned int) (serial >> 32);
  576. serialnr->low = (unsigned int) (serial & 0xffffffff);
  577. } else {
  578. serialnr->high = 0;
  579. serialnr->low = 0;
  580. }
  581. }
  582. #endif
  583. /*
  584. * Check the SPL header for the "sunxi" variant. If found: parse values
  585. * that might have been passed by the loader ("fel" utility), and update
  586. * the environment accordingly.
  587. */
  588. static void parse_spl_header(const uint32_t spl_addr)
  589. {
  590. struct boot_file_head *spl = (void *)(ulong)spl_addr;
  591. if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
  592. return; /* signature mismatch, no usable header */
  593. uint8_t spl_header_version = spl->spl_signature[3];
  594. if (spl_header_version != SPL_HEADER_VERSION) {
  595. printf("sunxi SPL version mismatch: expected %u, got %u\n",
  596. SPL_HEADER_VERSION, spl_header_version);
  597. return;
  598. }
  599. if (!spl->fel_script_address)
  600. return;
  601. if (spl->fel_uEnv_length != 0) {
  602. /*
  603. * data is expected in uEnv.txt compatible format, so "env
  604. * import -t" the string(s) at fel_script_address right away.
  605. */
  606. himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
  607. spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
  608. return;
  609. }
  610. /* otherwise assume .scr format (mkimage-type script) */
  611. env_set_hex("fel_scriptaddr", spl->fel_script_address);
  612. }
  613. /*
  614. * Note this function gets called multiple times.
  615. * It must not make any changes to env variables which already exist.
  616. */
  617. static void setup_environment(const void *fdt)
  618. {
  619. char serial_string[17] = { 0 };
  620. unsigned int sid[4];
  621. uint8_t mac_addr[6];
  622. char ethaddr[16];
  623. int i, ret;
  624. ret = sunxi_get_sid(sid);
  625. if (ret == 0 && sid[0] != 0) {
  626. /*
  627. * The single words 1 - 3 of the SID have quite a few bits
  628. * which are the same on many models, so we take a crc32
  629. * of all 3 words, to get a more unique value.
  630. *
  631. * Note we only do this on newer SoCs as we cannot change
  632. * the algorithm on older SoCs since those have been using
  633. * fixed mac-addresses based on only using word 3 for a
  634. * long time and changing a fixed mac-address with an
  635. * u-boot update is not good.
  636. */
  637. #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
  638. !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
  639. !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
  640. sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
  641. #endif
  642. /* Ensure the NIC specific bytes of the mac are not all 0 */
  643. if ((sid[3] & 0xffffff) == 0)
  644. sid[3] |= 0x800000;
  645. for (i = 0; i < 4; i++) {
  646. sprintf(ethaddr, "ethernet%d", i);
  647. if (!fdt_get_alias(fdt, ethaddr))
  648. continue;
  649. if (i == 0)
  650. strcpy(ethaddr, "ethaddr");
  651. else
  652. sprintf(ethaddr, "eth%daddr", i);
  653. if (env_get(ethaddr))
  654. continue;
  655. /* Non OUI / registered MAC address */
  656. mac_addr[0] = (i << 4) | 0x02;
  657. mac_addr[1] = (sid[0] >> 0) & 0xff;
  658. mac_addr[2] = (sid[3] >> 24) & 0xff;
  659. mac_addr[3] = (sid[3] >> 16) & 0xff;
  660. mac_addr[4] = (sid[3] >> 8) & 0xff;
  661. mac_addr[5] = (sid[3] >> 0) & 0xff;
  662. eth_env_set_enetaddr(ethaddr, mac_addr);
  663. }
  664. if (!env_get("serial#")) {
  665. snprintf(serial_string, sizeof(serial_string),
  666. "%08x%08x", sid[0], sid[3]);
  667. env_set("serial#", serial_string);
  668. }
  669. }
  670. }
  671. int misc_init_r(void)
  672. {
  673. __maybe_unused int ret;
  674. uint boot;
  675. env_set("fel_booted", NULL);
  676. env_set("fel_scriptaddr", NULL);
  677. env_set("mmc_bootdev", NULL);
  678. boot = sunxi_get_boot_device();
  679. /* determine if we are running in FEL mode */
  680. if (boot == BOOT_DEVICE_BOARD) {
  681. env_set("fel_booted", "1");
  682. parse_spl_header(SPL_ADDR);
  683. /* or if we booted from MMC, and which one */
  684. } else if (boot == BOOT_DEVICE_MMC1) {
  685. env_set("mmc_bootdev", "0");
  686. } else if (boot == BOOT_DEVICE_MMC2) {
  687. env_set("mmc_bootdev", "1");
  688. }
  689. setup_environment(gd->fdt_blob);
  690. #ifndef CONFIG_MACH_SUN9I
  691. ret = sunxi_usb_phy_probe();
  692. if (ret)
  693. return ret;
  694. #endif
  695. #ifdef CONFIG_USB_ETHER
  696. usb_ether_init();
  697. #endif
  698. return 0;
  699. }
  700. int ft_board_setup(void *blob, bd_t *bd)
  701. {
  702. int __maybe_unused r;
  703. /*
  704. * Call setup_environment again in case the boot fdt has
  705. * ethernet aliases the u-boot copy does not have.
  706. */
  707. setup_environment(blob);
  708. #ifdef CONFIG_VIDEO_DT_SIMPLEFB
  709. r = sunxi_simplefb_setup(blob);
  710. if (r)
  711. return r;
  712. #endif
  713. return 0;
  714. }
  715. #ifdef CONFIG_SPL_LOAD_FIT
  716. int board_fit_config_name_match(const char *name)
  717. {
  718. struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
  719. const char *cmp_str = (void *)(ulong)SPL_ADDR;
  720. /* Check if there is a DT name stored in the SPL header and use that. */
  721. if (spl->dt_name_offset) {
  722. cmp_str += spl->dt_name_offset;
  723. } else {
  724. #ifdef CONFIG_DEFAULT_DEVICE_TREE
  725. cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
  726. #else
  727. return 0;
  728. #endif
  729. };
  730. /* Differentiate the two Pine64 board DTs by their DRAM size. */
  731. if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
  732. if ((gd->ram_size > 512 * 1024 * 1024))
  733. return !strstr(name, "plus");
  734. else
  735. return !!strstr(name, "plus");
  736. } else {
  737. return strcmp(name, cmp_str);
  738. }
  739. }
  740. #endif