mv_ddr_topology.h 8.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #ifndef _MV_DDR_TOPOLOGY_H
  6. #define _MV_DDR_TOPOLOGY_H
  7. #define MAX_CS_NUM 4
  8. enum mv_ddr_speed_bin {
  9. SPEED_BIN_DDR_800D,
  10. SPEED_BIN_DDR_800E,
  11. SPEED_BIN_DDR_1066E,
  12. SPEED_BIN_DDR_1066F,
  13. SPEED_BIN_DDR_1066G,
  14. SPEED_BIN_DDR_1333F,
  15. SPEED_BIN_DDR_1333G,
  16. SPEED_BIN_DDR_1333H,
  17. SPEED_BIN_DDR_1333J,
  18. SPEED_BIN_DDR_1600G,
  19. SPEED_BIN_DDR_1600H,
  20. SPEED_BIN_DDR_1600J,
  21. SPEED_BIN_DDR_1600K,
  22. SPEED_BIN_DDR_1866J,
  23. SPEED_BIN_DDR_1866K,
  24. SPEED_BIN_DDR_1866L,
  25. SPEED_BIN_DDR_1866M,
  26. SPEED_BIN_DDR_2133K,
  27. SPEED_BIN_DDR_2133L,
  28. SPEED_BIN_DDR_2133M,
  29. SPEED_BIN_DDR_2133N,
  30. SPEED_BIN_DDR_1333H_EXT,
  31. SPEED_BIN_DDR_1600K_EXT,
  32. SPEED_BIN_DDR_1866M_EXT
  33. };
  34. enum mv_ddr_freq {
  35. MV_DDR_FREQ_LOW_FREQ,
  36. MV_DDR_FREQ_400,
  37. MV_DDR_FREQ_533,
  38. MV_DDR_FREQ_667,
  39. MV_DDR_FREQ_800,
  40. MV_DDR_FREQ_933,
  41. MV_DDR_FREQ_1066,
  42. MV_DDR_FREQ_311,
  43. MV_DDR_FREQ_333,
  44. MV_DDR_FREQ_467,
  45. MV_DDR_FREQ_850,
  46. MV_DDR_FREQ_600,
  47. MV_DDR_FREQ_300,
  48. MV_DDR_FREQ_900,
  49. MV_DDR_FREQ_360,
  50. MV_DDR_FREQ_1000,
  51. MV_DDR_FREQ_LAST,
  52. MV_DDR_FREQ_SAR
  53. };
  54. enum mv_ddr_speed_bin_timing {
  55. SPEED_BIN_TRCD,
  56. SPEED_BIN_TRP,
  57. SPEED_BIN_TRAS,
  58. SPEED_BIN_TRC,
  59. SPEED_BIN_TRRD1K,
  60. SPEED_BIN_TRRD2K,
  61. SPEED_BIN_TPD,
  62. SPEED_BIN_TFAW1K,
  63. SPEED_BIN_TFAW2K,
  64. SPEED_BIN_TWTR,
  65. SPEED_BIN_TRTP,
  66. SPEED_BIN_TWR,
  67. SPEED_BIN_TMOD,
  68. SPEED_BIN_TXPDLL,
  69. SPEED_BIN_TXSDLL
  70. };
  71. /* ddr bus masks */
  72. #define BUS_MASK_32BIT 0xf
  73. #define BUS_MASK_32BIT_ECC 0x1f
  74. #define BUS_MASK_16BIT 0x3
  75. #define BUS_MASK_16BIT_ECC 0x13
  76. #define BUS_MASK_16BIT_ECC_PUP3 0xb
  77. #define MV_DDR_64BIT_BUS_MASK 0xff
  78. #define MV_DDR_64BIT_ECC_PUP8_BUS_MASK 0x1ff
  79. #define MV_DDR_32BIT_ECC_PUP8_BUS_MASK 0x10f
  80. #define MV_DDR_CS_BITMASK_1CS 0x1
  81. #define MV_DDR_CS_BITMASK_2CS 0x3
  82. #define MV_DDR_ONE_SPHY_PER_DUNIT 1
  83. #define MV_DDR_TWO_SPHY_PER_DUNIT 2
  84. /* source of ddr configuration data */
  85. enum mv_ddr_cfg_src {
  86. MV_DDR_CFG_DEFAULT, /* based on data in mv_ddr_topology_map structure */
  87. MV_DDR_CFG_SPD, /* based on data in spd */
  88. MV_DDR_CFG_USER, /* based on data from user */
  89. MV_DDR_CFG_STATIC, /* based on data from user in register-value format */
  90. MV_DDR_CFG_LAST
  91. };
  92. enum mv_ddr_temperature {
  93. MV_DDR_TEMP_LOW,
  94. MV_DDR_TEMP_NORMAL,
  95. MV_DDR_TEMP_HIGH
  96. };
  97. enum mv_ddr_timing {
  98. MV_DDR_TIM_DEFAULT,
  99. MV_DDR_TIM_1T,
  100. MV_DDR_TIM_2T
  101. };
  102. enum mv_ddr_timing_data {
  103. MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
  104. MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */
  105. MV_DDR_TRFC1_MIN, /* min refresh recovery delay time (t rfc1 min) */
  106. MV_DDR_TWR_MIN, /* min write recovery time (t wr min) */
  107. MV_DDR_TRCD_MIN, /* min ras to cas delay time (t rcd min) */
  108. MV_DDR_TRP_MIN, /* min row precharge delay time (t rp min) */
  109. MV_DDR_TRC_MIN, /* min active to active/refresh delay time (t rc min) */
  110. MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */
  111. MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */
  112. MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */
  113. MV_DDR_TCCD_L_MIN, /* min cas to cas delay time (t ccd_l min), same bank group */
  114. MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */
  115. MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */
  116. MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */
  117. MV_DDR_TDATA_LAST
  118. };
  119. enum mv_ddr_electrical_data {
  120. MV_DDR_CK_DLY,
  121. MV_DDR_PHY_REG3,
  122. MV_DDR_ZPRI_DATA,
  123. MV_DDR_ZNRI_DATA,
  124. MV_DDR_ZPRI_CTRL,
  125. MV_DDR_ZNRI_CTRL,
  126. MV_DDR_ZPODT_DATA,
  127. MV_DDR_ZNODT_DATA,
  128. MV_DDR_ZPODT_CTRL,
  129. MV_DDR_ZNODT_CTRL,
  130. MV_DDR_DIC,
  131. MV_DDR_ODT_CFG,
  132. MV_DDR_RTT_NOM,
  133. MV_DDR_RTT_WR,
  134. MV_DDR_RTT_PARK,
  135. MV_DDR_EDATA_LAST
  136. };
  137. /* memory electrical configuration values */
  138. enum mv_ddr_rtt_nom_park_evalue {
  139. MV_DDR_RTT_NOM_PARK_RZQ_DISABLE,
  140. MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* 60-Ohm; RZQ = 240-Ohm */
  141. MV_DDR_RTT_NOM_PARK_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */
  142. MV_DDR_RTT_NOM_PARK_RZQ_DIV6, /* 40-Ohm; RZQ = 240-Ohm */
  143. MV_DDR_RTT_NOM_PARK_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */
  144. MV_DDR_RTT_NOM_PARK_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */
  145. MV_DDR_RTT_NOM_PARK_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */
  146. MV_DDR_RTT_NOM_PARK_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */
  147. MV_DDR_RTT_NOM_PARK_RZQ_LAST
  148. };
  149. enum mv_ddr_rtt_wr_evalue {
  150. MV_DDR_RTT_WR_DYN_ODT_OFF,
  151. MV_DDR_RTT_WR_RZQ_DIV2, /* 120-Ohm; RZQ = 240-Ohm */
  152. MV_DDR_RTT_WR_RZQ_DIV1, /* 240-Ohm; RZQ = 240-Ohm */
  153. MV_DDR_RTT_WR_HIZ,
  154. MV_DDR_RTT_WR_RZQ_DIV3, /* 80-Ohm; RZQ = 240-Ohm */
  155. MV_DDR_RTT_WR_RZQ_LAST
  156. };
  157. enum mv_ddr_dic_evalue {
  158. MV_DDR_DIC_RZQ_DIV7, /* 34-Ohm; RZQ = 240-Ohm */
  159. MV_DDR_DIC_RZQ_DIV5, /* 48-Ohm; RZQ = 240-Ohm */
  160. MV_DDR_DIC_RZQ_LAST
  161. };
  162. /* phy electrical configuration values */
  163. enum mv_ddr_ohm_evalue {
  164. MV_DDR_OHM_30 = 30,
  165. MV_DDR_OHM_48 = 48,
  166. MV_DDR_OHM_60 = 60,
  167. MV_DDR_OHM_80 = 80,
  168. MV_DDR_OHM_120 = 120,
  169. MV_DDR_OHM_240 = 240,
  170. MV_DDR_OHM_LAST
  171. };
  172. /* mac electrical configuration values */
  173. enum mv_ddr_odt_cfg_evalue {
  174. MV_DDR_ODT_CFG_NORMAL,
  175. MV_DDR_ODT_CFG_ALWAYS_ON,
  176. MV_DDR_ODT_CFG_LAST
  177. };
  178. enum mv_ddr_dev_width { /* sdram device width */
  179. MV_DDR_DEV_WIDTH_4BIT,
  180. MV_DDR_DEV_WIDTH_8BIT,
  181. MV_DDR_DEV_WIDTH_16BIT,
  182. MV_DDR_DEV_WIDTH_32BIT,
  183. MV_DDR_DEV_WIDTH_LAST
  184. };
  185. enum mv_ddr_die_capacity { /* total sdram capacity per die, megabits */
  186. MV_DDR_DIE_CAP_256MBIT,
  187. MV_DDR_DIE_CAP_512MBIT = 0,
  188. MV_DDR_DIE_CAP_1GBIT,
  189. MV_DDR_DIE_CAP_2GBIT,
  190. MV_DDR_DIE_CAP_4GBIT,
  191. MV_DDR_DIE_CAP_8GBIT,
  192. MV_DDR_DIE_CAP_16GBIT,
  193. MV_DDR_DIE_CAP_32GBIT,
  194. MV_DDR_DIE_CAP_12GBIT,
  195. MV_DDR_DIE_CAP_24GBIT,
  196. MV_DDR_DIE_CAP_LAST
  197. };
  198. enum mv_ddr_pkg_rank { /* number of package ranks per dimm */
  199. MV_DDR_PKG_RANK_1,
  200. MV_DDR_PKG_RANK_2,
  201. MV_DDR_PKG_RANK_3,
  202. MV_DDR_PKG_RANK_4,
  203. MV_DDR_PKG_RANK_5,
  204. MV_DDR_PKG_RANK_6,
  205. MV_DDR_PKG_RANK_7,
  206. MV_DDR_PKG_RANK_8,
  207. MV_DDR_PKG_RANK_LAST
  208. };
  209. enum mv_ddr_pri_bus_width { /* number of primary bus width bits */
  210. MV_DDR_PRI_BUS_WIDTH_8,
  211. MV_DDR_PRI_BUS_WIDTH_16,
  212. MV_DDR_PRI_BUS_WIDTH_32,
  213. MV_DDR_PRI_BUS_WIDTH_64,
  214. MV_DDR_PRI_BUS_WIDTH_LAST
  215. };
  216. enum mv_ddr_bus_width_ext { /* number of extension bus width bits */
  217. MV_DDR_BUS_WIDTH_EXT_0,
  218. MV_DDR_BUS_WIDTH_EXT_8,
  219. MV_DDR_BUS_WIDTH_EXT_LAST
  220. };
  221. enum mv_ddr_die_count {
  222. MV_DDR_DIE_CNT_1,
  223. MV_DDR_DIE_CNT_2,
  224. MV_DDR_DIE_CNT_3,
  225. MV_DDR_DIE_CNT_4,
  226. MV_DDR_DIE_CNT_5,
  227. MV_DDR_DIE_CNT_6,
  228. MV_DDR_DIE_CNT_7,
  229. MV_DDR_DIE_CNT_8,
  230. MV_DDR_DIE_CNT_LAST
  231. };
  232. #define IS_ACTIVE(mask, id) \
  233. ((mask) & (1 << (id)))
  234. #define VALIDATE_ACTIVE(mask, id) \
  235. { \
  236. if (IS_ACTIVE(mask, id) == 0) \
  237. continue; \
  238. }
  239. #define IS_IF_ACTIVE(if_mask, if_id) \
  240. ((if_mask) & (1 << (if_id)))
  241. #define VALIDATE_IF_ACTIVE(mask, id) \
  242. { \
  243. if (IS_IF_ACTIVE(mask, id) == 0) \
  244. continue; \
  245. }
  246. #define IS_BUS_ACTIVE(if_mask , if_id) \
  247. (((if_mask) >> (if_id)) & 1)
  248. #define VALIDATE_BUS_ACTIVE(mask, id) \
  249. { \
  250. if (IS_BUS_ACTIVE(mask, id) == 0) \
  251. continue; \
  252. }
  253. #define DDR3_IS_ECC_PUP3_MODE(if_mask) \
  254. (((if_mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
  255. #define DDR3_IS_ECC_PUP4_MODE(if_mask) \
  256. (((if_mask) == BUS_MASK_32BIT_ECC || \
  257. (if_mask) == BUS_MASK_16BIT_ECC) ? 1 : 0)
  258. #define DDR3_IS_16BIT_DRAM_MODE(mask) \
  259. (((mask) == BUS_MASK_16BIT || \
  260. (mask) == BUS_MASK_16BIT_ECC || \
  261. (mask) == BUS_MASK_16BIT_ECC_PUP3) ? 1 : 0)
  262. #define DDR3_IS_ECC_PUP8_MODE(if_mask) \
  263. (((if_mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK || \
  264. (if_mask) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
  265. #define MV_DDR_IS_64BIT_DRAM_MODE(mask) \
  266. ((((mask) & MV_DDR_64BIT_BUS_MASK) == MV_DDR_64BIT_BUS_MASK) || \
  267. (((mask) & MV_DDR_64BIT_ECC_PUP8_BUS_MASK) == MV_DDR_64BIT_ECC_PUP8_BUS_MASK) ? 1 : 0)
  268. #define MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) \
  269. (((sphys) == 9) && \
  270. (((mask) == BUS_MASK_32BIT) || \
  271. ((mask) == MV_DDR_32BIT_ECC_PUP8_BUS_MASK)) ? 1 : 0)
  272. #define MV_DDR_IS_HALF_BUS_DRAM_MODE(mask, sphys) \
  273. (MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(mask, sphys) || \
  274. DDR3_IS_16BIT_DRAM_MODE(mask))
  275. struct mv_ddr_topology_map *mv_ddr_topology_map_get(void);
  276. unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk);
  277. unsigned int mv_ddr_cwl_calc(unsigned int tclk);
  278. int mv_ddr_topology_map_update(void);
  279. unsigned short mv_ddr_bus_bit_mask_get(void);
  280. unsigned int mv_ddr_if_bus_width_get(void);
  281. unsigned int mv_ddr_cs_num_get(void);
  282. int mv_ddr_is_ecc_ena(void);
  283. int mv_ddr_ck_delay_get(void);
  284. unsigned long long mv_ddr_mem_sz_per_cs_get(void);
  285. unsigned long long mv_ddr_mem_sz_get(void);
  286. unsigned int mv_ddr_rtt_nom_get(void);
  287. unsigned int mv_ddr_rtt_park_get(void);
  288. unsigned int mv_ddr_rtt_wr_get(void);
  289. unsigned int mv_ddr_dic_get(void);
  290. #endif /* _MV_DDR_TOPOLOGY_H */